usb: gadget: fotg210: add w1c interrupt status support

Since hardware revision 1.11.0, the following interrupt status registers are now W1C (i.e., write 1 clear): 1. Interrupt Source Group 0 Register (0x144) (EP0 Abort: BIT5) 2. Interrupt Source Group 2 Register (0x14C) (All bits) And before revision 1.11.0, these registers are all R/W. Which means software must write a 0 to clear the status. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Marek Vasut <marex@denx.de>

usb: gadget: fotg210: add w1c interrupt status support
Since hardware revision 1.11.0, the following interrupt status registers are now W1C (i.e., write 1 clear): 1. Interrupt Source Group 0 Register (0x144) (EP0 Abort: BIT5) 2. Interrupt Source Group 2 Register (0x14C) (All bits) And before revision 1.11.0, these registers are all R/W. Which means software must write a 0 to clear the status. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Marek Vasut <marex@denx.de>
Kuo-Jung Su · Marek Vasut
1 parent 7f673c99c2
Showing 1 changed file with 14 additions and 0 deletions Side-by-side Diff
drivers/usb/gadget/fotg210.c
@@ -847,6 +847,13 @@
 	/* CX interrupts */
 	if (gisr & GISR_GRP0) {
 		st = readl(&regs->gisr0);
+		/*
+		 * Write 1 and then 0 works for both W1C & RW.
+		 *
+		 * HW v1.11.0+: It's a W1C register (write 1 clear)
+		 * HW v1.10.0-: It's a R/W register (write 0 clear)
+		 */
+		writel(st & GISR0_CXABORT, &regs->gisr0);
 		writel(0, &regs->gisr0);
  
 		if (st & GISR0_CXERR)
@@ -873,6 +880,13 @@
 	/* Device Status Interrupts */
 	if (gisr & GISR_GRP2) {
 		st = readl(&regs->gisr2);
+		/*
+		 * Write 1 and then 0 works for both W1C & RW.
+		 *
+		 * HW v1.11.0+: It's a W1C register (write 1 clear)
+		 * HW v1.10.0-: It's a R/W register (write 0 clear)
+		 */
+		writel(st, &regs->gisr2);
 		writel(0, &regs->gisr2);
  
 		if (st & GISR2_RESET)
...	...	@@ -847,6 +847,13 @@
847	847	/* CX interrupts */
848	848	if (gisr & GISR_GRP0) {
849	849	st = readl(&regs->gisr0);
	850	+ /*
	851	+ * Write 1 and then 0 works for both W1C & RW.
	852	+ *
	853	+ * HW v1.11.0+: It's a W1C register (write 1 clear)
	854	+ * HW v1.10.0-: It's a R/W register (write 0 clear)
	855	+ */
	856	+ writel(st & GISR0_CXABORT, &regs->gisr0);
850	857	writel(0, &regs->gisr0);
851	858
852	859	if (st & GISR0_CXERR)
...	...	@@ -873,6 +880,13 @@
873	880	/* Device Status Interrupts */
874	881	if (gisr & GISR_GRP2) {
875	882	st = readl(&regs->gisr2);
	883	+ /*
	884	+ * Write 1 and then 0 works for both W1C & RW.
	885	+ *
	886	+ * HW v1.11.0+: It's a W1C register (write 1 clear)
	887	+ * HW v1.10.0-: It's a R/W register (write 0 clear)
	888	+ */
	889	+ writel(st, &regs->gisr2);
876	890	writel(0, &regs->gisr2);
877	891
878	892	if (st & GISR2_RESET)