Commit bf9012b808515bf1314538e8d423080951d012df
Committed by
Daniel Schwierzeck
Daniel Schwierzeck
1 parent
5a0efcf78a
Exists in
smarc_8mq_lf_v2020.04
and in
17 other branches
MIPS: add support for Broadcom MIPS BCM6348 SoC family
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Showing 6 changed files with 215 additions and 1 deletions Inline Diff
arch/mips/dts/brcm,bcm6348.dtsi
| File was created | 1 | /* | |
| 2 | * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> | ||
| 3 | * | ||
| 4 | * SPDX-License-Identifier: GPL-2.0+ | ||
| 5 | */ | ||
| 6 | |||
| 7 | #include <dt-bindings/clock/bcm6348-clock.h> | ||
| 8 | #include <dt-bindings/gpio/gpio.h> | ||
| 9 | #include <dt-bindings/reset/bcm6348-reset.h> | ||
| 10 | #include "skeleton.dtsi" | ||
| 11 | |||
| 12 | / { | ||
| 13 | compatible = "brcm,bcm6348"; | ||
| 14 | |||
| 15 | cpus { | ||
| 16 | reg = <0xfffe0000 0x4>; | ||
| 17 | #address-cells = <1>; | ||
| 18 | #size-cells = <0>; | ||
| 19 | u-boot,dm-pre-reloc; | ||
| 20 | |||
| 21 | cpu@0 { | ||
| 22 | compatible = "brcm,bcm6348-cpu", "mips,mips4Kc"; | ||
| 23 | device_type = "cpu"; | ||
| 24 | reg = <0>; | ||
| 25 | u-boot,dm-pre-reloc; | ||
| 26 | }; | ||
| 27 | }; | ||
| 28 | |||
| 29 | clocks { | ||
| 30 | compatible = "simple-bus"; | ||
| 31 | #address-cells = <1>; | ||
| 32 | #size-cells = <1>; | ||
| 33 | u-boot,dm-pre-reloc; | ||
| 34 | |||
| 35 | periph_osc: periph-osc { | ||
| 36 | compatible = "fixed-clock"; | ||
| 37 | #clock-cells = <0>; | ||
| 38 | clock-frequency = <50000000>; | ||
| 39 | u-boot,dm-pre-reloc; | ||
| 40 | }; | ||
| 41 | |||
| 42 | periph_clk: periph-clk { | ||
| 43 | compatible = "brcm,bcm6345-clk"; | ||
| 44 | reg = <0xfffe0004 0x4>; | ||
| 45 | #clock-cells = <1>; | ||
| 46 | }; | ||
| 47 | }; | ||
| 48 | |||
| 49 | pflash: nor@1fc00000 { | ||
| 50 | compatible = "cfi-flash"; | ||
| 51 | reg = <0x1fc00000 0x2000000>; | ||
| 52 | bank-width = <2>; | ||
| 53 | #address-cells = <1>; | ||
| 54 | #size-cells = <1>; | ||
| 55 | |||
| 56 | status = "disabled"; | ||
| 57 | }; | ||
| 58 | |||
| 59 | ubus { | ||
| 60 | compatible = "simple-bus"; | ||
| 61 | #address-cells = <1>; | ||
| 62 | #size-cells = <1>; | ||
| 63 | u-boot,dm-pre-reloc; | ||
| 64 | |||
| 65 | pll_cntl: syscon@fffe0008 { | ||
| 66 | compatible = "syscon"; | ||
| 67 | reg = <0xfffe0008 0x4>; | ||
| 68 | }; | ||
| 69 | |||
| 70 | syscon-reboot { | ||
| 71 | compatible = "syscon-reboot"; | ||
| 72 | regmap = <&pll_cntl>; | ||
| 73 | offset = <0x0>; | ||
| 74 | mask = <0x1>; | ||
| 75 | }; | ||
| 76 | |||
| 77 | periph_rst: reset-controller@fffe0028 { | ||
| 78 | compatible = "brcm,bcm6345-reset"; | ||
| 79 | reg = <0xfffe0028 0x4>; | ||
| 80 | #reset-cells = <1>; | ||
| 81 | }; | ||
| 82 | |||
| 83 | wdt: watchdog@fffe021c { | ||
| 84 | compatible = "brcm,bcm6345-wdt"; | ||
| 85 | reg = <0xfffe021c 0xc>; | ||
| 86 | clocks = <&periph_osc>; | ||
| 87 | }; | ||
| 88 | |||
| 89 | wdt-reboot { | ||
| 90 | compatible = "wdt-reboot"; | ||
| 91 | wdt = <&wdt>; | ||
| 92 | }; | ||
| 93 | |||
| 94 | uart0: serial@fffe0300 { | ||
| 95 | compatible = "brcm,bcm6345-uart"; | ||
| 96 | reg = <0xfffe0300 0x18>; | ||
| 97 | clocks = <&periph_osc>; | ||
| 98 | |||
| 99 | status = "disabled"; | ||
| 100 | }; | ||
| 101 | |||
| 102 | gpio1: gpio-controller@fffe0400 { | ||
| 103 | compatible = "brcm,bcm6345-gpio"; | ||
| 104 | reg = <0xfffe0400 0x4>, <0xfffe0408 0x4>; | ||
| 105 | gpio-controller; | ||
| 106 | #gpio-cells = <2>; | ||
| 107 | ngpios = <5>; | ||
| 108 | |||
| 109 | status = "disabled"; | ||
| 110 | }; | ||
| 111 | |||
| 112 | gpio0: gpio-controller@fffe0404 { | ||
| 113 | compatible = "brcm,bcm6345-gpio"; | ||
| 114 | reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>; | ||
| 115 | gpio-controller; | ||
| 116 | #gpio-cells = <2>; | ||
| 117 | |||
| 118 | status = "disabled"; | ||
| 119 | }; | ||
| 120 | |||
| 121 | memory-controller@fffe2300 { | ||
| 122 | compatible = "brcm,bcm6338-mc"; | ||
| 123 | reg = <0xfffe2300 0x38>; | ||
| 124 | u-boot,dm-pre-reloc; | ||
| 125 | }; | ||
| 126 | }; | ||
| 127 | }; | ||
| 128 |
arch/mips/mach-bmips/Kconfig
| 1 | menu "Broadcom MIPS platforms" | 1 | menu "Broadcom MIPS platforms" |
| 2 | depends on ARCH_BMIPS | 2 | depends on ARCH_BMIPS |
| 3 | 3 | ||
| 4 | config SYS_SOC | 4 | config SYS_SOC |
| 5 | default "bcm6328" if SOC_BMIPS_BCM6328 | 5 | default "bcm6328" if SOC_BMIPS_BCM6328 |
| 6 | default "bcm6348" if SOC_BMIPS_BCM6348 | ||
| 6 | default "bcm6358" if SOC_BMIPS_BCM6358 | 7 | default "bcm6358" if SOC_BMIPS_BCM6358 |
| 7 | default "bcm63268" if SOC_BMIPS_BCM63268 | 8 | default "bcm63268" if SOC_BMIPS_BCM63268 |
| 8 | 9 | ||
| 9 | choice | 10 | choice |
| 10 | prompt "Broadcom MIPS SoC select" | 11 | prompt "Broadcom MIPS SoC select" |
| 11 | 12 | ||
| 12 | config SOC_BMIPS_BCM6328 | 13 | config SOC_BMIPS_BCM6328 |
| 13 | bool "BMIPS BCM6328 family" | 14 | bool "BMIPS BCM6328 family" |
| 14 | select SUPPORTS_BIG_ENDIAN | 15 | select SUPPORTS_BIG_ENDIAN |
| 15 | select SUPPORTS_CPU_MIPS32_R1 | 16 | select SUPPORTS_CPU_MIPS32_R1 |
| 16 | select MIPS_TUNE_4KC | 17 | select MIPS_TUNE_4KC |
| 17 | select MIPS_L1_CACHE_SHIFT_4 | 18 | select MIPS_L1_CACHE_SHIFT_4 |
| 18 | select SWAP_IO_SPACE | 19 | select SWAP_IO_SPACE |
| 19 | select SYSRESET_SYSCON | 20 | select SYSRESET_SYSCON |
| 20 | help | 21 | help |
| 21 | This supports BMIPS BCM6328 family including BCM63281 and BCM63283. | 22 | This supports BMIPS BCM6328 family including BCM63281 and BCM63283. |
| 23 | |||
| 24 | config SOC_BMIPS_BCM6348 | ||
| 25 | bool "BMIPS BCM6348 family" | ||
| 26 | select SUPPORTS_BIG_ENDIAN | ||
| 27 | select SUPPORTS_CPU_MIPS32_R1 | ||
| 28 | select MIPS_TUNE_4KC | ||
| 29 | select MIPS_L1_CACHE_SHIFT_4 | ||
| 30 | select SWAP_IO_SPACE | ||
| 31 | select SYSRESET_WATCHDOG | ||
| 32 | help | ||
| 33 | This supports BMIPS BCM6348 family. | ||
| 22 | 34 | ||
| 23 | config SOC_BMIPS_BCM6358 | 35 | config SOC_BMIPS_BCM6358 |
| 24 | bool "BMIPS BCM6358 family" | 36 | bool "BMIPS BCM6358 family" |
| 25 | select SUPPORTS_BIG_ENDIAN | 37 | select SUPPORTS_BIG_ENDIAN |
| 26 | select SUPPORTS_CPU_MIPS32_R1 | 38 | select SUPPORTS_CPU_MIPS32_R1 |
| 27 | select MIPS_TUNE_4KC | 39 | select MIPS_TUNE_4KC |
| 28 | select MIPS_L1_CACHE_SHIFT_4 | 40 | select MIPS_L1_CACHE_SHIFT_4 |
| 29 | select SWAP_IO_SPACE | 41 | select SWAP_IO_SPACE |
| 30 | select SYSRESET_SYSCON | 42 | select SYSRESET_SYSCON |
| 31 | help | 43 | help |
| 32 | This supports BMIPS BCM6358 family including BCM6358 and BCM6359. | 44 | This supports BMIPS BCM6358 family including BCM6358 and BCM6359. |
| 33 | 45 | ||
| 34 | config SOC_BMIPS_BCM63268 | 46 | config SOC_BMIPS_BCM63268 |
| 35 | bool "BMIPS BCM63268 family" | 47 | bool "BMIPS BCM63268 family" |
| 36 | select SUPPORTS_BIG_ENDIAN | 48 | select SUPPORTS_BIG_ENDIAN |
| 37 | select SUPPORTS_CPU_MIPS32_R1 | 49 | select SUPPORTS_CPU_MIPS32_R1 |
| 38 | select MIPS_TUNE_4KC | 50 | select MIPS_TUNE_4KC |
| 39 | select MIPS_L1_CACHE_SHIFT_4 | 51 | select MIPS_L1_CACHE_SHIFT_4 |
| 40 | select SWAP_IO_SPACE | 52 | select SWAP_IO_SPACE |
| 41 | select SYSRESET_SYSCON | 53 | select SYSRESET_SYSCON |
| 42 | help | 54 | help |
| 43 | This supports BMIPS BCM63268 family including BCM63168, BCM63169, | 55 | This supports BMIPS BCM63268 family including BCM63168, BCM63169, |
| 44 | BCM63268 and BCM63269. | 56 | BCM63268 and BCM63269. |
| 45 | 57 | ||
| 46 | endchoice | 58 | endchoice |
| 47 | 59 | ||
| 48 | choice | 60 | choice |
| 49 | prompt "Board select" | 61 | prompt "Board select" |
| 50 | 62 | ||
| 51 | config BOARD_COMTREND_AR5387UN | 63 | config BOARD_COMTREND_AR5387UN |
| 52 | bool "Comtrend AR-5387un" | 64 | bool "Comtrend AR-5387un" |
| 53 | depends on SOC_BMIPS_BCM6328 | 65 | depends on SOC_BMIPS_BCM6328 |
| 54 | select BMIPS_SUPPORTS_BOOT_RAM | 66 | select BMIPS_SUPPORTS_BOOT_RAM |
| 55 | 67 | ||
| 56 | config BOARD_COMTREND_VR3032U | 68 | config BOARD_COMTREND_VR3032U |
| 57 | bool "Comtrend VR-3032u board" | 69 | bool "Comtrend VR-3032u board" |
| 58 | depends on SOC_BMIPS_BCM63268 | 70 | depends on SOC_BMIPS_BCM63268 |
| 59 | select BMIPS_SUPPORTS_BOOT_RAM | 71 | select BMIPS_SUPPORTS_BOOT_RAM |
| 60 | 72 | ||
| 61 | config BOARD_HUAWEI_HG556A | 73 | config BOARD_HUAWEI_HG556A |
| 62 | bool "Huawei EchoLife HG556a" | 74 | bool "Huawei EchoLife HG556a" |
| 63 | depends on SOC_BMIPS_BCM6358 | 75 | depends on SOC_BMIPS_BCM6358 |
| 64 | select BMIPS_SUPPORTS_BOOT_RAM | 76 | select BMIPS_SUPPORTS_BOOT_RAM |
| 65 | 77 | ||
| 66 | config BOARD_SFR_NB4_SER | 78 | config BOARD_SFR_NB4_SER |
| 67 | bool "SFR NeufBox 4 (Sercomm)" | 79 | bool "SFR NeufBox 4 (Sercomm)" |
| 68 | depends on SOC_BMIPS_BCM6358 | 80 | depends on SOC_BMIPS_BCM6358 |
| 69 | select BMIPS_SUPPORTS_BOOT_RAM | 81 | select BMIPS_SUPPORTS_BOOT_RAM |
| 70 | 82 | ||
| 71 | endchoice | 83 | endchoice |
| 72 | 84 | ||
| 73 | choice | 85 | choice |
| 74 | prompt "Boot mode" | 86 | prompt "Boot mode" |
| 75 | 87 | ||
| 76 | config BMIPS_BOOT_RAM | 88 | config BMIPS_BOOT_RAM |
| 77 | bool "RAM boot" | 89 | bool "RAM boot" |
| 78 | depends on BMIPS_SUPPORTS_BOOT_RAM | 90 | depends on BMIPS_SUPPORTS_BOOT_RAM |
| 79 | help | 91 | help |
| 80 | This builds an image that is linked to a RAM address. It can be used | 92 | This builds an image that is linked to a RAM address. It can be used |
| 81 | for booting from CFE via TFTP using an ELF image, but it can also be | 93 | for booting from CFE via TFTP using an ELF image, but it can also be |
| 82 | booted from RAM by other bootloaders using a BIN image. | 94 | booted from RAM by other bootloaders using a BIN image. |
| 83 | 95 | ||
| 84 | endchoice | 96 | endchoice |
| 85 | 97 | ||
| 86 | config BMIPS_SUPPORTS_BOOT_RAM | 98 | config BMIPS_SUPPORTS_BOOT_RAM |
| 87 | bool | 99 | bool |
| 88 | 100 | ||
| 89 | source "board/comtrend/ar5387un/Kconfig" | 101 | source "board/comtrend/ar5387un/Kconfig" |
| 90 | source "board/comtrend/vr3032u/Kconfig" | 102 | source "board/comtrend/vr3032u/Kconfig" |
| 91 | source "board/huawei/hg556a/Kconfig" | 103 | source "board/huawei/hg556a/Kconfig" |
| 92 | source "board/sfr/nb4_ser/Kconfig" | 104 | source "board/sfr/nb4_ser/Kconfig" |
| 93 | 105 | ||
| 94 | endmenu | 106 | endmenu |
| 95 | 107 |
arch/mips/mach-bmips/include/ioremap.h
| 1 | /* | 1 | /* |
| 2 | * SPDX-License-Identifier: GPL-2.0 | 2 | * SPDX-License-Identifier: GPL-2.0 |
| 3 | */ | 3 | */ |
| 4 | #ifndef __ASM_MACH_BMIPS_IOREMAP_H | 4 | #ifndef __ASM_MACH_BMIPS_IOREMAP_H |
| 5 | #define __ASM_MACH_BMIPS_IOREMAP_H | 5 | #define __ASM_MACH_BMIPS_IOREMAP_H |
| 6 | 6 | ||
| 7 | #include <linux/types.h> | 7 | #include <linux/types.h> |
| 8 | 8 | ||
| 9 | /* | 9 | /* |
| 10 | * Allow physical addresses to be fixed up to help peripherals located | 10 | * Allow physical addresses to be fixed up to help peripherals located |
| 11 | * outside the low 32-bit range -- generic pass-through version. | 11 | * outside the low 32-bit range -- generic pass-through version. |
| 12 | */ | 12 | */ |
| 13 | static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, | 13 | static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, |
| 14 | phys_addr_t size) | 14 | phys_addr_t size) |
| 15 | { | 15 | { |
| 16 | return phys_addr; | 16 | return phys_addr; |
| 17 | } | 17 | } |
| 18 | 18 | ||
| 19 | static inline int is_bmips_internal_registers(phys_addr_t offset) | 19 | static inline int is_bmips_internal_registers(phys_addr_t offset) |
| 20 | { | 20 | { |
| 21 | #if defined(CONFIG_SOC_BMIPS_BCM6358) | 21 | #if defined(CONFIG_SOC_BMIPS_BCM6348) || \ |
| 22 | defined(CONFIG_SOC_BMIPS_BCM6358) | ||
| 22 | if (offset >= 0xfffe0000) | 23 | if (offset >= 0xfffe0000) |
| 23 | return 1; | 24 | return 1; |
| 24 | #endif | 25 | #endif |
| 25 | 26 | ||
| 26 | return 0; | 27 | return 0; |
| 27 | } | 28 | } |
| 28 | 29 | ||
| 29 | static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, | 30 | static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, |
| 30 | unsigned long flags) | 31 | unsigned long flags) |
| 31 | { | 32 | { |
| 32 | if (is_bmips_internal_registers(offset)) | 33 | if (is_bmips_internal_registers(offset)) |
| 33 | return (void __iomem *)offset; | 34 | return (void __iomem *)offset; |
| 34 | 35 | ||
| 35 | return NULL; | 36 | return NULL; |
| 36 | } | 37 | } |
| 37 | 38 | ||
| 38 | static inline int plat_iounmap(const volatile void __iomem *addr) | 39 | static inline int plat_iounmap(const volatile void __iomem *addr) |
| 39 | { | 40 | { |
| 40 | return is_bmips_internal_registers((unsigned long)addr); | 41 | return is_bmips_internal_registers((unsigned long)addr); |
| 41 | } | 42 | } |
| 42 | 43 | ||
| 43 | #define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT | 44 | #define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT |
| 44 | 45 | ||
| 45 | #endif /* __ASM_MACH_BMIPS_IOREMAP_H */ | 46 | #endif /* __ASM_MACH_BMIPS_IOREMAP_H */ |
| 46 | 47 |
include/configs/bmips_bcm6348.h
| File was created | 1 | /* | |
| 2 | * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> | ||
| 3 | * | ||
| 4 | * SPDX-License-Identifier: GPL-2.0+ | ||
| 5 | */ | ||
| 6 | |||
| 7 | #ifndef __CONFIG_BMIPS_BCM6348_H | ||
| 8 | #define __CONFIG_BMIPS_BCM6348_H | ||
| 9 | |||
| 10 | /* CPU */ | ||
| 11 | #define CONFIG_SYS_MIPS_TIMER_FREQ 128000000 | ||
| 12 | |||
| 13 | /* RAM */ | ||
| 14 | #define CONFIG_NR_DRAM_BANKS 1 | ||
| 15 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 | ||
| 16 | |||
| 17 | /* U-Boot */ | ||
| 18 | #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 | ||
| 19 | |||
| 20 | #if defined(CONFIG_BMIPS_BOOT_RAM) | ||
| 21 | #define CONFIG_SKIP_LOWLEVEL_INIT | ||
| 22 | #define CONFIG_SYS_INIT_SP_OFFSET 0x2000 | ||
| 23 | #endif | ||
| 24 | |||
| 25 | #define CONFIG_SYS_FLASH_BASE 0xbfc00000 | ||
| 26 | #define CONFIG_SYS_FLASH_EMPTY_INFO | ||
| 27 | #define CONFIG_SYS_FLASH_PROTECTION | ||
| 28 | #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 | ||
| 29 | |||
| 30 | #endif /* __CONFIG_BMIPS_BCM6348_H */ | ||
| 31 |
include/dt-bindings/clock/bcm6348-clock.h
| File was created | 1 | /* | |
| 2 | * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> | ||
| 3 | * | ||
| 4 | * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | ||
| 5 | * | ||
| 6 | * SPDX-License-Identifier: GPL-2.0+ | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __DT_BINDINGS_CLOCK_BCM6348_H | ||
| 10 | #define __DT_BINDINGS_CLOCK_BCM6348_H | ||
| 11 | |||
| 12 | #define BCM6348_CLK_ADSL 0 | ||
| 13 | #define BCM6348_CLK_MPI 1 | ||
| 14 | #define BCM6348_CLK_SDRAM 2 | ||
| 15 | #define BCM6348_CLK_M2M 3 | ||
| 16 | #define BCM6348_CLK_ENET 4 | ||
| 17 | #define BCM6348_CLK_SAR 5 | ||
| 18 | #define BCM6348_CLK_USBS 6 | ||
| 19 | #define BCM6348_CLK_USBH 8 | ||
| 20 | #define BCM6348_CLK_SPI 9 | ||
| 21 | |||
| 22 | #endif /* __DT_BINDINGS_CLOCK_BCM6348_H */ | ||
| 23 |
include/dt-bindings/reset/bcm6348-reset.h
| File was created | 1 | /* | |
| 2 | * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com> | ||
| 3 | * | ||
| 4 | * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | ||
| 5 | * | ||
| 6 | * SPDX-License-Identifier: GPL-2.0+ | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __DT_BINDINGS_RESET_BCM6348_H | ||
| 10 | #define __DT_BINDINGS_RESET_BCM6348_H | ||
| 11 | |||
| 12 | #define BCM6348_RST_SPI 0 | ||
| 13 | #define BCM6348_RST_ENET 2 | ||
| 14 | #define BCM6348_RST_USBH 3 | ||
| 15 | #define BCM6348_RST_USBS 4 | ||
| 16 | #define BCM6348_RST_ADSL 5 | ||
| 17 | #define BCM6348_RST_DMAMEM 6 | ||
| 18 | #define BCM6348_RST_SAR 7 | ||
| 19 | #define BCM6348_RST_ACLC 8 | ||
| 20 | #define BCM6348_RST_ADSL_MIPS 10 | ||
| 21 | |||
| 22 | #endif /* __DT_BINDINGS_RESET_BCM6348_H */ | ||
| 23 |