MIPS: add support for Broadcom MIPS BCM6348 SoC family

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>

MIPS: add support for Broadcom MIPS BCM6348 SoC family
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Álvaro Fernández Rojas · Daniel Schwierzeck
1 parent 5a0efcf78a
Showing 6 changed files with 215 additions and 1 deletions Side-by-side Diff
arch/mips/dts/brcm,bcm6348.dtsi
arch/mips/mach-bmips/Kconfig
arch/mips/mach-bmips/include/ioremap.h
include/configs/bmips_bcm6348.h
include/dt-bindings/clock/bcm6348-clock.h
include/dt-bindings/reset/bcm6348-reset.h
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <dt-bindings/clock/bcm6348-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/bcm6348-reset.h>
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "brcm,bcm6348";
+
+	cpus {
+		reg = <0xfffe0000 0x4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;
+
+		cpu@0 {
+			compatible = "brcm,bcm6348-cpu", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <0>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		periph_clk: periph-clk {
+			compatible = "brcm,bcm6345-clk";
+			reg = <0xfffe0004 0x4>;
+			#clock-cells = <1>;
+		};
+	};
+
+	pflash: nor@1fc00000 {
+		compatible = "cfi-flash";
+		reg = <0x1fc00000 0x2000000>;
+		bank-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		status = "disabled";
+	};
+
+	ubus {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		pll_cntl: syscon@fffe0008 {
+			compatible = "syscon";
+			reg = <0xfffe0008 0x4>;
+		};
+
+		syscon-reboot {
+			compatible = "syscon-reboot";
+			regmap = <&pll_cntl>;
+			offset = <0x0>;
+			mask = <0x1>;
+		};
+
+		periph_rst: reset-controller@fffe0028 {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0xfffe0028 0x4>;
+			#reset-cells = <1>;
+		};
+
+		wdt: watchdog@fffe021c {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0xfffe021c 0xc>;
+			clocks = <&periph_osc>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt>;
+		};
+
+		uart0: serial@fffe0300 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0xfffe0300 0x18>;
+			clocks = <&periph_osc>;
+
+			status = "disabled";
+		};
+
+		gpio1: gpio-controller@fffe0400 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0xfffe0400 0x4>, <0xfffe0408 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <5>;
+
+			status = "disabled";
+		};
+
+		gpio0: gpio-controller@fffe0404 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			status = "disabled";
+		};
+
+		memory-controller@fffe2300 {
+			compatible = "brcm,bcm6338-mc";
+			reg = <0xfffe2300 0x38>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
@@ -3,6 +3,7 @@
  
 config SYS_SOC
 	default "bcm6328" if SOC_BMIPS_BCM6328
+	default "bcm6348" if SOC_BMIPS_BCM6348
 	default "bcm6358" if SOC_BMIPS_BCM6358
 	default "bcm63268" if SOC_BMIPS_BCM63268
  
@@ -19,6 +20,17 @@
 	select SYSRESET_SYSCON
 	help
 	  This supports BMIPS BCM6328 family including BCM63281 and BCM63283.
+
+config SOC_BMIPS_BCM6348
+	bool "BMIPS BCM6348 family"
+	select SUPPORTS_BIG_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select MIPS_TUNE_4KC
+	select MIPS_L1_CACHE_SHIFT_4
+	select SWAP_IO_SPACE
+	select SYSRESET_WATCHDOG
+	help
+	  This supports BMIPS BCM6348 family.
  
 config SOC_BMIPS_BCM6358
 	bool "BMIPS BCM6358 family"
@@ -18,7 +18,8 @@
  
 static inline int is_bmips_internal_registers(phys_addr_t offset)
 {
-#if defined(CONFIG_SOC_BMIPS_BCM6358)
+#if defined(CONFIG_SOC_BMIPS_BCM6348) || \
+	defined(CONFIG_SOC_BMIPS_BCM6358)
 	if (offset >= 0xfffe0000)
 		return 1;
 #endif
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6348_H
+#define __CONFIG_BMIPS_BCM6348_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	128000000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET	0x2000
+#endif
+
+#define CONFIG_SYS_FLASH_BASE			0xbfc00000
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
+
+#endif /* __CONFIG_BMIPS_BCM6348_H */
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6348_H
+#define __DT_BINDINGS_CLOCK_BCM6348_H
+
+#define BCM6348_CLK_ADSL	0
+#define BCM6348_CLK_MPI		1
+#define BCM6348_CLK_SDRAM	2
+#define BCM6348_CLK_M2M		3
+#define BCM6348_CLK_ENET	4
+#define BCM6348_CLK_SAR		5
+#define BCM6348_CLK_USBS	6
+#define BCM6348_CLK_USBH	8
+#define BCM6348_CLK_SPI		9
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6348_H */
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6348_H
+#define __DT_BINDINGS_RESET_BCM6348_H
+
+#define BCM6348_RST_SPI		0
+#define BCM6348_RST_ENET	2
+#define BCM6348_RST_USBH	3
+#define BCM6348_RST_USBS	4
+#define BCM6348_RST_ADSL	5
+#define BCM6348_RST_DMAMEM	6
+#define BCM6348_RST_SAR		7
+#define BCM6348_RST_ACLC	8
+#define BCM6348_RST_ADSL_MIPS	10
+
+#endif /* __DT_BINDINGS_RESET_BCM6348_H */
	1	+/*
	2	+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+
	7	+#include <dt-bindings/clock/bcm6348-clock.h>
	8	+#include <dt-bindings/gpio/gpio.h>
	9	+#include <dt-bindings/reset/bcm6348-reset.h>
	10	+#include "skeleton.dtsi"
	11	+
	12	+/ {
	13	+ compatible = "brcm,bcm6348";
	14	+
	15	+ cpus {
	16	+ reg = <0xfffe0000 0x4>;
	17	+ #address-cells = <1>;
	18	+ #size-cells = <0>;
	19	+ u-boot,dm-pre-reloc;
	20	+
	21	+ cpu@0 {
	22	+ compatible = "brcm,bcm6348-cpu", "mips,mips4Kc";
	23	+ device_type = "cpu";
	24	+ reg = <0>;
	25	+ u-boot,dm-pre-reloc;
	26	+ };
	27	+ };
	28	+
	29	+ clocks {
	30	+ compatible = "simple-bus";
	31	+ #address-cells = <1>;
	32	+ #size-cells = <1>;
	33	+ u-boot,dm-pre-reloc;
	34	+
	35	+ periph_osc: periph-osc {
	36	+ compatible = "fixed-clock";
	37	+ #clock-cells = <0>;
	38	+ clock-frequency = <50000000>;
	39	+ u-boot,dm-pre-reloc;
	40	+ };
	41	+
	42	+ periph_clk: periph-clk {
	43	+ compatible = "brcm,bcm6345-clk";
	44	+ reg = <0xfffe0004 0x4>;
	45	+ #clock-cells = <1>;
	46	+ };
	47	+ };
	48	+
	49	+ pflash: nor@1fc00000 {
	50	+ compatible = "cfi-flash";
	51	+ reg = <0x1fc00000 0x2000000>;
	52	+ bank-width = <2>;
	53	+ #address-cells = <1>;
	54	+ #size-cells = <1>;
	55	+
	56	+ status = "disabled";
	57	+ };
	58	+
	59	+ ubus {
	60	+ compatible = "simple-bus";
	61	+ #address-cells = <1>;
	62	+ #size-cells = <1>;
	63	+ u-boot,dm-pre-reloc;
	64	+
	65	+ pll_cntl: syscon@fffe0008 {
	66	+ compatible = "syscon";
	67	+ reg = <0xfffe0008 0x4>;
	68	+ };
	69	+
	70	+ syscon-reboot {
	71	+ compatible = "syscon-reboot";
	72	+ regmap = <&pll_cntl>;
	73	+ offset = <0x0>;
	74	+ mask = <0x1>;
	75	+ };
	76	+
	77	+ periph_rst: reset-controller@fffe0028 {
	78	+ compatible = "brcm,bcm6345-reset";
	79	+ reg = <0xfffe0028 0x4>;
	80	+ #reset-cells = <1>;
	81	+ };
	82	+
	83	+ wdt: watchdog@fffe021c {
	84	+ compatible = "brcm,bcm6345-wdt";
	85	+ reg = <0xfffe021c 0xc>;
	86	+ clocks = <&periph_osc>;
	87	+ };
	88	+
	89	+ wdt-reboot {
	90	+ compatible = "wdt-reboot";
	91	+ wdt = <&wdt>;
	92	+ };
	93	+
	94	+ uart0: serial@fffe0300 {
	95	+ compatible = "brcm,bcm6345-uart";
	96	+ reg = <0xfffe0300 0x18>;
	97	+ clocks = <&periph_osc>;
	98	+
	99	+ status = "disabled";
	100	+ };
	101	+
	102	+ gpio1: gpio-controller@fffe0400 {
	103	+ compatible = "brcm,bcm6345-gpio";
	104	+ reg = <0xfffe0400 0x4>, <0xfffe0408 0x4>;
	105	+ gpio-controller;
	106	+ #gpio-cells = <2>;
	107	+ ngpios = <5>;
	108	+
	109	+ status = "disabled";
	110	+ };
	111	+
	112	+ gpio0: gpio-controller@fffe0404 {
	113	+ compatible = "brcm,bcm6345-gpio";
	114	+ reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>;
	115	+ gpio-controller;
	116	+ #gpio-cells = <2>;
	117	+
	118	+ status = "disabled";
	119	+ };
	120	+
	121	+ memory-controller@fffe2300 {
	122	+ compatible = "brcm,bcm6338-mc";
	123	+ reg = <0xfffe2300 0x38>;
	124	+ u-boot,dm-pre-reloc;
	125	+ };
	126	+ };
	127	+};
...	...	@@ -3,6 +3,7 @@
3	3
4	4	config SYS_SOC
5	5	default "bcm6328" if SOC_BMIPS_BCM6328
	6	+ default "bcm6348" if SOC_BMIPS_BCM6348
6	7	default "bcm6358" if SOC_BMIPS_BCM6358
7	8	default "bcm63268" if SOC_BMIPS_BCM63268
8	9
...	...	@@ -19,6 +20,17 @@
19	20	select SYSRESET_SYSCON
20	21	help
21	22	This supports BMIPS BCM6328 family including BCM63281 and BCM63283.
	23	+
	24	+config SOC_BMIPS_BCM6348
	25	+ bool "BMIPS BCM6348 family"
	26	+ select SUPPORTS_BIG_ENDIAN
	27	+ select SUPPORTS_CPU_MIPS32_R1
	28	+ select MIPS_TUNE_4KC
	29	+ select MIPS_L1_CACHE_SHIFT_4
	30	+ select SWAP_IO_SPACE
	31	+ select SYSRESET_WATCHDOG
	32	+ help
	33	+ This supports BMIPS BCM6348 family.
22	34
23	35	config SOC_BMIPS_BCM6358
24	36	bool "BMIPS BCM6358 family"
...	...	@@ -18,7 +18,8 @@
18	18
19	19	static inline int is_bmips_internal_registers(phys_addr_t offset)
20	20	{
21		-#if defined(CONFIG_SOC_BMIPS_BCM6358)
	21	+#if defined(CONFIG_SOC_BMIPS_BCM6348) \|\| \
	22	+ defined(CONFIG_SOC_BMIPS_BCM6358)
22	23	if (offset >= 0xfffe0000)
23	24	return 1;
24	25	#endif
	1	+/*
	2	+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
	3	+ *
	4	+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ */
	8	+
	9	+#ifndef __DT_BINDINGS_CLOCK_BCM6348_H
	10	+#define __DT_BINDINGS_CLOCK_BCM6348_H
	11	+
	12	+#define BCM6348_CLK_ADSL 0
	13	+#define BCM6348_CLK_MPI 1
	14	+#define BCM6348_CLK_SDRAM 2
	15	+#define BCM6348_CLK_M2M 3
	16	+#define BCM6348_CLK_ENET 4
	17	+#define BCM6348_CLK_SAR 5
	18	+#define BCM6348_CLK_USBS 6
	19	+#define BCM6348_CLK_USBH 8
	20	+#define BCM6348_CLK_SPI 9
	21	+
	22	+#endif /* __DT_BINDINGS_CLOCK_BCM6348_H */