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Commit c6f90e1418a84fe5fa463b38403bd1845cb6a59c

Authored by Nishanth Menon
Committed by Tom Rini
1 parent fc7368ec85
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ARM: OMAP3: Enable workaround for ARM errata 454179, 430973, 621766 

Enable the OMAP3 specific errata code for 454179, 430973, 621766
and while at it, remove legacy non-revision checked errata logic.

Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Matt Porter <mporter@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

Showing 16 changed files with 71 additions and 21 deletions Side-by-side Diff

arch/arm/cpu/armv7/omap3/board.c
Diff comments   View file @ c6f90e1
... ... @@ -35,7 +35,6 @@
35 35  
36 36 /* Declarations */
37 37 extern omap3_sysinfo sysinfo;
38   -static void omap3_setup_aux_cr(void);
39 38 #ifndef CONFIG_SYS_L2CACHE_OFF
40 39 static void omap3_invalidate_l2_cache_secure(void);
41 40 #endif
... ... @@ -244,9 +243,6 @@
244 243  
245 244 try_unlock_memory();
246 245  
247   - /* Errata workarounds */
248   - omap3_setup_aux_cr();
249   -
250 246 #ifndef CONFIG_SYS_L2CACHE_OFF
251 247 /* Invalidate L2-cache from secure mode */
252 248 omap3_invalidate_l2_cache_secure();
253 249  
... ... @@ -419,15 +415,9 @@
419 415 do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
420 416 }
421 417  
422   -static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
  418 +void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
  419 + u32 cpu_variant, u32 cpu_rev)
423 420 {
424   - u32 acr;
425   -
426   - /* Read ACR */
427   - asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
428   - acr &= ~clear_bits;
429   - acr |= set_bits;
430   -
431 421 if (get_device_type() == GP_DEVICE) {
432 422 omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
433 423 } else {
434 424  
... ... @@ -439,16 +429,15 @@
439 429 }
440 430 }
441 431  
442   -static void omap3_setup_aux_cr(void)
  432 +static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
443 433 {
444   - /* Workaround for Cortex-A8 errata: #454179 #430973
445   - * Set "IBE" bit
446   - * Set "Disable Branch Size Mispredicts" bit
447   - * Workaround for erratum #621766
448   - * Enable L1NEON bit
449   - * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
450   - */
451   - omap3_update_aux_cr_secure(0xE0, 0);
  434 + u32 acr;
  435 +
  436 + /* Read ACR */
  437 + asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
  438 + acr &= ~clear_bits;
  439 + acr |= set_bits;
  440 + v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
452 441 }
453 442  
454 443 #ifndef CONFIG_SYS_L2CACHE_OFF
include/configs/am3517_crane.h
Diff comments   View file @ c6f90e1
... ... @@ -19,6 +19,10 @@
19 19 #define CONFIG_OMAP 1 /* in a TI OMAP core */
20 20 #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */
21 21 #define CONFIG_OMAP_COMMON
  22 +/* Common ARM Erratas */
  23 +#define CONFIG_ARM_ERRATA_454179
  24 +#define CONFIG_ARM_ERRATA_430973
  25 +#define CONFIG_ARM_ERRATA_621766
22 26  
23 27 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
24 28  
include/configs/am3517_evm.h
Diff comments   View file @ c6f90e1
... ... @@ -19,6 +19,10 @@
19 19 #define CONFIG_OMAP 1 /* in a TI OMAP core */
20 20 #define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */
21 21 #define CONFIG_OMAP_COMMON
  22 +/* Common ARM Erratas */
  23 +#define CONFIG_ARM_ERRATA_454179
  24 +#define CONFIG_ARM_ERRATA_430973
  25 +#define CONFIG_ARM_ERRATA_621766
22 26  
23 27 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */
24 28  
include/configs/cm_t35.h
Diff comments   View file @ c6f90e1
... ... @@ -26,6 +26,10 @@
26 26 #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
27 27 #define CONFIG_OMAP_COMMON
28 28 #define CONFIG_SYS_GENERIC_BOARD
  29 +/* Common ARM Erratas */
  30 +#define CONFIG_ARM_ERRATA_454179
  31 +#define CONFIG_ARM_ERRATA_430973
  32 +#define CONFIG_ARM_ERRATA_621766
29 33  
30 34 #define CONFIG_SDRC /* The chip has SDRC controller */
31 35  
include/configs/cm_t3517.h
Diff comments   View file @ c6f90e1
... ... @@ -17,6 +17,10 @@
17 17 #define CONFIG_CM_T3517 /* working with CM-T3517 */
18 18 #define CONFIG_OMAP_COMMON
19 19 #define CONFIG_SYS_GENERIC_BOARD
  20 +/* Common ARM Erratas */
  21 +#define CONFIG_ARM_ERRATA_454179
  22 +#define CONFIG_ARM_ERRATA_430973
  23 +#define CONFIG_ARM_ERRATA_621766
20 24  
21 25 #define CONFIG_SYS_TEXT_BASE 0x80008000
22 26  
include/configs/dig297.h
Diff comments   View file @ c6f90e1
... ... @@ -23,6 +23,10 @@
23 23 #define MACH_TYPE_OMAP3_CPS 2751
24 24 #endif
25 25 #define CONFIG_MACH_TYPE MACH_TYPE_OMAP3_CPS
  26 +/* Common ARM Erratas */
  27 +#define CONFIG_ARM_ERRATA_454179
  28 +#define CONFIG_ARM_ERRATA_430973
  29 +#define CONFIG_ARM_ERRATA_621766
26 30  
27 31 /*
28 32 * High Level Configuration Options
include/configs/mcx.h
Diff comments   View file @ c6f90e1
... ... @@ -16,6 +16,10 @@
16 16 #define CONFIG_OMAP3_MCX /* working with mcx */
17 17 #define CONFIG_OMAP_GPIO
18 18 #define CONFIG_OMAP_COMMON
  19 +/* Common ARM Erratas */
  20 +#define CONFIG_ARM_ERRATA_454179
  21 +#define CONFIG_ARM_ERRATA_430973
  22 +#define CONFIG_ARM_ERRATA_621766
19 23  
20 24 #define MACH_TYPE_MCX 3656
21 25 #define CONFIG_MACH_TYPE MACH_TYPE_MCX
include/configs/omap3_evm_common.h
Diff comments   View file @ c6f90e1
... ... @@ -15,6 +15,10 @@
15 15 #define CONFIG_OMAP /* This is TI OMAP core */
16 16 #define CONFIG_OMAP_GPIO
17 17 #define CONFIG_OMAP_COMMON
  18 +/* Common ARM Erratas */
  19 +#define CONFIG_ARM_ERRATA_454179
  20 +#define CONFIG_ARM_ERRATA_430973
  21 +#define CONFIG_ARM_ERRATA_621766
18 22  
19 23 #define CONFIG_SDRC /* The chip has SDRC controller */
20 24  
include/configs/omap3_logic.h
Diff comments   View file @ c6f90e1
... ... @@ -18,6 +18,10 @@
18 18 #define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */
19 19 #define CONFIG_OMAP_GPIO
20 20 #define CONFIG_OMAP_COMMON
  21 +/* Common ARM Erratas */
  22 +#define CONFIG_ARM_ERRATA_454179
  23 +#define CONFIG_ARM_ERRATA_430973
  24 +#define CONFIG_ARM_ERRATA_621766
21 25  
22 26 #define CONFIG_SYS_TEXT_BASE 0x80400000
23 27  
include/configs/omap3_mvblx.h
Diff comments   View file @ c6f90e1
... ... @@ -23,6 +23,10 @@
23 23 #define CONFIG_MACH_TYPE MACH_TYPE_MVBLX
24 24 #define CONFIG_OMAP_GPIO
25 25 #define CONFIG_OMAP_COMMON
  26 +/* Common ARM Erratas */
  27 +#define CONFIG_ARM_ERRATA_454179
  28 +#define CONFIG_ARM_ERRATA_430973
  29 +#define CONFIG_ARM_ERRATA_621766
26 30  
27 31 #define CONFIG_SDRC /* The chip has SDRC controller */
28 32  
include/configs/omap3_pandora.h
Diff comments   View file @ c6f90e1
... ... @@ -17,6 +17,10 @@
17 17 #define CONFIG_OMAP3_PANDORA 1 /* working with pandora */
18 18 #define CONFIG_OMAP_GPIO
19 19 #define CONFIG_OMAP_COMMON
  20 +/* Common ARM Erratas */
  21 +#define CONFIG_ARM_ERRATA_454179
  22 +#define CONFIG_ARM_ERRATA_430973
  23 +#define CONFIG_ARM_ERRATA_621766
20 24  
21 25 #define CONFIG_SDRC /* The chip has SDRC controller */
22 26  
include/configs/omap3_sdp3430.h
Diff comments   View file @ c6f90e1
... ... @@ -23,6 +23,10 @@
23 23 #define CONFIG_OMAP 1 /* in a TI OMAP core */
24 24 #define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */
25 25 #define CONFIG_OMAP_COMMON
  26 +/* Common ARM Erratas */
  27 +#define CONFIG_ARM_ERRATA_454179
  28 +#define CONFIG_ARM_ERRATA_430973
  29 +#define CONFIG_ARM_ERRATA_621766
26 30  
27 31 #define CONFIG_SDRC /* The chip has SDRC controller */
28 32  
include/configs/tam3517-common.h
Diff comments   View file @ c6f90e1
... ... @@ -17,6 +17,10 @@
17 17 #define CONFIG_OMAP_GPIO
18 18 #define CONFIG_OMAP_COMMON
19 19 #define CONFIG_SYS_GENERIC_BOARD
  20 +/* Common ARM Erratas */
  21 +#define CONFIG_ARM_ERRATA_454179
  22 +#define CONFIG_ARM_ERRATA_430973
  23 +#define CONFIG_ARM_ERRATA_621766
20 24  
21 25 #define CONFIG_SYS_TEXT_BASE 0x80008000
22 26  
include/configs/tao3530.h
Diff comments   View file @ c6f90e1
... ... @@ -21,6 +21,10 @@
21 21 #define CONFIG_OMAP_GPIO
22 22 #define CONFIG_OMAP_COMMON
23 23 #define CONFIG_SYS_GENERIC_BOARD
  24 +/* Common ARM Erratas */
  25 +#define CONFIG_ARM_ERRATA_454179
  26 +#define CONFIG_ARM_ERRATA_430973
  27 +#define CONFIG_ARM_ERRATA_621766
24 28  
25 29 #define MACH_TYPE_OMAP3_TAO3530 2836
26 30  
include/configs/ti_omap3_common.h
Diff comments   View file @ c6f90e1
... ... @@ -22,6 +22,11 @@
22 22 # define CONFIG_OMAP_SERIAL
23 23 #endif
24 24  
  25 +/* Common ARM Erratas */
  26 +#define CONFIG_ARM_ERRATA_454179
  27 +#define CONFIG_ARM_ERRATA_430973
  28 +#define CONFIG_ARM_ERRATA_621766
  29 +
25 30 /* The chip has SDRC controller */
26 31 #define CONFIG_SDRC
27 32  
include/configs/tricorder.h
Diff comments   View file @ c6f90e1
... ... @@ -19,6 +19,10 @@
19 19 /* High Level Configuration Options */
20 20 #define CONFIG_OMAP /* in a TI OMAP core */
21 21 #define CONFIG_OMAP_COMMON
  22 +/* Common ARM Erratas */
  23 +#define CONFIG_ARM_ERRATA_454179
  24 +#define CONFIG_ARM_ERRATA_430973
  25 +#define CONFIG_ARM_ERRATA_621766
22 26  
23 27 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
24 28 /*