Eric Lee / smarc-uboot

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Commit c82e9de400ee36038c76be67c5a6fb39c165ac1c

Authored by Wang Huan
Committed by York Sun
1 parent 52d00a812a
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

esdhc: Add CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE macros 

For LS102xA, the processor is in little-endian mode, while esdhc IP is
in big-endian mode. CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE
are added. So accessing ESDHC registers can be determined by ESDHC IP's
endian mode.

Signed-off-by: Alison Wang <alison.wang@freescale.com>

Showing 2 changed files with 18 additions and 1 deletions Side-by-side Diff

doc/README.fsl-esdhc
Diff comments   View file @ c82e9de
  1 +CONFIG_SYS_FSL_ESDHC_LE means ESDHC IP is in little-endian mode.
  2 +CONFIG_SYS_FSL_ESDHC_BE means ESDHC IP is in big-endian mode.
  3 +
  4 +Accessing ESDHC registers can be determined by ESDHC IP's endian
  5 +mode or processor's endian mode.
... ... @@ -162,7 +162,19 @@
162 162 };
163 163  
164 164 /* Select the correct accessors depending on endianess */
165   -#if __BYTE_ORDER == __LITTLE_ENDIAN
  165 +#if defined CONFIG_SYS_FSL_ESDHC_LE
  166 +#define esdhc_read32 in_le32
  167 +#define esdhc_write32 out_le32
  168 +#define esdhc_clrsetbits32 clrsetbits_le32
  169 +#define esdhc_clrbits32 clrbits_le32
  170 +#define esdhc_setbits32 setbits_le32
  171 +#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
  172 +#define esdhc_read32 in_be32
  173 +#define esdhc_write32 out_be32
  174 +#define esdhc_clrsetbits32 clrsetbits_be32
  175 +#define esdhc_clrbits32 clrbits_be32
  176 +#define esdhc_setbits32 setbits_be32
  177 +#elif __BYTE_ORDER == __LITTLE_ENDIAN
166 178 #define esdhc_read32 in_le32
167 179 #define esdhc_write32 out_le32
168 180 #define esdhc_clrsetbits32 clrsetbits_le32