Eric Lee / smarc-uboot

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Commit ca0df9c20a3b0e67bf95a077115cd43ef61df1b6

Authored by Ye Li
Committed by Peng Fan
1 parent 82b3ab2230
Exists in smarc-rel_imx_4.1.15_2.0.0_ga

MLK-12616-5 GPT: Update GPT driver for MX6ULL 

The MX6ULL has GPT with supporting OSC clock source, update the driver
accordingly.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit b2740fd7a0f8d80b416d4de1f57b6542407d23bd)

Showing 1 changed file with 4 additions and 3 deletions Side-by-side Diff

arch/arm/imx-common/timer.c
Diff comments   View file @ ca0df9c
... ... @@ -46,7 +46,7 @@
46 46 if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
47 47 (soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) ||
48 48 is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) ||
49   - is_cpu_type(MXC_CPU_MX6UL))
  49 + is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6ULL))
50 50 return 1;
51 51  
52 52 return 0;
53 53  
... ... @@ -91,12 +91,13 @@
91 91 if (gpt_has_clk_source_osc()) {
92 92 i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
93 93  
94   - /* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */
  94 + /* For DL/S, SX, UL, ULL set 24Mhz OSC Enable bit and prescaler */
95 95 if (is_cpu_type(MXC_CPU_MX6DL) ||
96 96 is_cpu_type(MXC_CPU_MX6SOLO) ||
97 97 is_cpu_type(MXC_CPU_MX6SX) ||
98 98 is_cpu_type(MXC_CPU_MX7D) ||
99   - is_cpu_type(MXC_CPU_MX6UL)) {
  99 + is_cpu_type(MXC_CPU_MX6UL) ||
  100 + is_cpu_type(MXC_CPU_MX6ULL)) {
100 101 i |= GPTCR_24MEN;
101 102  
102 103 /* Produce 3Mhz clock */