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Commit ccfa28aec4093ac30a9b76d973f0288ab9c8f92c

Authored by Peng Fan
Committed by Ye Li
1 parent a9678f1645
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 5 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MLK-14418-8 imx: mx7dsabresd: add epdc support 

Add epdc support from v2016.03.
Add a epdc specified DTS file for using epdc

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit ab2f9e136f5da034a8335dc8ca276a54367132e8)

Showing 6 changed files with 404 additions and 1 deletions Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ ccfa28a
... ... @@ -411,7 +411,8 @@
411 411 imx6ul-opos6uldev.dtb
412 412  
413 413 dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
414   - imx7d-sdb.dtb
  414 + imx7d-sdb.dtb \
  415 + imx7d-sdb-epdc.dtb
415 416  
416 417 dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
417 418  
arch/arm/dts/imx7d-sdb-epdc.dts
Diff comments   View file @ ccfa28a
  1 +/*
  2 + * Copyright (C) 2015 Freescale Semiconductor, Inc.
  3 + *
  4 + * This program is free software; you can redistribute it and/or modify
  5 + * it under the terms of the GNU General Public License version 2 as
  6 + * published by the Free Software Foundation.
  7 + */
  8 +#include "imx7d-sdb.dts"
  9 +#include "imx7d-sdb-epdc.dtsi"
arch/arm/dts/imx7d-sdb-epdc.dtsi
Diff comments   View file @ ccfa28a
  1 +/*
  2 + * Copyright (C) 2015 Freescale Semiconductor, Inc.
  3 + *
  4 + * This program is free software; you can redistribute it and/or modify
  5 + * it under the terms of the GNU General Public License version 2 as
  6 + * published by the Free Software Foundation.
  7 + */
  8 +
  9 +&epdc {
  10 + status = "okay";
  11 +};
  12 +
  13 +&fec1 {
  14 + status = "disabled";
  15 +};
  16 +
  17 +&fec2 {
  18 + status = "disabled";
  19 +};
  20 +
  21 +&flexcan2 {
  22 + status = "disabled";
  23 +};
  24 +
  25 +&max17135 {
  26 + status = "okay";
  27 +};
  28 +
  29 +&sii902x {
  30 + status = "disabled";
  31 +};
  32 +
  33 +&sim1 {
  34 + status = "disabled";
  35 +};
  36 +
  37 +&uart5 {
  38 + status = "disabled";
  39 +};
  40 +
  41 +&i2c3 {
  42 + elan@10 {
  43 + pinctrl-names = "default";
  44 + pinctrl-0 = <&pinctrl_epdc_elan_touch>;
  45 + compatible = "elan,elan-touch";
  46 + reg = <0x10>;
  47 + interrupt-parent = <&gpio6>;
  48 + interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
  49 + gpio_elan_cs = <&gpio6 13 0>;
  50 + gpio_elan_rst = <&gpio6 15 0>;
  51 + gpio_intr = <&gpio6 12 0>;
  52 + status = "okay";
  53 + };
  54 +};
board/freescale/mx7dsabresd/mx7dsabresd.c
Diff comments   View file @ ccfa28a
... ... @@ -23,6 +23,10 @@
23 23 #include <i2c.h>
24 24 #include <asm/mach-imx/mxc_i2c.h>
25 25 #include <asm/arch/crm_regs.h>
  26 +#if defined(CONFIG_MXC_EPDC)
  27 +#include <lcd.h>
  28 +#include <mxc_epdc_fb.h>
  29 +#endif
26 30  
27 31 DECLARE_GLOBAL_DATA_PTR;
28 32  
... ... @@ -47,6 +51,8 @@
47 51  
48 52 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
49 53  
  54 +#define EPDC_PAD_CTRL 0x0
  55 +
50 56 #ifdef CONFIG_MXC_SPI
51 57 static iomux_v3_cfg_t const ecspi3_pads[] = {
52 58 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
... ... @@ -328,6 +334,221 @@
328 334 }
329 335 #endif
330 336  
  337 +#ifdef CONFIG_MXC_EPDC
  338 +iomux_v3_cfg_t const epdc_en_pads[] = {
  339 + MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(NO_PAD_CTRL),
  340 +};
  341 +
  342 +static iomux_v3_cfg_t const epdc_enable_pads[] = {
  343 + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  344 + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  345 + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  346 + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  347 + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  348 + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  349 + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  350 + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  351 + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  352 + MX7D_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  353 + MX7D_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  354 + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  355 + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  356 + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  357 + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  358 + MX7D_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  359 + MX7D_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  360 + MX7D_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  361 + MX7D_PAD_EPDC_BDR0__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  362 + MX7D_PAD_EPDC_BDR1__EPDC_BDR1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  363 +};
  364 +
  365 +static iomux_v3_cfg_t const epdc_disable_pads[] = {
  366 + MX7D_PAD_EPDC_DATA00__GPIO2_IO0,
  367 + MX7D_PAD_EPDC_DATA01__GPIO2_IO1,
  368 + MX7D_PAD_EPDC_DATA02__GPIO2_IO2,
  369 + MX7D_PAD_EPDC_DATA03__GPIO2_IO3,
  370 + MX7D_PAD_EPDC_DATA04__GPIO2_IO4,
  371 + MX7D_PAD_EPDC_DATA05__GPIO2_IO5,
  372 + MX7D_PAD_EPDC_DATA06__GPIO2_IO6,
  373 + MX7D_PAD_EPDC_DATA07__GPIO2_IO7,
  374 + MX7D_PAD_EPDC_SDCLK__GPIO2_IO16,
  375 + MX7D_PAD_EPDC_SDLE__GPIO2_IO17,
  376 + MX7D_PAD_EPDC_SDOE__GPIO2_IO18,
  377 + MX7D_PAD_EPDC_SDSHR__GPIO2_IO19,
  378 + MX7D_PAD_EPDC_SDCE0__GPIO2_IO20,
  379 + MX7D_PAD_EPDC_SDCE1__GPIO2_IO21,
  380 + MX7D_PAD_EPDC_GDCLK__GPIO2_IO24,
  381 + MX7D_PAD_EPDC_GDOE__GPIO2_IO25,
  382 + MX7D_PAD_EPDC_GDRL__GPIO2_IO26,
  383 + MX7D_PAD_EPDC_GDSP__GPIO2_IO27,
  384 + MX7D_PAD_EPDC_BDR0__GPIO2_IO28,
  385 + MX7D_PAD_EPDC_BDR1__GPIO2_IO29,
  386 +};
  387 +
  388 +vidinfo_t panel_info = {
  389 + .vl_refresh = 85,
  390 + .vl_col = 1024,
  391 + .vl_row = 758,
  392 + .vl_pixclock = 40000000,
  393 + .vl_left_margin = 12,
  394 + .vl_right_margin = 76,
  395 + .vl_upper_margin = 4,
  396 + .vl_lower_margin = 5,
  397 + .vl_hsync = 12,
  398 + .vl_vsync = 2,
  399 + .vl_sync = 0,
  400 + .vl_mode = 0,
  401 + .vl_flag = 0,
  402 + .vl_bpix = 3,
  403 + .cmap = 0,
  404 +};
  405 +
  406 +struct epdc_timing_params panel_timings = {
  407 + .vscan_holdoff = 4,
  408 + .sdoed_width = 10,
  409 + .sdoed_delay = 20,
  410 + .sdoez_width = 10,
  411 + .sdoez_delay = 20,
  412 + .gdclk_hp_offs = 524,
  413 + .gdsp_offs = 327,
  414 + .gdoe_offs = 0,
  415 + .gdclk_offs = 19,
  416 + .num_ce = 1,
  417 +};
  418 +
  419 +static void setup_epdc_power(void)
  420 +{
  421 + /* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */
  422 + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
  423 + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
  424 +
  425 + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
  426 + IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0);
  427 +
  428 + /* Setup epdc voltage */
  429 +
  430 + /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
  431 + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |
  432 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  433 + gpio_request(IMX_GPIO_NR(2, 31), "epdc_pwrstat");
  434 + gpio_direction_input(IMX_GPIO_NR(2, 31));
  435 +
  436 + /* EPDC_VCOM0 - GPIO4[14] for VCOM control */
  437 + imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |
  438 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  439 +
  440 + /* Set as output */
  441 + gpio_request(IMX_GPIO_NR(4, 14), "epdc_vcom");
  442 + gpio_direction_output(IMX_GPIO_NR(4, 14), 1);
  443 +
  444 + /* EPDC_PWRWAKEUP - GPIO2[23] for EPD PMIC WAKEUP */
  445 + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |
  446 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  447 + /* Set as output */
  448 + gpio_request(IMX_GPIO_NR(2, 23), "epdc_pmic");
  449 + gpio_direction_output(IMX_GPIO_NR(2, 23), 1);
  450 +
  451 + /* EPDC_PWRCTRL0 - GPIO2[30] for EPD PWR CTL0 */
  452 + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |
  453 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  454 + /* Set as output */
  455 + gpio_request(IMX_GPIO_NR(2, 30), "epdc_pwr_ctl0");
  456 + gpio_direction_output(IMX_GPIO_NR(2, 30), 1);
  457 +}
  458 +
  459 +static void epdc_enable_pins(void)
  460 +{
  461 + /* epdc iomux settings */
  462 + imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,
  463 + ARRAY_SIZE(epdc_enable_pads));
  464 +}
  465 +
  466 +static void epdc_disable_pins(void)
  467 +{
  468 + /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */
  469 + imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,
  470 + ARRAY_SIZE(epdc_disable_pads));
  471 +}
  472 +
  473 +static void setup_epdc(void)
  474 +{
  475 + /*** epdc Maxim PMIC settings ***/
  476 +
  477 + /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
  478 + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |
  479 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  480 +
  481 + /* EPDC_VCOM0 - GPIO4[14] for VCOM control */
  482 + imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |
  483 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  484 +
  485 + /* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */
  486 + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |
  487 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  488 +
  489 + /* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */
  490 + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |
  491 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  492 +
  493 + /* Set pixel clock rates for EPDC in clock.c */
  494 +
  495 + panel_info.epdc_data.wv_modes.mode_init = 0;
  496 + panel_info.epdc_data.wv_modes.mode_du = 1;
  497 + panel_info.epdc_data.wv_modes.mode_gc4 = 3;
  498 + panel_info.epdc_data.wv_modes.mode_gc8 = 2;
  499 + panel_info.epdc_data.wv_modes.mode_gc16 = 2;
  500 + panel_info.epdc_data.wv_modes.mode_gc32 = 2;
  501 +
  502 + panel_info.epdc_data.epdc_timings = panel_timings;
  503 +
  504 + setup_epdc_power();
  505 +}
  506 +
  507 +void epdc_power_on(void)
  508 +{
  509 + unsigned int reg;
  510 + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
  511 +
  512 + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
  513 + gpio_set_value(IMX_GPIO_NR(2, 30), 1);
  514 + udelay(1000);
  515 +
  516 + /* Enable epdc signal pin */
  517 + epdc_enable_pins();
  518 +
  519 + /* Set PMIC Wakeup to high - enable Display power */
  520 + gpio_set_value(IMX_GPIO_NR(2, 23), 1);
  521 +
  522 + /* Wait for PWRGOOD == 1 */
  523 + while (1) {
  524 + reg = readl(&gpio_regs->gpio_psr);
  525 + if (!(reg & (1 << 31)))
  526 + break;
  527 +
  528 + udelay(100);
  529 + }
  530 +
  531 + /* Enable VCOM */
  532 + gpio_set_value(IMX_GPIO_NR(4, 14), 1);
  533 +
  534 + udelay(500);
  535 +}
  536 +
  537 +void epdc_power_off(void)
  538 +{
  539 + /* Set PMIC Wakeup to low - disable Display power */
  540 + gpio_set_value(IMX_GPIO_NR(2, 23), 0);
  541 +
  542 + /* Disable VCOM */
  543 + gpio_set_value(IMX_GPIO_NR(4, 14), 0);
  544 +
  545 + epdc_disable_pins();
  546 +
  547 + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
  548 + gpio_set_value(IMX_GPIO_NR(2, 30), 0);
  549 +}
  550 +#endif
  551 +
331 552 int board_early_init_f(void)
332 553 {
333 554 setup_iomux_uart();
... ... @@ -354,6 +575,21 @@
354 575  
355 576 #ifdef CONFIG_FSL_QSPI
356 577 board_qspi_init();
  578 +#endif
  579 +
  580 +#ifdef CONFIG_MXC_EPDC
  581 + if (mx7sabre_rev() >= BOARD_REV_B) {
  582 + /*
  583 + * On RevB, GPIO1_IO04 is used for ENET2 EN,
  584 + * so set its output to high to isolate the
  585 + * ENET2 signals for EPDC
  586 + */
  587 + imx_iomux_v3_setup_multiple_pads(epdc_en_pads,
  588 + ARRAY_SIZE(epdc_en_pads));
  589 + gpio_request(IMX_GPIO_NR(1, 4), "epdc_en");
  590 + gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
  591 + }
  592 + setup_epdc();
357 593 #endif
358 594  
359 595 #ifdef CONFIG_MXC_SPI
configs/mx7dsabresd_epdc_defconfig
Diff comments   View file @ ccfa28a
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_MX7=y
  3 +CONFIG_TARGET_MX7DSABRESD=y
  4 +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
  5 +# CONFIG_ARMV7_VIRT is not set
  6 +CONFIG_IMX_RDC=y
  7 +CONFIG_IMX_BOOTAUX=y
  8 +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb"
  9 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
  10 +CONFIG_MXC_EPDC=y
  11 +CONFIG_LCD=y
  12 +CONFIG_BOOTDELAY=3
  13 +# CONFIG_CONSOLE_MUX is not set
  14 +CONFIG_SYS_CONSOLE_IS_IN_ENV=y
  15 +CONFIG_HUSH_PARSER=y
  16 +CONFIG_CMD_BOOTZ=y
  17 +# CONFIG_CMD_IMI is not set
  18 +# CONFIG_CMD_IMLS is not set
  19 +# CONFIG_CMD_XIMG is not set
  20 +# CONFIG_CMD_EXPORTENV is not set
  21 +# CONFIG_CMD_IMPORTENV is not set
  22 +CONFIG_CMD_MEMTEST=y
  23 +CONFIG_CMD_DFU=y
  24 +CONFIG_CMD_GPIO=y
  25 +CONFIG_CMD_I2C=y
  26 +CONFIG_CMD_MMC=y
  27 +CONFIG_CMD_SF=y
  28 +CONFIG_CMD_USB=y
  29 +CONFIG_CMD_USB_MASS_STORAGE=y
  30 +CONFIG_CMD_NET=y
  31 +CONFIG_CMD_DHCP=y
  32 +CONFIG_CMD_PING=y
  33 +CONFIG_CMD_CACHE=y
  34 +CONFIG_CMD_PMIC=y
  35 +CONFIG_CMD_REGULATOR=y
  36 +CONFIG_CMD_EXT2=y
  37 +CONFIG_CMD_EXT4=y
  38 +CONFIG_CMD_EXT4_WRITE=y
  39 +CONFIG_CMD_FAT=y
  40 +CONFIG_OF_CONTROL=y
  41 +CONFIG_DFU_MMC=y
  42 +CONFIG_DFU_RAM=y
  43 +CONFIG_DM_GPIO=y
  44 +CONFIG_DM_74X164=y
  45 +CONFIG_DM_I2C=y
  46 +CONFIG_DM_MMC=y
  47 +CONFIG_MMC_IO_VOLTAGE=y
  48 +CONFIG_MMC_UHS_SUPPORT=y
  49 +CONFIG_MMC_HS200_SUPPORT=y
  50 +CONFIG_SPI_FLASH=y
  51 +CONFIG_SPI_FLASH_EON=y
  52 +CONFIG_PINCTRL=y
  53 +CONFIG_PINCTRL_IMX7=y
  54 +CONFIG_DM_PMIC=y
  55 +CONFIG_DM_PMIC_PFUZE100=y
  56 +CONFIG_DM_REGULATOR=y
  57 +CONFIG_DM_REGULATOR_PFUZE100=y
  58 +CONFIG_DM_REGULATOR_FIXED=y
  59 +CONFIG_DM_REGULATOR_GPIO=y
  60 +CONFIG_DM_SPI=y
  61 +CONFIG_SOFT_SPI=y
  62 +CONFIG_USB=y
  63 +CONFIG_DM_USB=y
  64 +CONFIG_USB_EHCI_HCD=y
  65 +CONFIG_MXC_USB_OTG_HACTIVE=y
  66 +CONFIG_USB_STORAGE=y
  67 +CONFIG_USB_GADGET=y
  68 +CONFIG_USB_GADGET_MANUFACTURER="FSL"
  69 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525
  70 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
  71 +CONFIG_CI_UDC=y
  72 +CONFIG_USB_GADGET_DOWNLOAD=y
  73 +CONFIG_USB_HOST_ETHER=y
  74 +CONFIG_USB_ETHER_ASIX=y
  75 +CONFIG_VIDEO=y
  76 +CONFIG_ERRNO_STR=y
include/configs/mx7dsabresd.h
Diff comments   View file @ ccfa28a
... ... @@ -20,6 +20,7 @@
20 20 #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
21 21  
22 22 /* Network */
  23 +#ifdef CONFIG_DM_ETH
23 24 #define CONFIG_FEC_MXC
24 25 #define CONFIG_MII
25 26 #define CONFIG_FEC_XCV_TYPE RGMII
... ... @@ -38,6 +39,7 @@
38 39 #endif
39 40  
40 41 #define CONFIG_FEC_MXC_MDIO_BASE ENET_IPS_BASE_ADDR
  42 +#endif
41 43  
42 44 /* MMC Config*/
43 45 #define CONFIG_SYS_FSL_ESDHC_ADDR 0
... ... @@ -234,6 +236,31 @@
234 236 #define CONFIG_BMP_16BPP
235 237 #define CONFIG_VIDEO_BMP_RLE8
236 238 #define CONFIG_VIDEO_BMP_LOGO
  239 +#endif
  240 +
  241 +/* #define CONFIG_SPLASH_SCREEN*/
  242 +/* #define CONFIG_MXC_EPDC*/
  243 +
  244 +/*
  245 + * SPLASH SCREEN Configs
  246 + */
  247 +#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MXC_EPDC)
  248 +/*
  249 + * Framebuffer and LCD
  250 + */
  251 +#define CONFIG_CMD_BMP
  252 +#define CONFIG_LCD
  253 +
  254 +#undef LCD_TEST_PATTERN
  255 +/* #define CONFIG_SPLASH_IS_IN_MMC 1 */
  256 +#define LCD_BPP LCD_MONOCHROME
  257 +/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */
  258 +
  259 +#define CONFIG_WAVEFORM_BUF_SIZE 0x400000
  260 +#endif
  261 +
  262 +#if defined(CONFIG_MXC_EPDC) && defined(CONFIG_SYS_USE_QSPI)
  263 +#error "EPDC Pins conflicts QSPI, Either EPDC or QSPI can be enabled!"
237 264 #endif
238 265  
239 266 #ifdef CONFIG_FSL_QSPI