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Commit cf91023fc464d0dfb16fd1273a2218fba5a98892

Authored by Peng Fan
Committed by Ye Li
1 parent 9ad94817a5
Exists in smarc_8mq-imx_v2020.04_5.4.24_2.1.0 and in 3 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, smarc-8m-android-10.0.0_2.6.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0

MLK-14418-8 imx: mx7dsabresd: add epdc support 

Add epdc support from v2019.04.
Add a epdc specified DTS file for using epdc

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit ab2f9e136f5da034a8335dc8ca276a54367132e8)
(cherry picked from commit ccfa28aec4093ac30a9b76d973f0288ab9c8f92c)
(cherry picked from commit 86f7a2c50aeb4d5c12f7159356ea782f48905b19)

Showing 5 changed files with 471 additions and 0 deletions Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ cf91023
... ... @@ -703,6 +703,7 @@
703 703  
704 704 dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
705 705 imx7d-sdb-qspi.dtb \
  706 + imx7d-sdb-epdc.dtb \
706 707 imx7d-sdb-gpmi-weim.dtb \
707 708 imx7d-sdb-reva.dtb \
708 709 imx7-colibri-emmc.dtb \
arch/arm/dts/imx7d-sdb-epdc.dts
Diff comments   View file @ cf91023
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright (C) 2015 Freescale Semiconductor, Inc.
  4 + *
  5 + */
  6 +
  7 +#include "imx7d-sdb.dts"
  8 +
  9 +&epdc {
  10 + status = "okay";
  11 +};
  12 +
  13 +&fec1 {
  14 + status = "okay";
  15 +};
  16 +
  17 +&fec2 {
  18 + status = "disabled";
  19 +};
  20 +
  21 +&reg_can2_3v3 {
  22 + status = "disabled";
  23 +};
  24 +
  25 +&reg_fec2_3v3 {
  26 + status = "disabled";
  27 +};
  28 +
  29 +&flexcan2 {
  30 + status = "disabled";
  31 +};
  32 +
  33 +&max17135 {
  34 + status = "okay";
  35 +};
  36 +
  37 +&sii902x {
  38 + status = "disabled";
  39 +};
  40 +
  41 +&sim1 {
  42 + status = "disabled";
  43 +};
  44 +
  45 +&uart5 {
  46 + status = "disabled";
  47 +};
  48 +
  49 +&i2c3 {
  50 + elan@10 {
  51 + pinctrl-names = "default";
  52 + pinctrl-0 = <&pinctrl_epdc_elan_touch>;
  53 + compatible = "elan,elan-touch";
  54 + reg = <0x10>;
  55 + interrupt-parent = <&gpio6>;
  56 + interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
  57 + gpio_elan_cs = <&gpio6 13 0>;
  58 + gpio_elan_rst = <&gpio6 15 0>;
  59 + gpio_intr = <&gpio6 12 0>;
  60 + status = "okay";
  61 + };
  62 +};
board/freescale/mx7dsabresd/mx7dsabresd.c
Diff comments   View file @ cf91023
... ... @@ -24,6 +24,10 @@
24 24 #include <i2c.h>
25 25 #include <asm/mach-imx/mxc_i2c.h>
26 26 #include <asm/arch/crm_regs.h>
  27 +#if defined(CONFIG_MXC_EPDC)
  28 +#include <lcd.h>
  29 +#include <mxc_epdc_fb.h>
  30 +#endif
27 31 #include <asm/mach-imx/video.h>
28 32  
29 33 DECLARE_GLOBAL_DATA_PTR;
... ... @@ -41,6 +45,8 @@
41 45  
42 46 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
43 47  
  48 +#define EPDC_PAD_CTRL 0x0
  49 +
44 50 #ifdef CONFIG_MXC_SPI
45 51 static iomux_v3_cfg_t const ecspi3_pads[] = {
46 52 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
... ... @@ -312,6 +318,263 @@
312 318 }
313 319 #endif
314 320  
  321 +#ifdef CONFIG_MXC_EPDC
  322 +iomux_v3_cfg_t const epdc_en_pads[] = {
  323 + MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(NO_PAD_CTRL),
  324 +};
  325 +
  326 +static iomux_v3_cfg_t const epdc_enable_pads[] = {
  327 + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  328 + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  329 + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  330 + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  331 + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  332 + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  333 + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  334 + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  335 + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  336 + MX7D_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  337 + MX7D_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  338 + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  339 + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  340 + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  341 + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  342 + MX7D_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  343 + MX7D_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  344 + MX7D_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  345 + MX7D_PAD_EPDC_BDR0__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  346 + MX7D_PAD_EPDC_BDR1__EPDC_BDR1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  347 +};
  348 +
  349 +static iomux_v3_cfg_t const epdc_disable_pads[] = {
  350 + MX7D_PAD_EPDC_DATA00__GPIO2_IO0,
  351 + MX7D_PAD_EPDC_DATA01__GPIO2_IO1,
  352 + MX7D_PAD_EPDC_DATA02__GPIO2_IO2,
  353 + MX7D_PAD_EPDC_DATA03__GPIO2_IO3,
  354 + MX7D_PAD_EPDC_DATA04__GPIO2_IO4,
  355 + MX7D_PAD_EPDC_DATA05__GPIO2_IO5,
  356 + MX7D_PAD_EPDC_DATA06__GPIO2_IO6,
  357 + MX7D_PAD_EPDC_DATA07__GPIO2_IO7,
  358 + MX7D_PAD_EPDC_SDCLK__GPIO2_IO16,
  359 + MX7D_PAD_EPDC_SDLE__GPIO2_IO17,
  360 + MX7D_PAD_EPDC_SDOE__GPIO2_IO18,
  361 + MX7D_PAD_EPDC_SDSHR__GPIO2_IO19,
  362 + MX7D_PAD_EPDC_SDCE0__GPIO2_IO20,
  363 + MX7D_PAD_EPDC_SDCE1__GPIO2_IO21,
  364 + MX7D_PAD_EPDC_GDCLK__GPIO2_IO24,
  365 + MX7D_PAD_EPDC_GDOE__GPIO2_IO25,
  366 + MX7D_PAD_EPDC_GDRL__GPIO2_IO26,
  367 + MX7D_PAD_EPDC_GDSP__GPIO2_IO27,
  368 + MX7D_PAD_EPDC_BDR0__GPIO2_IO28,
  369 + MX7D_PAD_EPDC_BDR1__GPIO2_IO29,
  370 +};
  371 +
  372 +vidinfo_t panel_info = {
  373 + .vl_refresh = 85,
  374 + .vl_col = 1024,
  375 + .vl_row = 758,
  376 + .vl_pixclock = 40000000,
  377 + .vl_left_margin = 12,
  378 + .vl_right_margin = 76,
  379 + .vl_upper_margin = 4,
  380 + .vl_lower_margin = 5,
  381 + .vl_hsync = 12,
  382 + .vl_vsync = 2,
  383 + .vl_sync = 0,
  384 + .vl_mode = 0,
  385 + .vl_flag = 0,
  386 + .vl_bpix = 3,
  387 + .cmap = 0,
  388 +};
  389 +
  390 +struct epdc_timing_params panel_timings = {
  391 + .vscan_holdoff = 4,
  392 + .sdoed_width = 10,
  393 + .sdoed_delay = 20,
  394 + .sdoez_width = 10,
  395 + .sdoez_delay = 20,
  396 + .gdclk_hp_offs = 524,
  397 + .gdsp_offs = 327,
  398 + .gdoe_offs = 0,
  399 + .gdclk_offs = 19,
  400 + .num_ce = 1,
  401 +};
  402 +
  403 +struct gpio_desc epd_pwrstat_desc;
  404 +struct gpio_desc epd_vcom_desc;
  405 +struct gpio_desc epd_wakeup_desc;
  406 +struct gpio_desc epd_pwr_ctl0_desc;
  407 +
  408 +static void setup_epdc_power(void)
  409 +{
  410 + int ret;
  411 +
  412 + /* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */
  413 + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
  414 + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
  415 +
  416 + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
  417 + IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0);
  418 +
  419 + /* Setup epdc voltage */
  420 +
  421 + /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
  422 + ret = dm_gpio_lookup_name("GPIO2_31", &epd_pwrstat_desc);
  423 + if (ret) {
  424 + printf("%s lookup GPIO2_31 failed ret = %d\n", __func__, ret);
  425 + return;
  426 + }
  427 +
  428 + ret = dm_gpio_request(&epd_pwrstat_desc, "epdc_pwrstat");
  429 + if (ret) {
  430 + printf("%s request epdc_pwrstat failed ret = %d\n", __func__, ret);
  431 + return;
  432 + }
  433 +
  434 + dm_gpio_set_dir_flags(&epd_pwrstat_desc, GPIOD_IS_IN);
  435 +
  436 + /* EPDC_VCOM0 - GPIO4[14] for VCOM control */
  437 + /* Set as output */
  438 + ret = dm_gpio_lookup_name("GPIO4_14", &epd_vcom_desc);
  439 + if (ret) {
  440 + printf("%s lookup GPIO4_14 failed ret = %d\n", __func__, ret);
  441 + return;
  442 + }
  443 +
  444 + ret = dm_gpio_request(&epd_vcom_desc, "epdc_vcom");
  445 + if (ret) {
  446 + printf("%s request epdc_vcom failed ret = %d\n", __func__, ret);
  447 + return;
  448 + }
  449 +
  450 + dm_gpio_set_dir_flags(&epd_vcom_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  451 +
  452 + /* EPDC_PWRWAKEUP - GPIO2[23] for EPD PMIC WAKEUP */
  453 + /* Set as output */
  454 + ret = dm_gpio_lookup_name("GPIO2_23", &epd_wakeup_desc);
  455 + if (ret) {
  456 + printf("%s lookup GPIO2_23 failed ret = %d\n", __func__, ret);
  457 + return;
  458 + }
  459 +
  460 + ret = dm_gpio_request(&epd_wakeup_desc, "epdc_pmic");
  461 + if (ret) {
  462 + printf("%s request epdc_pmic failed ret = %d\n", __func__, ret);
  463 + return;
  464 + }
  465 +
  466 + dm_gpio_set_dir_flags(&epd_wakeup_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  467 +
  468 + /* EPDC_PWRCTRL0 - GPIO2[30] for EPD PWR CTL0 */
  469 + /* Set as output */
  470 + ret = dm_gpio_lookup_name("GPIO2_30", &epd_pwr_ctl0_desc);
  471 + if (ret) {
  472 + printf("%s lookup GPIO2_30 failed ret = %d\n", __func__, ret);
  473 + return;
  474 + }
  475 +
  476 + ret = dm_gpio_request(&epd_pwr_ctl0_desc, "epdc_pwr_ctl0");
  477 + if (ret) {
  478 + printf("%s request epdc_pwr_ctl0 failed ret = %d\n", __func__, ret);
  479 + return;
  480 + }
  481 +
  482 + dm_gpio_set_dir_flags(&epd_pwr_ctl0_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  483 +}
  484 +
  485 +static void epdc_enable_pins(void)
  486 +{
  487 + /* epdc iomux settings */
  488 + imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,
  489 + ARRAY_SIZE(epdc_enable_pads));
  490 +}
  491 +
  492 +static void epdc_disable_pins(void)
  493 +{
  494 + /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */
  495 + imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,
  496 + ARRAY_SIZE(epdc_disable_pads));
  497 +}
  498 +
  499 +static void setup_epdc(void)
  500 +{
  501 + /*** epdc Maxim PMIC settings ***/
  502 +
  503 + /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
  504 + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |
  505 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  506 +
  507 + /* EPDC_VCOM0 - GPIO4[14] for VCOM control */
  508 + imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |
  509 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  510 +
  511 + /* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */
  512 + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |
  513 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  514 +
  515 + /* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */
  516 + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |
  517 + MUX_PAD_CTRL(EPDC_PAD_CTRL));
  518 +
  519 + /* Set pixel clock rates for EPDC in clock.c */
  520 +
  521 + panel_info.epdc_data.wv_modes.mode_init = 0;
  522 + panel_info.epdc_data.wv_modes.mode_du = 1;
  523 + panel_info.epdc_data.wv_modes.mode_gc4 = 3;
  524 + panel_info.epdc_data.wv_modes.mode_gc8 = 2;
  525 + panel_info.epdc_data.wv_modes.mode_gc16 = 2;
  526 + panel_info.epdc_data.wv_modes.mode_gc32 = 2;
  527 +
  528 + panel_info.epdc_data.epdc_timings = panel_timings;
  529 +
  530 + setup_epdc_power();
  531 +}
  532 +
  533 +void epdc_power_on(void)
  534 +{
  535 + unsigned int reg;
  536 + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
  537 +
  538 + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
  539 + dm_gpio_set_value(&epd_pwr_ctl0_desc, 1);
  540 + udelay(1000);
  541 +
  542 + /* Enable epdc signal pin */
  543 + epdc_enable_pins();
  544 +
  545 + /* Set PMIC Wakeup to high - enable Display power */
  546 + dm_gpio_set_value(&epd_wakeup_desc, 1);
  547 +
  548 + /* Wait for PWRGOOD == 1 */
  549 + while (1) {
  550 + reg = readl(&gpio_regs->gpio_psr);
  551 + if (!(reg & (1 << 31)))
  552 + break;
  553 +
  554 + udelay(100);
  555 + }
  556 +
  557 + /* Enable VCOM */
  558 + dm_gpio_set_value(&epd_vcom_desc, 1);
  559 +
  560 + udelay(500);
  561 +}
  562 +
  563 +void epdc_power_off(void)
  564 +{
  565 + /* Set PMIC Wakeup to low - disable Display power */
  566 + dm_gpio_set_value(&epd_wakeup_desc, 0);
  567 +
  568 + /* Disable VCOM */
  569 + dm_gpio_set_value(&epd_vcom_desc, 0);
  570 +
  571 + epdc_disable_pins();
  572 +
  573 + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
  574 + dm_gpio_set_value(&epd_pwr_ctl0_desc, 0);
  575 +}
  576 +#endif
  577 +
315 578 int board_early_init_f(void)
316 579 {
317 580 setup_iomux_uart();
... ... @@ -334,6 +597,35 @@
334 597  
335 598 #ifdef CONFIG_FSL_QSPI
336 599 board_qspi_init();
  600 +#endif
  601 +
  602 +#ifdef CONFIG_MXC_EPDC
  603 + if (mx7sabre_rev() >= BOARD_REV_B) {
  604 + int ret;
  605 + struct gpio_desc desc;
  606 + /*
  607 + * From RevB, GPIO1_IO04 is used for ENET2 EN,
  608 + * so set its output to high to isolate the
  609 + * ENET2 signals for EPDC
  610 + */
  611 + imx_iomux_v3_setup_multiple_pads(epdc_en_pads,
  612 + ARRAY_SIZE(epdc_en_pads));
  613 +
  614 + ret = dm_gpio_lookup_name("GPIO1_4", &desc);
  615 + if (ret) {
  616 + printf("%s lookup GPIO1_4 failed ret = %d\n", __func__, ret);
  617 + return -ENODEV;
  618 + }
  619 +
  620 + ret = dm_gpio_request(&desc, "epdc_en");
  621 + if (ret) {
  622 + printf("%s request epdc_en failed ret = %d\n", __func__, ret);
  623 + return -ENODEV;
  624 + }
  625 +
  626 + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  627 + }
  628 + setup_epdc();
337 629 #endif
338 630  
339 631 #ifdef CONFIG_MXC_SPI
configs/mx7dsabresd_epdc_defconfig
Diff comments   View file @ cf91023
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_MX7=y
  3 +CONFIG_ENV_SIZE=0x2000
  4 +CONFIG_ENV_OFFSET=0xE0000
  5 +CONFIG_DM_GPIO=y
  6 +CONFIG_TARGET_MX7DSABRESD=y
  7 +CONFIG_NR_DRAM_BANKS=1
  8 +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
  9 +# CONFIG_ARMV7_VIRT is not set
  10 +CONFIG_IMX_RDC=y
  11 +CONFIG_IMX_BOOTAUX=y
  12 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
  13 +CONFIG_MXC_EPDC=y
  14 +CONFIG_LCD=y
  15 +CONFIG_CMD_BMP=y
  16 +CONFIG_BOOTDELAY=3
  17 +# CONFIG_CONSOLE_MUX is not set
  18 +CONFIG_SYS_CONSOLE_IS_IN_ENV=y
  19 +CONFIG_BOUNCE_BUFFER=y
  20 +CONFIG_HUSH_PARSER=y
  21 +CONFIG_CMD_BOOTZ=y
  22 +# CONFIG_BOOTM_NETBSD is not set
  23 +# CONFIG_BOOTM_PLAN9 is not set
  24 +# CONFIG_BOOTM_RTEMS is not set
  25 +# CONFIG_CMD_IMLS is not set
  26 +# CONFIG_CMD_XIMG is not set
  27 +# CONFIG_CMD_EXPORTENV is not set
  28 +# CONFIG_CMD_IMPORTENV is not set
  29 +CONFIG_CMD_MEMTEST=y
  30 +CONFIG_CMD_DFU=y
  31 +CONFIG_CMD_GPIO=y
  32 +CONFIG_CMD_I2C=y
  33 +CONFIG_CMD_MMC=y
  34 +CONFIG_CMD_SF=y
  35 +CONFIG_CMD_USB=y
  36 +CONFIG_CMD_USB_MASS_STORAGE=y
  37 +CONFIG_CMD_DHCP=y
  38 +CONFIG_CMD_MII=y
  39 +CONFIG_CMD_PING=y
  40 +CONFIG_CMD_CACHE=y
  41 +CONFIG_CMD_PMIC=y
  42 +CONFIG_CMD_REGULATOR=y
  43 +CONFIG_CMD_EXT2=y
  44 +CONFIG_CMD_EXT4=y
  45 +CONFIG_CMD_EXT4_WRITE=y
  46 +CONFIG_CMD_FAT=y
  47 +CONFIG_OF_CONTROL=y
  48 +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-epdc"
  49 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
  50 +CONFIG_DFU_MMC=y
  51 +CONFIG_DFU_RAM=y
  52 +CONFIG_DM_74X164=y
  53 +CONFIG_DM_I2C=y
  54 +CONFIG_DM_MMC=y
  55 +CONFIG_SUPPORT_EMMC_BOOT=y
  56 +CONFIG_MMC_IO_VOLTAGE=y
  57 +CONFIG_MMC_UHS_SUPPORT=y
  58 +CONFIG_MMC_HS200_SUPPORT=y
  59 +CONFIG_FSL_USDHC=y
  60 +CONFIG_PHYLIB=y
  61 +CONFIG_PHY_BROADCOM=y
  62 +CONFIG_DM_ETH=y
  63 +CONFIG_DM_ETH_PHY=y
  64 +CONFIG_FEC_MXC=y
  65 +CONFIG_RGMII=y
  66 +CONFIG_MII=y
  67 +CONFIG_PINCTRL=y
  68 +CONFIG_PINCTRL_IMX7=y
  69 +CONFIG_DM_PMIC=y
  70 +CONFIG_DM_PMIC_PFUZE100=y
  71 +CONFIG_DM_REGULATOR=y
  72 +CONFIG_DM_REGULATOR_PFUZE100=y
  73 +CONFIG_DM_REGULATOR_FIXED=y
  74 +CONFIG_DM_REGULATOR_GPIO=y
  75 +CONFIG_SPI=y
  76 +CONFIG_DM_SPI=y
  77 +CONFIG_SOFT_SPI=y
  78 +CONFIG_USB=y
  79 +CONFIG_DM_USB=y
  80 +CONFIG_USB_EHCI_HCD=y
  81 +CONFIG_MXC_USB_OTG_HACTIVE=y
  82 +CONFIG_USB_STORAGE=y
  83 +CONFIG_USB_GADGET=y
  84 +CONFIG_USB_GADGET_MANUFACTURER="FSL"
  85 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525
  86 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
  87 +CONFIG_CI_UDC=y
  88 +CONFIG_USB_GADGET_DOWNLOAD=y
  89 +CONFIG_USB_HOST_ETHER=y
  90 +CONFIG_USB_ETHER_ASIX=y
  91 +CONFIG_VIDEO=y
  92 +CONFIG_ERRNO_STR=y
include/configs/mx7dsabresd.h
Diff comments   View file @ cf91023
... ... @@ -259,6 +259,30 @@
259 259 #define CONFIG_IMX_VIDEO_SKIP
260 260 #endif
261 261  
  262 +/* #define CONFIG_SPLASH_SCREEN*/
  263 +/* #define CONFIG_MXC_EPDC*/
  264 +
  265 +/*
  266 + * SPLASH SCREEN Configs
  267 + */
  268 +#if defined(CONFIG_MXC_EPDC)
  269 +/*
  270 + * Framebuffer and LCD
  271 + */
  272 +#define CONFIG_SPLASH_SCREEN
  273 +
  274 +#undef LCD_TEST_PATTERN
  275 +/* #define CONFIG_SPLASH_IS_IN_MMC 1 */
  276 +#define LCD_BPP LCD_MONOCHROME
  277 +/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */
  278 +
  279 +#define CONFIG_WAVEFORM_BUF_SIZE 0x400000
  280 +#endif
  281 +
  282 +#if defined(CONFIG_MXC_EPDC) && defined(CONFIG_FSL_QSPI)
  283 +#error "EPDC Pins conflicts QSPI, Either EPDC or QSPI can be enabled!"
  284 +#endif
  285 +
262 286 #ifdef CONFIG_FSL_QSPI
263 287 #define CONFIG_SYS_FSL_QSPI_AHB
264 288 #define FSL_QSPI_FLASH_NUM 1