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Commit cdbdde3f56e1752d7a3f479693251f0ab459431a

Authored by Fabio Estevam
Committed by Stefano Babic
1 parent 573960aca5
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

mx6qsabreauto: Add parallel NOR flash support 

mx6sabreauto boards come with 32 MiB of parallel NOR flash.

Add support for it:

U-Boot 2015.01-rc1-18107-g1543636-dirty (Nov 14 2014 - 11:11:04)

CPU:   Freescale i.MX6Q rev1.2 at 792 MHz
Reset cause: POR
Board: MX6Q-Sabreauto revA
I2C:   ready
DRAM:  2 GiB
Flash: 32 MiB
NAND:  0 MiB

Due to pin conflict with I2C3, only define configure I2C3 IOMUX when flash is
not used.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

Showing 2 changed files with 89 additions and 1 deletions Side-by-side Diff

board/freescale/mx6qsabreauto/mx6qsabreauto.c
Diff comments   View file @ cdbdde3
... ... @@ -53,6 +53,10 @@
53 53  
54 54 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
55 55  
  56 +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  57 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  58 + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  59 +
56 60 int dram_init(void)
57 61 {
58 62 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
... ... @@ -97,6 +101,7 @@
97 101 }
98 102 };
99 103  
  104 +#ifndef CONFIG_SYS_FLASH_CFI
100 105 /*
101 106 * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
102 107 * Compass Sensor, Accelerometer, Res Touch
... ... @@ -113,6 +118,7 @@
113 118 .gp = IMX_GPIO_NR(3, 18)
114 119 }
115 120 };
  121 +#endif
116 122  
117 123 static iomux_v3_cfg_t const i2c3_pads[] = {
118 124 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
... ... @@ -160,6 +166,75 @@
160 166 return 0;
161 167 }
162 168  
  169 +static iomux_v3_cfg_t const eimnor_pads[] = {
  170 + MX6_PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  171 + MX6_PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  172 + MX6_PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  173 + MX6_PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  174 + MX6_PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  175 + MX6_PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  176 + MX6_PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  177 + MX6_PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  178 + MX6_PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  179 + MX6_PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  180 + MX6_PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  181 + MX6_PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  182 + MX6_PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  183 + MX6_PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  184 + MX6_PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  185 + MX6_PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  186 + MX6_PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  187 + MX6_PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  188 + MX6_PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  189 + MX6_PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  190 + MX6_PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  191 + MX6_PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  192 + MX6_PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  193 + MX6_PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  194 + MX6_PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  195 + MX6_PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  196 + MX6_PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  197 + MX6_PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
  198 + MX6_PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  199 + MX6_PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  200 + MX6_PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  201 + MX6_PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  202 + MX6_PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  203 + MX6_PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  204 + MX6_PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  205 + MX6_PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  206 + MX6_PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  207 + MX6_PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  208 + MX6_PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  209 + MX6_PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
  210 + MX6_PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  211 + MX6_PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL),
  212 + MX6_PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  213 +};
  214 +
  215 +static void eimnor_cs_setup(void)
  216 +{
  217 + struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
  218 +
  219 + writel(0x00020181, &weim_regs->cs0gcr1);
  220 + writel(0x00000001, &weim_regs->cs0gcr2);
  221 + writel(0x0a020000, &weim_regs->cs0rcr1);
  222 + writel(0x0000c000, &weim_regs->cs0rcr2);
  223 + writel(0x0804a240, &weim_regs->cs0wcr1);
  224 + writel(0x00000120, &weim_regs->wcr);
  225 +
  226 + set_chipselect_size(CS0_128);
  227 +}
  228 +
  229 +static void setup_iomux_eimnor(void)
  230 +{
  231 + imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
  232 +
  233 + gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
  234 +
  235 + eimnor_cs_setup();
  236 +}
  237 +
163 238 static void setup_iomux_enet(void)
164 239 {
165 240 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
... ... @@ -402,6 +477,7 @@
402 477 #ifdef CONFIG_NAND_MXS
403 478 setup_gpmi_nand();
404 479 #endif
  480 +
405 481 return 0;
406 482 }
407 483  
408 484  
409 485  
... ... @@ -415,11 +491,13 @@
415 491 /* I2C 3 Steer */
416 492 gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
417 493 imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
  494 +#ifndef CONFIG_SYS_FLASH_CFI
418 495 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
419   -
  496 +#endif
420 497 gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
421 498 imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
422 499  
  500 + setup_iomux_eimnor();
423 501 return 0;
424 502 }
425 503  
include/configs/mx6qsabreauto.h
Diff comments   View file @ cdbdde3
... ... @@ -37,6 +37,16 @@
37 37  
38 38 #include "mx6sabre_common.h"
39 39  
  40 +#undef CONFIG_SYS_NO_FLASH
  41 +#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
  42 +#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024)
  43 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  44 +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  45 +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
  46 +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
  47 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
  48 +#define CONFIG_SYS_FLASH_EMPTY_INFO
  49 +
40 50 #define CONFIG_SYS_FSL_USDHC_NUM 2
41 51 #if defined(CONFIG_ENV_IS_IN_MMC)
42 52 #define CONFIG_SYS_MMC_ENV_DEV 0