ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973, 621766

RX51 has a secure logic which uses different parameters compared to traditional implementation. So, make the generic secure acr write over-ride-able by board file and refactor rx51 code to use this. While at it, enable the OMAP3 specific errata code for 454179, 430973, 621766. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>

ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973, 621766
RX51 has a secure logic which uses different parameters compared to traditional implementation. So, make the generic secure acr write over-ride-able by board file and refactor rx51 code to use this. While at it, enable the OMAP3 specific errata code for 454179, 430973, 621766. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Nishanth Menon · Tom Rini
1 parent c6f90e1418
Showing 4 changed files with 37 additions and 32 deletions Side-by-side Diff
arch/arm/cpu/armv7/omap3/board.c
arch/arm/include/asm/arch-omap3/sys_proto.h
board/nokia/rx51/rx51.c
include/configs/nokia_rx51.h
@@ -415,31 +415,30 @@
 	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
 }
  
+void __weak omap3_set_aux_cr_secure(u32 acr)
+{
+	struct emu_hal_params emu_romcode_params;
+
+	emu_romcode_params.num_params = 1;
+	emu_romcode_params.param1 = acr;
+	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
+			       (u32 *)&emu_romcode_params);
+}
+
 void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
 			  u32 cpu_variant, u32 cpu_rev)
 {
-	if (get_device_type() == GP_DEVICE) {
+	/* Write ACR - affects secure banked bits */
+	if (get_device_type() == GP_DEVICE)
 		omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
-	} else {
-		struct emu_hal_params emu_romcode_params;
-		emu_romcode_params.num_params = 1;
-		emu_romcode_params.param1 = acr;
-		omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
-				       (u32 *)&emu_romcode_params);
-	}
-}
+	else
+		omap3_set_aux_cr_secure(acr);
  
-static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
-{
-	u32 acr;
-
-	/* Read ACR */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
-	acr &= ~clear_bits;
-	acr |= set_bits;
-	v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
+	/* Write ACR - affects non-secure banked bits - some erratas need it */
+	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
 }
  
+
 #ifndef CONFIG_SYS_L2CACHE_OFF
 static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
 {
  
@@ -449,9 +448,8 @@
 	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
 	acr &= ~clear_bits;
 	acr |= set_bits;
+	v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
  
-	/* Write ACR - affects non-secure banked bits */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
 }
  
 /* Invalidate the entire L2 cache from secure mode */
  
@@ -470,10 +468,9 @@
  
 void v7_outer_cache_enable(void)
 {
-	/* Set L2EN */
-	omap3_update_aux_cr_secure(0x2, 0);
  
 	/*
+	 * Set L2EN
 	 * On some revisions L2EN bit is banked on some revisions it's not
 	 * No harm in setting both banked bits(in fact this is required
 	 * by an erratum)
  
@@ -483,10 +480,8 @@
  
 void omap3_outer_cache_disable(void)
 {
-	/* Clear L2EN */
-	omap3_update_aux_cr_secure(0, 0x2);
-
 	/*
+	 * Clear L2EN
 	 * On some revisions L2EN bit is banked on some revisions it's not
 	 * No harm in clearing both banked bits(in fact this is required
 	 * by an erratum)
@@ -73,6 +73,7 @@
 void dieid_num_r(void);
 void get_dieid(u32 *id);
 void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
+void omap3_set_aux_cr_secure(u32 acr);
 u32 warm_reset(void);
 #endif
@@ -341,6 +341,17 @@
 	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
 }
  
+void omap3_set_aux_cr_secure(u32 acr)
+{
+	struct emu_hal_params_rx51 emu_romcode_params = { 0, };
+
+	emu_romcode_params.num_params = 2;
+	emu_romcode_params.param1 = acr;
+
+	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
+			       (u32 *)&emu_romcode_params);
+}
+
 /*
  * Routine: omap3_update_aux_cr_secure_rx51
  * Description: Modify the contents Auxiliary Control Register.
  
@@ -350,19 +361,13 @@
  */
 static void omap3_update_aux_cr_secure_rx51(u32 set_bits, u32 clear_bits)
 {
-	struct emu_hal_params_rx51 emu_romcode_params = { 0, };
 	u32 acr;
  
 	/* Read ACR */
 	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
 	acr &= ~clear_bits;
 	acr |= set_bits;
-
-	emu_romcode_params.num_params = 2;
-	emu_romcode_params.param1 = acr;
-
-	omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
-				(u32 *)&emu_romcode_params);
+	omap3_set_aux_cr_secure(acr);
 }
  
 /*
@@ -29,6 +29,10 @@
 #define CONFIG_SYS_L2CACHE_OFF		/* pretend there is no L2 CACHE */
 #define CONFIG_OMAP_COMMON
 #define CONFIG_SYS_GENERIC_BOARD
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
  
 #define CONFIG_MACH_TYPE		MACH_TYPE_NOKIA_RX51
...	...	@@ -415,31 +415,30 @@
415	415	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
416	416	}
417	417
	418	+void __weak omap3_set_aux_cr_secure(u32 acr)
	419	+{
	420	+ struct emu_hal_params emu_romcode_params;
	421	+
	422	+ emu_romcode_params.num_params = 1;
	423	+ emu_romcode_params.param1 = acr;
	424	+ omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
	425	+ (u32 *)&emu_romcode_params);
	426	+}
	427	+
418	428	void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
419	429	u32 cpu_variant, u32 cpu_rev)
420	430	{
421		- if (get_device_type() == GP_DEVICE) {
	431	+ /* Write ACR - affects secure banked bits */
	432	+ if (get_device_type() == GP_DEVICE)
422	433	omap_smc1(OMAP3_GP_ROMCODE_API_WRITE_ACR, acr);
423		- } else {
424		- struct emu_hal_params emu_romcode_params;
425		- emu_romcode_params.num_params = 1;
426		- emu_romcode_params.param1 = acr;
427		- omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
428		- (u32 *)&emu_romcode_params);
429		- }
430		-}
	434	+ else
	435	+ omap3_set_aux_cr_secure(acr);
431	436
432		-static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
433		-{
434		- u32 acr;
435		-
436		- /* Read ACR */
437		- asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
438		- acr &= ~clear_bits;
439		- acr \|= set_bits;
440		- v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
	437	+ /* Write ACR - affects non-secure banked bits - some erratas need it */
	438	+ asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
441	439	}
442	440
	441	+
443	442	#ifndef CONFIG_SYS_L2CACHE_OFF
444	443	static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
445	444	{
446	445
...	...	@@ -449,9 +448,8 @@
449	448	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
450	449	acr &= ~clear_bits;
451	450	acr \|= set_bits;
	451	+ v7_arch_cp15_set_acr(acr, 0, 0, 0, 0);
452	452
453		- /* Write ACR - affects non-secure banked bits */
454		- asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
455	453	}
456	454
457	455	/* Invalidate the entire L2 cache from secure mode */
458	456
...	...	@@ -470,10 +468,9 @@
470	468
471	469	void v7_outer_cache_enable(void)
472	470	{
473		- /* Set L2EN */
474		- omap3_update_aux_cr_secure(0x2, 0);
475	471
476	472	/*
	473	+ * Set L2EN
477	474	* On some revisions L2EN bit is banked on some revisions it's not
478	475	* No harm in setting both banked bits(in fact this is required
479	476	* by an erratum)
480	477
...	...	@@ -483,10 +480,8 @@
483	480
484	481	void omap3_outer_cache_disable(void)
485	482	{
486		- /* Clear L2EN */
487		- omap3_update_aux_cr_secure(0, 0x2);
488		-
489	483	/*
	484	+ * Clear L2EN
490	485	* On some revisions L2EN bit is banked on some revisions it's not
491	486	* No harm in clearing both banked bits(in fact this is required
492	487	* by an erratum)
...	...	@@ -73,6 +73,7 @@
73	73	void dieid_num_r(void);
74	74	void get_dieid(u32 *id);
75	75	void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
	76	+void omap3_set_aux_cr_secure(u32 acr);
76	77	u32 warm_reset(void);
77	78	#endif
...	...	@@ -341,6 +341,17 @@
341	341	do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
342	342	}
343	343
	344	+void omap3_set_aux_cr_secure(u32 acr)
	345	+{
	346	+ struct emu_hal_params_rx51 emu_romcode_params = { 0, };
	347	+
	348	+ emu_romcode_params.num_params = 2;
	349	+ emu_romcode_params.param1 = acr;
	350	+
	351	+ omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
	352	+ (u32 *)&emu_romcode_params);
	353	+}
	354	+
344	355	/*
345	356	* Routine: omap3_update_aux_cr_secure_rx51
346	357	* Description: Modify the contents Auxiliary Control Register.
347	358
...	...	@@ -350,19 +361,13 @@
350	361	*/
351	362	static void omap3_update_aux_cr_secure_rx51(u32 set_bits, u32 clear_bits)
352	363	{
353		- struct emu_hal_params_rx51 emu_romcode_params = { 0, };
354	364	u32 acr;
355	365
356	366	/* Read ACR */
357	367	asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
358	368	acr &= ~clear_bits;
359	369	acr \|= set_bits;
360		-
361		- emu_romcode_params.num_params = 2;
362		- emu_romcode_params.param1 = acr;
363		-
364		- omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
365		- (u32 *)&emu_romcode_params);
	370	+ omap3_set_aux_cr_secure(acr);
366	371	}
367	372
368	373	/*
...	...	@@ -29,6 +29,10 @@
29	29	#define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */
30	30	#define CONFIG_OMAP_COMMON
31	31	#define CONFIG_SYS_GENERIC_BOARD
	32	+/* Common ARM Erratas */
	33	+#define CONFIG_ARM_ERRATA_454179
	34	+#define CONFIG_ARM_ERRATA_430973
	35	+#define CONFIG_ARM_ERRATA_621766
32	36
33	37	#define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51
34	38