Merge branch 'master' of http://www.denx.de/git/u-boot

Jon Loeliger
2 parents 4d45f69e36 fcfed4f2f2
Showing 16 changed files Side-by-side Diff
CHANGELOG
MAKEALL
Makefile
board/v38b/Makefile
board/v38b/config.mk
board/v38b/ethaddr.c
board/v38b/u-boot.lds
board/v38b/v38b.c
cpu/mpc5xxx/fec.c
cpu/ppc4xx/cpu_init.c
cpu/ppc4xx/start.S
doc/README.nand
include/common.h
include/configs/V38B.h
include/status_led.h
lib_ppc/board.c
@@ -2,6 +2,17 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
  
+* Add (preliminary) support for V38B board
+
+* PPC405EP: Add support for board configuration of CPC0_PCI register
+  This is needed to be able to configure PerWE*/PCI_INT* pin as PerWE*
+  Patch by Tolunay Orkun, 07 Apr 2006
+
+* PPC405EP: Add CFG_GPIO0_OR, CFG_GPIO0_ODR to setup GPIO completely.
+  - Add configuration of Open Drain GPIO Output selection
+  - Add configuration of initial value of GPIO output pins
+  Patch by Tolunay Orkun, 07 Apr 2006
+
 * Fix spelling; minor code cleanup.
  
 * Fix JFFS2 compilation problem
@@ -39,7 +39,7 @@
 	icecube_5100	icecube_5200	lite5200b	mcc200		\
 	o2dnt		pf5200		PM520		TB5200		\
 	Total5100	Total5200	Total5200_Rev2	TQM5200		\
-	TQM5200_B	TQM5200S					\
+	TQM5200_B	TQM5200S	v38b				\
 "
  
 #########################################################################
@@ -403,6 +403,9 @@
 		}
 	@$(MKCONFIG) -a IceCube ppc mpc5xxx icecube
  
+v38b_config: unconfig
+	@./mkconfig -a V38B ppc mpc5xxx v38b
+
 inka4x0_config:	unconfig
 	@$(MKCONFIG) inka4x0 ppc mpc5xxx inka4x0
  
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o ethaddr.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) crv $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+#
+# (C) Copyright 2003-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MarelV38B board
+#
+
+sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
+
+TEXT_BASE = 0xFF000000
+
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
+/*
+ *
+ * (C) Copyright 2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+
+#define GPIO_ENABLE	(MPC5XXX_WU_GPIO)
+
+/* Open Drain Emulation Register */
+#define GPIO_ODR	(MPC5XXX_WU_GPIO + 0x04)
+
+/* Data Direction Register */
+#define GPIO_DDR	(MPC5XXX_WU_GPIO + 0x08)
+
+/* Data Value Out Register */
+#define GPIO_DVOR	(MPC5XXX_WU_GPIO + 0x0C)
+
+/* Interrupt Enable Register */
+#define GPIO_IER	(MPC5XXX_WU_GPIO + 0x10)
+
+/* Individual Interrupt Enable Register */
+#define GPIO_IIER	(MPC5XXX_WU_GPIO + 0x14)
+
+/* Interrupt Type Register */
+#define GPIO_ITR	(MPC5XXX_WU_GPIO + 0x18)
+
+/* Master Enable Register */
+#define GPIO_MER	(MPC5XXX_WU_GPIO + 0x1C)
+
+/* Data Input Value Register */
+#define GPIO_DIVR	(MPC5XXX_WU_GPIO + 0x20)
+
+/* Status Register */
+#define GPIO_SR		(MPC5XXX_WU_GPIO + 0x24)
+
+#define PSC6_0		0x10000000
+#define WKUP_7		0x80000000
+
+/* For NS4 A/B board define WKUP_7, for V38B board PSC_6 */
+#define GPIO_PIN	PSC6_0
+
+#define NO_ERROR	0
+#define ERR_NO_NUMBER	1
+#define ERR_BAD_NUMBER	2
+
+typedef volatile unsigned long GPIO_REG;
+typedef GPIO_REG *GPIO_REG_PTR;
+
+static int is_high(void);
+static int check_device(void);
+static void io_out(int value);
+static void io_input(void);
+static void io_output(void);
+static void init_gpio(void);
+static void read_byte(unsigned char *data);
+static void write_byte(unsigned char command);
+
+void read_2501_memory(unsigned char *psernum, unsigned char *perr);
+void board_get_enetaddr(uchar *enetaddr);
+
+static int is_high()
+{
+	return (* ((vu_long *) GPIO_DIVR) & GPIO_PIN);
+}
+
+static void io_out(int value)
+{
+	if (value)
+		*((vu_long *) GPIO_DVOR) |= GPIO_PIN;
+	else
+		*((vu_long *) GPIO_DVOR) &= ~GPIO_PIN;
+}
+
+static void io_input()
+{
+	*((vu_long *) GPIO_DDR) &= ~GPIO_PIN;
+	udelay(3);	/* allow input to settle */
+}
+
+static void io_output()
+{
+	*((vu_long *) GPIO_DDR) |= GPIO_PIN;
+}
+
+static void init_gpio()
+{
+	*((vu_long *) GPIO_ENABLE) |= GPIO_PIN;	/* Enable appropriate pin */
+}
+
+void read_2501_memory(unsigned char *psernum, unsigned char *perr)
+{
+#define NBYTES 28
+	unsigned char crcval, i;
+	unsigned char buf[NBYTES];
+
+	*perr = 0;
+	crcval = 0;
+
+	for (i=0; i<NBYTES; i++)
+
+
+	if (!check_device())
+		*perr = ERR_NO_NUMBER;
+	else {
+		*perr = NO_ERROR;
+		write_byte(0xCC);		/* skip ROM (0xCC) */
+		write_byte(0xF0);		/* Read memory command 0xF0 */
+		write_byte(0x00);		/* Address TA1=0, TA2=0 */
+		write_byte(0x00);
+		read_byte(&crcval);		/* Read CRC of address and command */
+
+		for (i=0; i<NBYTES; i++)
+			read_byte( &buf[i] );
+	}
+	if (strncmp((const char*) &buf[11], "MAREL IEEE 802.3", 16)) {
+		*perr = ERR_BAD_NUMBER;
+		psernum[0] = 0x00;
+		psernum[1] = 0xE0;
+		psernum[2] = 0xEE;
+		psernum[3] = 0xFF;
+		psernum[4] = 0xFF;
+		psernum[5] = 0xFF;
+	}
+	else {
+		psernum[0] = 0x00;
+		psernum[1] = 0xE0;
+		psernum[2] = 0xEE;
+		psernum[3] = buf[7];
+		psernum[4] = buf[6];
+		psernum[5] = buf[5];
+	}
+}
+
+static int check_device()
+{
+	int found;
+
+	io_output();
+	io_out(0);
+	udelay(500);  /* must be at least 480 us low pulse */
+
+	io_input();
+	udelay(60);
+
+	found = (is_high() == 0) ? 1 : 0;
+	udelay(500);  /* must be at least 480 us low pulse */
+
+	return found;
+}
+
+static void write_byte(unsigned char command)
+{
+	char i;
+
+	for (i=0; i<8; i++) {
+		/* 1 us to 15 us low pulse starts bit slot */
+		/* Start with high pulse for 3 us */
+		io_input();
+
+		udelay(3);
+
+		io_out(0);
+		io_output();
+
+		udelay(3);
+
+		if (command & 0x01) {
+			/* 60 us high for 1-bit */
+			io_input();
+			udelay(60);
+		}
+		else {
+			/* 60 us low for 0-bit */
+			udelay(60);
+		}
+		/*  Leave pin as input */
+		io_input();
+
+		command = command >> 1;
+	}
+}
+
+static void read_byte(unsigned char  *data)
+{
+	unsigned char i, rdat = 0;
+
+	for (i=0; i<8; i++) {
+		/* read one bit from one-wire device */
+
+		/* 1 - 15 us low starts bit slot */
+		io_out(0);
+		io_output();
+		udelay(0);
+
+		/* allow line to be pulled high */
+		io_input();
+
+		/* delay 10 us */
+		udelay(10);
+
+		/* now sample input status */
+		if (is_high())
+			rdat = (rdat >> 1) | 0x80;
+		else
+			rdat = rdat >> 1;
+
+		udelay(60);	/* at least 60 us */
+	}
+	/* copy the return value */
+	*data = rdat;
+}
+
+void board_get_enetaddr(uchar *enetaddr)
+{
+	unsigned char sn[6], err=NO_ERROR;
+
+	init_gpio();
+
+	read_2501_memory(sn, &err);
+
+	if (err == NO_ERROR) {
+		sprintf(enetaddr, "%02x:%02x:%02x:%02x:%02x:%02x",
+				sn[0], sn[1], sn[2], sn[3], sn[4], sn[5]);
+		printf("MAC address: %s\n", enetaddr);
+		setenv("ethaddr", enetaddr);
+	}
+	else {
+		sprintf(enetaddr, "00:01:02:03:04:05");
+		printf("Error reading MAC address.\n");
+		printf("Setting default to %s\n", enetaddr);
+		setenv("ethaddr", enetaddr);
+	}
+}
+/*
+ * (C) Copyright 2003-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text) 	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data) 	}
+  .rel.rodata    : { *(.rel.rodata) 	}
+  .rela.rodata   : { *(.rela.rodata) 	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc5xxx/start.o	(.text)
+    *(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+    *(.rodata.str1.4)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+/*
+ * (C) Copyright 2003-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc5xxx.h>
+#include <asm/processor.h>
+
+#ifndef CFG_RAMBOOT
+static void sdram_start(int hi_addr)
+{
+	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+
+	/* unlock mode register */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set mode register: extended mode */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
+	__asm__ volatile ("sync");
+
+	/* set mode register: reset DLL */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
+	__asm__ volatile ("sync");
+#endif /* SDRAM_DDR */
+
+	/* precharge all banks */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* auto refresh */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
+	__asm__ volatile ("sync");
+
+	/* set mode register */
+	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
+	__asm__ volatile ("sync");
+
+	/* normal operation */
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
+	__asm__ volatile ("sync");
+}
+#endif /* !CFG_RAMBOOT */
+
+
+long int initdram(int board_type)
+{
+	ulong dramsize = 0;
+	ulong dramsize2 = 0;
+	uint svr, pvr;
+
+#ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
+	/* setup SDRAM chip selects */
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;	/* 2G at 0x0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
+	__asm__ volatile ("sync");
+
+	/* setup config registers */
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
+	__asm__ volatile ("sync");
+
+#if SDRAM_DDR
+	/* set tap delay */
+	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
+	__asm__ volatile ("sync");
+#endif /* SDRAM_DDR */
+
+	/* find RAM size using SDRAM CS0 only */
+	sdram_start(0);
+	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	sdram_start(1);
+	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize = test1;
+	} else
+		dramsize = test2;
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize < (1 << 20))
+		dramsize = 0;
+
+	/* set SDRAM CS0 size according to the amount of RAM found */
+	if (dramsize > 0)
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
+	else
+		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+
+	/* let SDRAM CS1 start right after CS0 */
+	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
+
+	/* find RAM size using SDRAM CS1 only */
+	if (!dramsize)
+		sdram_start(0);
+	test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	if (!dramsize) {
+		sdram_start(1);
+		test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	}
+	if (test1 > test2) {
+		sdram_start(0);
+		dramsize2 = test1;
+	} else
+		dramsize2 = test2;
+
+	/* memory smaller than 1MB is impossible */
+	if (dramsize2 < (1 << 20))
+		dramsize2 = 0;
+
+	/* set SDRAM CS1 size according to the amount of RAM found */
+	if (dramsize2 > 0)
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
+			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
+	else
+		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+
+#else /* CFG_RAMBOOT */
+
+	/* retrieve size of memory connected to SDRAM CS0 */
+	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+	if (dramsize >= 0x13)
+		dramsize = (1 << (dramsize - 0x13)) << 20;
+	else
+		dramsize = 0;
+
+	/* retrieve size of memory connected to SDRAM CS1 */
+	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
+	if (dramsize2 >= 0x13)
+		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+	else
+		dramsize2 = 0;
+
+#endif /* CFG_RAMBOOT */
+
+	/*
+	 * On MPC5200B we need to set the special configuration delay in the
+	 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+	 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+	 *
+	 * "The SDelay should be written to a value of 0x00000004. It is
+	 * required to account for changes caused by normal wafer processing
+	 * parameters."
+	 */
+	svr = get_svr();
+	pvr = get_pvr();
+	if ((SVR_MJREV(svr) >= 2) &&
+		(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
+
+		*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
+		__asm__ volatile ("sync");
+	}
+
+	return dramsize + dramsize2;
+}
+
+
+int checkboard (void)
+{
+	puts("Board: MarelV38B\n");
+	return 0;
+}
+
+
+int board_early_init_r(void)
+{
+	/*
+	 * Now, when we are in RAM, enable flash write access for detection process.
+	 * Note that CS_BOOT cannot be cleared when executing in flash.
+	 */
+	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+	return 0;
+}
+
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+
+#define GPIO_PSC1_4	0x01000000UL
+
+void init_ide_reset(void)
+{
+	debug("init_ide_reset\n");
+
+	/* Configure PSC1_4 as GPIO output for ATA reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
+	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
+	/* Deassert reset */
+	*(vu_long *) MPC5XXX_WU_GPIO_DATA   |= GPIO_PSC1_4;
+}
+
+
+void ide_set_reset(int idereset)
+{
+	debug("ide_reset(%d)\n", idereset);
+
+	if (idereset) {
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
+		/* Make a delay. MPC5200 spec says 25 usec min */
+		udelay(500000);
+	} else
+		*(vu_long *) MPC5XXX_WU_GPIO_DATA |=  GPIO_PSC1_4;
+}
+#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
+
+void led_d4_on(void)
+{
+	/* TIMER7 as GPIO output low */
+	*(vu_long *) (MPC5XXX_GPT + 0x70) |= 0x24;
+}
+
+
+void led_d4_off(void)
+{
+	/* TIMER7 as GPIO output high */
+	*(vu_long *) (MPC5XXX_GPT + 0x70) |= 0x34;
+}
+
+
+void hw_watchdog_reset(void)
+{
+/* TODO fill this in */
+}
@@ -882,7 +882,7 @@
     defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0)	|| \
     defined(CONFIG_MCC200)  || defined(CONFIG_O2DNT)	|| \
     defined(CONFIG_PM520)   || defined(CONFIG_TOP5200)	|| \
-    defined(CONFIG_TQM5200)
+    defined(CONFIG_TQM5200) || defined(CONFIG_V38B)
 # ifndef CONFIG_FEC_10MBIT
 	fec->xcv_type = MII100;
 # else
@@ -226,13 +226,19 @@
 	/*
 	 * GPIO0 setup (select GPIO or alternate function)
 	 */
-	out32(GPIO0_OSRH, CFG_GPIO0_OSRH);   /* output select */
+#if defined(CFG_GPIO0_OR)
+	out32(GPIO0_OR, CFG_GPIO0_OR);		/* set initial state of output pins	*/
+#endif
+#if defined(CFG_GPIO0_ODR)
+	out32(GPIO0_ODR, CFG_GPIO0_ODR);	/* open-drain select			*/
+#endif
+	out32(GPIO0_OSRH, CFG_GPIO0_OSRH);	/* output select			*/
 	out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
-	out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
+	out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H);	/* input select				*/
 	out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
-	out32(GPIO0_TSRH, CFG_GPIO0_TSRH);   /* three-state select */
+	out32(GPIO0_TSRH, CFG_GPIO0_TSRH);	/* three-state select			*/
 	out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
-	out32(GPIO0_TCR, CFG_GPIO0_TCR);     /* enable output driver for outputs */
+	out32(GPIO0_TCR, CFG_GPIO0_TCR);	/* enable output driver for outputs	*/
  
 	/*
 	 * Set EMAC noise filter bits
@@ -1697,7 +1697,8 @@
 	mtdcr	ebccfgd,r3
 #endif
  
-	addi	r3,0,CPC0_PCI_HOST_CFG_EN
+#ifndef CFG_CPC0_PCI
+	li	r3,CPC0_PCI_HOST_CFG_EN
 #ifdef CONFIG_BUBINGA
 	/*
 	!-----------------------------------------------------------------------
@@ -1712,6 +1713,9 @@
 	beq	..pci_cfg_set		  /* if not set, then bypass reg write*/
 #endif
 	ori	r3,r3,CPC0_PCI_ARBIT_EN
+#else /* CFG_CPC0_PCI */
+	li	r3,CFG_CPC0_PCI
+#endif /* CFG_CPC0_PCI */
 ..pci_cfg_set:
 	mtdcr	CPC0_PCI, r3		 /* Enable internal arbiter*/
  
 NAND FLASH commands and notes
  
-
 See NOTE below!!!
  
-
 # (C) Copyright 2003
 # Dave Ellis, SIXNET, dge@sixnetio.com
 #
@@ -207,7 +205,6 @@
 The consequence of this is that the legacy NAND can't be removed  from
 the tree until the DoC is ported to use the new NAND support (or boards
 with DoC will break).
-
  
  
 Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006
@@ -320,7 +320,8 @@
  
 #if defined(CONFIG_RPXCLASSIC)	|| defined(CONFIG_MBX) || \
     defined(CONFIG_IAD210)	|| defined(CONFIG_XPEDITE1K) || \
-    defined(CONFIG_METROBOX)    || defined(CONFIG_KAREF)
+    defined(CONFIG_METROBOX)    || defined(CONFIG_KAREF) || \
+    defined(CONFIG_V38B)
 void	board_get_enetaddr (uchar *addr);
 #endif
  
+/*
+ * (C) Copyright 2003-2004 Wolfgang Denk, DENX Software Engineering,
+ * wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc., 59
+ * Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#if 0
+#define DEBUG 0xFFF
+#endif
+
+#if 0
+#define DEBUG 0x01
+#endif
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+*/
+
+#define CONFIG_MPC5xxx			1	/* This is an MPC5xxx CPU	*/
+#define CONFIG_MPC5200			1	/* This is an MPC5200 CPU	*/
+#define CONFIG_V38B			1	/* ... on V38B board		*/
+#define CFG_MPC5XXX_CLKIN	33000000	/* ... running at 33.000000MHz	*/
+
+#define CONFIG_RTC_PCF8563		1	/* has PCF8563 RTC		*/
+#define CONFIG_MPC5200_DDR		1	/* has DDR SDRAM		*/
+#define CONFIG_HW_WATCHDOG		1	/* has watchdog			*/
+
+#define CONFIG_NETCONSOLE		1
+
+#define CONFIG_BOARD_EARLY_INIT_R	1	/* make flash read/write	*/
+
+#define CFG_XLB_PIPELINING		1	/* gives better performance	*/
+
+
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM		0x02	/* Software reboot			*/
+
+#define CFG_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps	*/
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+
+
+/*
+ * DDR
+ */
+#define SDRAM_DDR		1	/* is DDR */
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE		0x018D0000
+#define SDRAM_EMODE		0x40090000
+#define SDRAM_CONTROL		0x704f0f00
+#define SDRAM_CONFIG1		0x73722930
+#define SDRAM_CONFIG2		0x47770000
+#define SDRAM_TAPDELAY		0x10000000
+
+
+/*
+ * PCI - no suport
+ */
+#undef CONFIG_PCI
+
+/*
+ * Partitions
+ */
+#define CONFIG_MAC_PARTITION	1
+#define CONFIG_DOS_PARTITION	1
+
+/*
+ * USB
+ */
+#define CONFIG_USB_OHCI
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_TIMESTAMP		/* Print image info with timestamp */
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
+				 CFG_CMD_FAT	| \
+				 CFG_CMD_I2C	| \
+				 CFG_CMD_IDE	| \
+				 CFG_CMD_PING	| \
+				 CFG_CMD_DHCP	| \
+				 CFG_CMD_DIAG	| \
+				 CFG_CMD_IRQ	| \
+				 CFG_CMD_JFFS2	| \
+				 CFG_CMD_MII	| \
+				 CFG_CMD_SDRAMi | \
+				 CFG_CMD_DATE	| \
+				 CFG_CMD_USB	| \
+				 CFG_CMD_FAT)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Boot low with 16 MB Flash
+ */
+#   define CFG_LOWBOOT		1
+#   define CFG_LOWBOOT16	1
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds */
+
+#define CONFIG_PREBOOT	"echo;" \
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"devno=5\0"							\
+	"hostname=V38B_$(devno)\0"					\
+	"ipaddr=10.100.99.$(devno)\0"					\
+	"netmask=255.255.0.0\0"						\
+	"serverip=10.100.10.90\0"					\
+	"gatewayip=10.100.254.254\0"					\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"rootpath=/opt/eldk/ppc_6xx\0"					\
+	"bootfile=mpc5200/uImage\0"					\
+	"bootcmd=run net_nfs\0"						\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):"		\
+		"$(netmask):$(hostname):$(netdev):off panic=1\0"	\
+	"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0"		\
+	"flash_self=run ramargs addip;bootm $(kernel_addr) "		\
+		"$(ramdisk_addr)\0"					\
+	"net_nfs=tftp 200000 $(bootfile);run nfsargs "			\
+		"addip;bootm\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run net_nfs"
+
+#if defined(CONFIG_MPC5200)
+/*
+ * IPB Bus clocking configuration.
+ */
+#undef CFG_IPBSPEED_133			/* define for 133MHz speed */
+#endif
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
+#define CFG_I2C_MODULE		2	/* Select I2C module #1 or #2 */
+
+#define CFG_I2C_SPEED		100000 /* 100 kHz */
+#define CFG_I2C_SLAVE		0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CFG_I2C_EEPROM_ADDR		0x50	/* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN		1
+#define CFG_EEPROM_PAGE_WRITE_BITS	3
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	70
+
+/*
+ * RTC configuration
+ */
+#define CFG_I2C_RTC_ADDR		0x51
+
+/*
+ * Flash configuration - use CFI driver
+ */
+#define CFG_FLASH_CFI		1		/* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER	1		/* Use the common driver */
+#define CFG_FLASH_CFI_AMD_RESET 1
+#define CFG_FLASH_BASE		0xFF000000
+#define CFG_MAX_FLASH_BANKS	1		/* max num of flash banks */
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#define CFG_FLASH_SIZE		0x01000000	/* 16 MiB */
+#define CFG_MAX_FLASH_SECT	256		/* max num of sects on one chip */
+#define CFG_FLASH_USE_BUFFER_WRITE	1	/* flash write speed-up */
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH	1
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x00040000)
+#define CFG_ENV_SIZE		0x10000
+#define CFG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_OVERWRITE	1
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR		0xF0000000
+#define CFG_SDRAM_BASE		0x00000000
+#define CFG_DEFAULT_MBAR	0x80000000
+
+/* Use SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
+#define CFG_INIT_RAM_END	MPC5XXX_SRAM_SIZE	/* End of used area in DPRAM */
+
+
+#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE    TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#   define CFG_RAMBOOT		1
+#endif
+
+#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC	1
+#define CONFIG_PHY_ADDR		0x00
+#define CONFIG_MII		1
+
+/*
+ * GPIO configuration
+ */
+#define CFG_GPS_PORT_CONFIG	0x90000404
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP			/* undef to save memory	    */
+#define CFG_PROMPT		"=> "	/* Monitor Command Prompt   */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE		1024	/* Console I/O Buffer Size  */
+#else
+#define CFG_CBSIZE		256	/* Console I/O Buffer Size  */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
+#define CFG_MAXARGS		16		/* max number of command args	*/
+#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
+#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+
+#define CFG_LOAD_ADDR		0x100000	/* default load address */
+
+#define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT		HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL		HID0_ICE
+#else
+#define CFG_HID0_INIT		0
+#define CFG_HID0_FINAL		0
+#endif
+
+
+#define CFG_BOOTCS_START	CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE		CFG_FLASH_SIZE
+#define CFG_BOOTCS_CFG		0x00047801
+#define CFG_CS0_START		CFG_FLASH_BASE
+#define CFG_CS0_SIZE		CFG_FLASH_SIZE
+
+#define CFG_CS_BURST		0x00000000
+#define CFG_CS_DEADCYCLE	0x33333333
+
+#define CFG_RESET_ADDRESS	0xff000000
+
+/*-----------------------------------------------------------------------
+ * USB stuff
+ *-----------------------------------------------------------------------
+ */
+#define CONFIG_USB_CLOCK	0x0001BBBB
+#define CONFIG_USB_CONFIG	0x00001000
+
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff Supports IDE harddisk
+ *-----------------------------------------------------------------------
+ */
+
+#undef	CONFIG_IDE_8xx_PCCARD		/* Don't use IDE with PC Card	Adapter */
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/
+#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
+
+#define CONFIG_IDE_RESET		/* reset for ide supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	MPC5XXX_ATA
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(0x0060)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(CFG_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	(0x005C)
+
+/* Interval between registers						     */
+#define CFG_ATA_STRIDE		4
+
+/* Status LED						     */
+
+#define	 CONFIG_STATUS_LED		 /* Status LED enabled		 */
+#define	 CONFIG_BOARD_SPECIFIC_LED	 /* version has board specific leds */
+
+#define CFG_LED_BASE	(0xf0000600 + 0x70)	/* Timer 7 GPIO */
+
+#ifndef __ASSEMBLY__
+/* LEDs */
+typedef unsigned int led_id_t;
+
+#define __led_toggle(_msk) \
+	do { \
+		*((volatile long *) (CFG_LED_BASE)) ^= (_msk); \
+	} while(0)
+
+#define __led_set(_msk, _st) \
+	do { \
+		if ((_st)) \
+			*((volatile long *) (CFG_LED_BASE)) &= ~(_msk); \
+		else \
+			*((volatile long *) (CFG_LED_BASE)) |= (_msk); \
+	} while(0)
+
+#define __led_init(_msk, st) \
+	{ \
+		*((volatile long *) (CFG_LED_BASE)) |= 0x34; \
+	}
+
+#endif
+
+#endif /* __CONFIG_H */
@@ -346,6 +346,15 @@
 #elif defined(CONFIG_NIOS2)
 /* XXX empty just to avoid the error */
 /************************************************************************/
+#elif defined(CONFIG_V38B)
+
+# define STATUS_LED_BIT		0x0010			/* Timer7 GPIO */
+# define STATUS_LED_PERIOD	(CFG_HZ / 2)
+# define STATUS_LED_STATE	STATUS_LED_BLINKING
+
+# define STATUS_LED_ACTIVE	0		/* LED on for bit == 0 */
+# define STATUS_LED_BOOT	0		/* LED 0 used for boot status */
+
 #else
 # error Status LED configuration missing
 #endif
 /*
- * (C) Copyright 2000-2004
+ * (C) Copyright 2000-2006
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -805,7 +805,10 @@
 #endif	/* CFG_EXTBDINFO */
  
 	s = getenv ("ethaddr");
-#if defined (CONFIG_MBX) || defined (CONFIG_RPXCLASSIC) || defined(CONFIG_IAD210)
+#if defined (CONFIG_MBX) || \
+    defined (CONFIG_RPXCLASSIC) || \
+    defined(CONFIG_IAD210) || \
+    defined(CONFIG_V38B)
 	if (s == NULL)
 		board_get_enetaddr (bd->bi_enetaddr);
 	else
...	...	@@ -2,6 +2,17 @@
2	2	Changes since U-Boot 1.1.4:
3	3	======================================================================
4	4
	5	+* Add (preliminary) support for V38B board
	6	+
	7	+* PPC405EP: Add support for board configuration of CPC0_PCI register
	8	+ This is needed to be able to configure PerWE/PCI_INT pin as PerWE*
	9	+ Patch by Tolunay Orkun, 07 Apr 2006
	10	+
	11	+* PPC405EP: Add CFG_GPIO0_OR, CFG_GPIO0_ODR to setup GPIO completely.
	12	+ - Add configuration of Open Drain GPIO Output selection
	13	+ - Add configuration of initial value of GPIO output pins
	14	+ Patch by Tolunay Orkun, 07 Apr 2006
	15	+
5	16	* Fix spelling; minor code cleanup.
6	17
7	18	* Fix JFFS2 compilation problem
...	...	@@ -39,7 +39,7 @@
39	39	icecube_5100 icecube_5200 lite5200b mcc200 \
40	40	o2dnt pf5200 PM520 TB5200 \
41	41	Total5100 Total5200 Total5200_Rev2 TQM5200 \
42		- TQM5200_B TQM5200S \
	42	+ TQM5200_B TQM5200S v38b \
43	43	"
44	44
45	45	#########################################################################
...	...	@@ -403,6 +403,9 @@
403	403	}
404	404	@$(MKCONFIG) -a IceCube ppc mpc5xxx icecube
405	405
	406	+v38b_config: unconfig
	407	+ @./mkconfig -a V38B ppc mpc5xxx v38b
	408	+
406	409	inka4x0_config: unconfig
407	410	@$(MKCONFIG) inka4x0 ppc mpc5xxx inka4x0
408	411
	1	+#
	2	+# (C) Copyright 2003-2006
	3	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+#
	5	+# See file CREDITS for list of people who contributed to this
	6	+# project.
	7	+#
	8	+# This program is free software; you can redistribute it and/or
	9	+# modify it under the terms of the GNU General Public License as
	10	+# published by the Free Software Foundation; either version 2 of
	11	+# the License, or (at your option) any later version.
	12	+#
	13	+# This program is distributed in the hope that it will be useful,
	14	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+# GNU General Public License for more details.
	17	+#
	18	+# You should have received a copy of the GNU General Public License
	19	+# along with this program; if not, write to the Free Software
	20	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+# MA 02111-1307 USA
	22	+#
	23	+
	24	+include $(TOPDIR)/config.mk
	25	+
	26	+LIB = $(obj)lib$(BOARD).a
	27	+
	28	+COBJS := $(BOARD).o ethaddr.o
	29	+
	30	+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
	31	+OBJS := $(addprefix $(obj),$(COBJS))
	32	+SOBJS := $(addprefix $(obj),$(SOBJS))
	33	+
	34	+$(LIB): $(obj).depend $(OBJS)
	35	+ $(AR) crv $@ $(OBJS)
	36	+
	37	+clean:
	38	+ rm -f $(SOBJS) $(OBJS)
	39	+
	40	+distclean: clean
	41	+ rm -f $(LIB) core *.bak .depend
	42	+
	43	+#########################################################################
	44	+
	45	+# defines $(obj).depend target
	46	+include $(SRCTREE)/rules.mk
	47	+
	48	+sinclude $(obj).depend
	49	+
	50	+#########################################################################
	1	+/*
	2	+ *
	3	+ * (C) Copyright 2006
	4	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	5	+ *
	6	+ * See file CREDITS for list of people who contributed to this
	7	+ * project.
	8	+ *
	9	+ * This program is free software; you can redistribute it and/or
	10	+ * modify it under the terms of the GNU General Public License as
	11	+ * published by the Free Software Foundation; either version 2 of
	12	+ * the License, or (at your option) any later version.
	13	+ *
	14	+ * This program is distributed in the hope that it will be useful,
	15	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	+ * GNU General Public License for more details.
	18	+ *
	19	+ * You should have received a copy of the GNU General Public License
	20	+ * along with this program; if not, write to the Free Software
	21	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	+ * MA 02111-1307 USA
	23	+ */
	24	+
	25	+#include <common.h>
	26	+#include <mpc5xxx.h>
	27	+
	28	+#define GPIO_ENABLE (MPC5XXX_WU_GPIO)
	29	+
	30	+/* Open Drain Emulation Register */
	31	+#define GPIO_ODR (MPC5XXX_WU_GPIO + 0x04)
	32	+
	33	+/* Data Direction Register */
	34	+#define GPIO_DDR (MPC5XXX_WU_GPIO + 0x08)
	35	+
	36	+/* Data Value Out Register */
	37	+#define GPIO_DVOR (MPC5XXX_WU_GPIO + 0x0C)
	38	+
	39	+/* Interrupt Enable Register */
	40	+#define GPIO_IER (MPC5XXX_WU_GPIO + 0x10)
	41	+
	42	+/* Individual Interrupt Enable Register */
	43	+#define GPIO_IIER (MPC5XXX_WU_GPIO + 0x14)
	44	+
	45	+/* Interrupt Type Register */
	46	+#define GPIO_ITR (MPC5XXX_WU_GPIO + 0x18)
	47	+
	48	+/* Master Enable Register */
	49	+#define GPIO_MER (MPC5XXX_WU_GPIO + 0x1C)
	50	+
	51	+/* Data Input Value Register */
	52	+#define GPIO_DIVR (MPC5XXX_WU_GPIO + 0x20)
	53	+
	54	+/* Status Register */
	55	+#define GPIO_SR (MPC5XXX_WU_GPIO + 0x24)
	56	+
	57	+#define PSC6_0 0x10000000
	58	+#define WKUP_7 0x80000000
	59	+
	60	+/* For NS4 A/B board define WKUP_7, for V38B board PSC_6 */
	61	+#define GPIO_PIN PSC6_0
	62	+
	63	+#define NO_ERROR 0
	64	+#define ERR_NO_NUMBER 1
	65	+#define ERR_BAD_NUMBER 2
	66	+
	67	+typedef volatile unsigned long GPIO_REG;
	68	+typedef GPIO_REG *GPIO_REG_PTR;
	69	+
	70	+static int is_high(void);
	71	+static int check_device(void);
	72	+static void io_out(int value);
	73	+static void io_input(void);
	74	+static void io_output(void);
	75	+static void init_gpio(void);
	76	+static void read_byte(unsigned char *data);
	77	+static void write_byte(unsigned char command);
	78	+
	79	+void read_2501_memory(unsigned char psernum, unsigned char perr);
	80	+void board_get_enetaddr(uchar *enetaddr);
	81	+
	82	+static int is_high()
	83	+{
	84	+ return (* ((vu_long *) GPIO_DIVR) & GPIO_PIN);
	85	+}
	86	+
	87	+static void io_out(int value)
	88	+{
	89	+ if (value)
	90	+ ((vu_long ) GPIO_DVOR) \|= GPIO_PIN;
	91	+ else
	92	+ ((vu_long ) GPIO_DVOR) &= ~GPIO_PIN;
	93	+}
	94	+
	95	+static void io_input()
	96	+{
	97	+ ((vu_long ) GPIO_DDR) &= ~GPIO_PIN;
	98	+ udelay(3); /* allow input to settle */
	99	+}
	100	+
	101	+static void io_output()
	102	+{
	103	+ ((vu_long ) GPIO_DDR) \|= GPIO_PIN;
	104	+}
	105	+
	106	+static void init_gpio()
	107	+{
	108	+ ((vu_long ) GPIO_ENABLE) \|= GPIO_PIN; /* Enable appropriate pin */
	109	+}
	110	+
	111	+void read_2501_memory(unsigned char psernum, unsigned char perr)
	112	+{
	113	+#define NBYTES 28
	114	+ unsigned char crcval, i;
	115	+ unsigned char buf[NBYTES];
	116	+
	117	+ *perr = 0;
	118	+ crcval = 0;
	119	+
	120	+ for (i=0; i<NBYTES; i++)
	121	+
	122	+
	123	+ if (!check_device())
	124	+ *perr = ERR_NO_NUMBER;
	125	+ else {
	126	+ *perr = NO_ERROR;
	127	+ write_byte(0xCC); /* skip ROM (0xCC) */
	128	+ write_byte(0xF0); /* Read memory command 0xF0 */
	129	+ write_byte(0x00); /* Address TA1=0, TA2=0 */
	130	+ write_byte(0x00);
	131	+ read_byte(&crcval); /* Read CRC of address and command */
	132	+
	133	+ for (i=0; i<NBYTES; i++)
	134	+ read_byte( &buf[i] );
	135	+ }
	136	+ if (strncmp((const char*) &buf[11], "MAREL IEEE 802.3", 16)) {
	137	+ *perr = ERR_BAD_NUMBER;
	138	+ psernum[0] = 0x00;
	139	+ psernum[1] = 0xE0;
	140	+ psernum[2] = 0xEE;
	141	+ psernum[3] = 0xFF;
	142	+ psernum[4] = 0xFF;
	143	+ psernum[5] = 0xFF;
	144	+ }
	145	+ else {
	146	+ psernum[0] = 0x00;
	147	+ psernum[1] = 0xE0;
	148	+ psernum[2] = 0xEE;
	149	+ psernum[3] = buf[7];
	150	+ psernum[4] = buf[6];
	151	+ psernum[5] = buf[5];
	152	+ }
	153	+}
	154	+
	155	+static int check_device()
	156	+{
	157	+ int found;
	158	+
	159	+ io_output();
	160	+ io_out(0);
	161	+ udelay(500); /* must be at least 480 us low pulse */
	162	+
	163	+ io_input();
	164	+ udelay(60);
	165	+
	166	+ found = (is_high() == 0) ? 1 : 0;
	167	+ udelay(500); /* must be at least 480 us low pulse */
	168	+
	169	+ return found;
	170	+}
	171	+
	172	+static void write_byte(unsigned char command)
	173	+{
	174	+ char i;
	175	+
	176	+ for (i=0; i<8; i++) {
	177	+ /* 1 us to 15 us low pulse starts bit slot */
	178	+ /* Start with high pulse for 3 us */
	179	+ io_input();
	180	+
	181	+ udelay(3);
	182	+
	183	+ io_out(0);
	184	+ io_output();
	185	+
	186	+ udelay(3);
	187	+
	188	+ if (command & 0x01) {
	189	+ /* 60 us high for 1-bit */
	190	+ io_input();
	191	+ udelay(60);
	192	+ }
	193	+ else {
	194	+ /* 60 us low for 0-bit */
	195	+ udelay(60);
	196	+ }
	197	+ /* Leave pin as input */
	198	+ io_input();
	199	+
	200	+ command = command >> 1;
	201	+ }
	202	+}
	203	+
	204	+static void read_byte(unsigned char *data)
	205	+{
	206	+ unsigned char i, rdat = 0;
	207	+
	208	+ for (i=0; i<8; i++) {
	209	+ /* read one bit from one-wire device */
	210	+
	211	+ /* 1 - 15 us low starts bit slot */
	212	+ io_out(0);
	213	+ io_output();
	214	+ udelay(0);
	215	+
	216	+ /* allow line to be pulled high */
	217	+ io_input();
	218	+
	219	+ /* delay 10 us */
	220	+ udelay(10);
	221	+
	222	+ /* now sample input status */
	223	+ if (is_high())
	224	+ rdat = (rdat >> 1) \| 0x80;
	225	+ else
	226	+ rdat = rdat >> 1;
	227	+
	228	+ udelay(60); /* at least 60 us */
	229	+ }
	230	+ /* copy the return value */
	231	+ *data = rdat;
	232	+}
	233	+
	234	+void board_get_enetaddr(uchar *enetaddr)
	235	+{
	236	+ unsigned char sn[6], err=NO_ERROR;
	237	+
	238	+ init_gpio();
	239	+
	240	+ read_2501_memory(sn, &err);
	241	+
	242	+ if (err == NO_ERROR) {
	243	+ sprintf(enetaddr, "%02x:%02x:%02x:%02x:%02x:%02x",
	244	+ sn[0], sn[1], sn[2], sn[3], sn[4], sn[5]);
	245	+ printf("MAC address: %s\n", enetaddr);
	246	+ setenv("ethaddr", enetaddr);
	247	+ }
	248	+ else {
	249	+ sprintf(enetaddr, "00:01:02:03:04:05");
	250	+ printf("Error reading MAC address.\n");
	251	+ printf("Setting default to %s\n", enetaddr);
	252	+ setenv("ethaddr", enetaddr);
	253	+ }
	254	+}
	1	+/*
	2	+ * (C) Copyright 2003-2006
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+OUTPUT_ARCH(powerpc)
	25	+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
	26	+/* Do we need any of these for elf?
	27	+ __DYNAMIC = 0; */
	28	+SECTIONS
	29	+{
	30	+ /* Read-only sections, merged into text segment: */
	31	+ . = + SIZEOF_HEADERS;
	32	+ .interp : { *(.interp) }
	33	+ .hash : { *(.hash) }
	34	+ .dynsym : { *(.dynsym) }
	35	+ .dynstr : { *(.dynstr) }
	36	+ .rel.text : { *(.rel.text) }
	37	+ .rela.text : { *(.rela.text) }
	38	+ .rel.data : { *(.rel.data) }
	39	+ .rela.data : { *(.rela.data) }
	40	+ .rel.rodata : { *(.rel.rodata) }
	41	+ .rela.rodata : { *(.rela.rodata) }
	42	+ .rel.got : { *(.rel.got) }
	43	+ .rela.got : { *(.rela.got) }
	44	+ .rel.ctors : { *(.rel.ctors) }
	45	+ .rela.ctors : { *(.rela.ctors) }
	46	+ .rel.dtors : { *(.rel.dtors) }
	47	+ .rela.dtors : { *(.rela.dtors) }
	48	+ .rel.bss : { *(.rel.bss) }
	49	+ .rela.bss : { *(.rela.bss) }
	50	+ .rel.plt : { *(.rel.plt) }
	51	+ .rela.plt : { *(.rela.plt) }
	52	+ .init : { *(.init) }
	53	+ .plt : { *(.plt) }
	54	+ .text :
	55	+ {
	56	+ cpu/mpc5xxx/start.o (.text)
	57	+ *(.text)
	58	+ *(.fixup)
	59	+ *(.got1)
	60	+ . = ALIGN(16);
	61	+ *(.rodata)
	62	+ *(.rodata1)
	63	+ *(.rodata.str1.4)
	64	+ }
	65	+ .fini : { *(.fini) } =0
	66	+ .ctors : { *(.ctors) }
	67	+ .dtors : { *(.dtors) }
	68	+
	69	+ /* Read-write section, merged into data segment: */
	70	+ . = (. + 0x0FFF) & 0xFFFFF000;
	71	+ _erotext = .;
	72	+ PROVIDE (erotext = .);
	73	+ .reloc :
	74	+ {
	75	+ *(.got)
	76	+ _GOT2_TABLE_ = .;
	77	+ *(.got2)
	78	+ _FIXUP_TABLE_ = .;
	79	+ *(.fixup)
	80	+ }
	81	+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
	82	+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
	83	+
	84	+ .data :
	85	+ {
	86	+ *(.data)
	87	+ *(.data1)
	88	+ *(.sdata)
	89	+ *(.sdata2)
	90	+ *(.dynamic)
	91	+ CONSTRUCTORS
	92	+ }
	93	+ _edata = .;
	94	+ PROVIDE (edata = .);
	95	+
	96	+ __u_boot_cmd_start = .;
	97	+ .u_boot_cmd : { *(.u_boot_cmd) }
	98	+ __u_boot_cmd_end = .;
	99	+
	100	+
	101	+ __start___ex_table = .;
	102	+ __ex_table : { *(__ex_table) }
	103	+ __stop___ex_table = .;
	104	+
	105	+ . = ALIGN(4096);
	106	+ __init_begin = .;
	107	+ .text.init : { *(.text.init) }
	108	+ .data.init : { *(.data.init) }
	109	+ . = ALIGN(4096);
	110	+ __init_end = .;
	111	+
	112	+ __bss_start = .;
	113	+ .bss :
	114	+ {
	115	+ (.sbss) (.scommon)
	116	+ *(.dynbss)
	117	+ *(.bss)
	118	+ *(COMMON)
	119	+ }
	120	+ _end = . ;
	121	+ PROVIDE (end = .);
	122	+}
	1	+/*
	2	+ * (C) Copyright 2003-2006
	3	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+ *
	5	+ * (C) Copyright 2004
	6	+ * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
	7	+ *
	8	+ * See file CREDITS for list of people who contributed to this
	9	+ * project.
	10	+ *
	11	+ * This program is free software; you can redistribute it and/or
	12	+ * modify it under the terms of the GNU General Public License as
	13	+ * published by the Free Software Foundation; either version 2 of
	14	+ * the License, or (at your option) any later version.
	15	+ *
	16	+ * This program is distributed in the hope that it will be useful,
	17	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	+ * GNU General Public License for more details.
	20	+ *
	21	+ * You should have received a copy of the GNU General Public License
	22	+ * along with this program; if not, write to the Free Software
	23	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	+ * MA 02111-1307 USA
	25	+ */
	26	+
	27	+#include <common.h>
	28	+#include <mpc5xxx.h>
	29	+#include <asm/processor.h>
	30	+
	31	+#ifndef CFG_RAMBOOT
	32	+static void sdram_start(int hi_addr)
	33	+{
	34	+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
	35	+
	36	+ /* unlock mode register */
	37	+ (vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit;
	38	+ __asm__ volatile ("sync");
	39	+
	40	+ /* precharge all banks */
	41	+ (vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
	42	+ __asm__ volatile ("sync");
	43	+
	44	+#if SDRAM_DDR
	45	+ /* set mode register: extended mode */
	46	+ (vu_long )MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	47	+ __asm__ volatile ("sync");
	48	+
	49	+ /* set mode register: reset DLL */
	50	+ (vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE \| 0x04000000;
	51	+ __asm__ volatile ("sync");
	52	+#endif /* SDRAM_DDR */
	53	+
	54	+ /* precharge all banks */
	55	+ (vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
	56	+ __asm__ volatile ("sync");
	57	+
	58	+ /* auto refresh */
	59	+ (vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit;
	60	+ __asm__ volatile ("sync");
	61	+
	62	+ /* set mode register */
	63	+ (vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	64	+ __asm__ volatile ("sync");
	65	+
	66	+ /* normal operation */
	67	+ (vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| hi_addr_bit;
	68	+ __asm__ volatile ("sync");
	69	+}
	70	+#endif /* !CFG_RAMBOOT */
	71	+
	72	+
	73	+long int initdram(int board_type)
	74	+{
	75	+ ulong dramsize = 0;
	76	+ ulong dramsize2 = 0;
	77	+ uint svr, pvr;
	78	+
	79	+#ifndef CFG_RAMBOOT
	80	+ ulong test1, test2;
	81	+
	82	+ /* setup SDRAM chip selects */
	83	+ (vu_long )MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
	84	+ (vu_long )MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
	85	+ __asm__ volatile ("sync");
	86	+
	87	+ /* setup config registers */
	88	+ (vu_long )MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	89	+ (vu_long )MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	90	+ __asm__ volatile ("sync");
	91	+
	92	+#if SDRAM_DDR
	93	+ /* set tap delay */
	94	+ (vu_long )MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	95	+ __asm__ volatile ("sync");
	96	+#endif /* SDRAM_DDR */
	97	+
	98	+ /* find RAM size using SDRAM CS0 only */
	99	+ sdram_start(0);
	100	+ test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
	101	+ sdram_start(1);
	102	+ test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
	103	+ if (test1 > test2) {
	104	+ sdram_start(0);
	105	+ dramsize = test1;
	106	+ } else
	107	+ dramsize = test2;
	108	+
	109	+ /* memory smaller than 1MB is impossible */
	110	+ if (dramsize < (1 << 20))
	111	+ dramsize = 0;
	112	+
	113	+ /* set SDRAM CS0 size according to the amount of RAM found */
	114	+ if (dramsize > 0)
	115	+ (vu_long )MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
	116	+ else
	117	+ (vu_long )MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	118	+
	119	+ /* let SDRAM CS1 start right after CS0 */
	120	+ (vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
	121	+
	122	+ /* find RAM size using SDRAM CS1 only */
	123	+ if (!dramsize)
	124	+ sdram_start(0);
	125	+ test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
	126	+ if (!dramsize) {
	127	+ sdram_start(1);
	128	+ test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
	129	+ }
	130	+ if (test1 > test2) {
	131	+ sdram_start(0);
	132	+ dramsize2 = test1;
	133	+ } else
	134	+ dramsize2 = test2;
	135	+
	136	+ /* memory smaller than 1MB is impossible */
	137	+ if (dramsize2 < (1 << 20))
	138	+ dramsize2 = 0;
	139	+
	140	+ /* set SDRAM CS1 size according to the amount of RAM found */
	141	+ if (dramsize2 > 0)
	142	+ (vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize
	143	+ \| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
	144	+ else
	145	+ (vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
	146	+
	147	+#else /* CFG_RAMBOOT */
	148	+
	149	+ /* retrieve size of memory connected to SDRAM CS0 */
	150	+ dramsize = (vu_long )MPC5XXX_SDRAM_CS0CFG & 0xFF;
	151	+ if (dramsize >= 0x13)
	152	+ dramsize = (1 << (dramsize - 0x13)) << 20;
	153	+ else
	154	+ dramsize = 0;
	155	+
	156	+ /* retrieve size of memory connected to SDRAM CS1 */
	157	+ dramsize2 = (vu_long )MPC5XXX_SDRAM_CS1CFG & 0xFF;
	158	+ if (dramsize2 >= 0x13)
	159	+ dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	160	+ else
	161	+ dramsize2 = 0;
	162	+
	163	+#endif /* CFG_RAMBOOT */
	164	+
	165	+ /*
	166	+ * On MPC5200B we need to set the special configuration delay in the
	167	+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
	168	+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
	169	+ *
	170	+ * "The SDelay should be written to a value of 0x00000004. It is
	171	+ * required to account for changes caused by normal wafer processing
	172	+ * parameters."
	173	+ */
	174	+ svr = get_svr();
	175	+ pvr = get_pvr();
	176	+ if ((SVR_MJREV(svr) >= 2) &&
	177	+ (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
	178	+
	179	+ (vu_long )MPC5XXX_SDRAM_SDELAY = 0x04;
	180	+ __asm__ volatile ("sync");
	181	+ }
	182	+
	183	+ return dramsize + dramsize2;
	184	+}
	185	+
	186	+
	187	+int checkboard (void)
	188	+{
	189	+ puts("Board: MarelV38B\n");
	190	+ return 0;
	191	+}
	192	+
	193	+
	194	+int board_early_init_r(void)
	195	+{
	196	+ /*
	197	+ * Now, when we are in RAM, enable flash write access for detection process.
	198	+ * Note that CS_BOOT cannot be cleared when executing in flash.
	199	+ */
	200	+ (vu_long )MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
	201	+ return 0;
	202	+}
	203	+
	204	+
	205	+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
	206	+
	207	+#define GPIO_PSC1_4 0x01000000UL
	208	+
	209	+void init_ide_reset(void)
	210	+{
	211	+ debug("init_ide_reset\n");
	212	+
	213	+ /* Configure PSC1_4 as GPIO output for ATA reset */
	214	+ (vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_PSC1_4;
	215	+ (vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_PSC1_4;
	216	+ /* Deassert reset */
	217	+ (vu_long ) MPC5XXX_WU_GPIO_DATA \|= GPIO_PSC1_4;
	218	+}
	219	+
	220	+
	221	+void ide_set_reset(int idereset)
	222	+{
	223	+ debug("ide_reset(%d)\n", idereset);
	224	+
	225	+ if (idereset) {
	226	+ (vu_long ) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
	227	+ /* Make a delay. MPC5200 spec says 25 usec min */
	228	+ udelay(500000);
	229	+ } else
	230	+ (vu_long ) MPC5XXX_WU_GPIO_DATA \|= GPIO_PSC1_4;
	231	+}
	232	+#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
	233	+
	234	+
	235	+void led_d4_on(void)
	236	+{
	237	+ /* TIMER7 as GPIO output low */
	238	+ (vu_long ) (MPC5XXX_GPT + 0x70) \|= 0x24;
	239	+}
	240	+
	241	+
	242	+void led_d4_off(void)
	243	+{
	244	+ /* TIMER7 as GPIO output high */
	245	+ (vu_long ) (MPC5XXX_GPT + 0x70) \|= 0x34;
	246	+}
	247	+
	248	+
	249	+void hw_watchdog_reset(void)
	250	+{
	251	+/* TODO fill this in */
	252	+}
...	...	@@ -882,7 +882,7 @@
882	882	defined(CONFIG_ICECUBE) \|\| defined(CONFIG_INKA4X0) \|\| \
883	883	defined(CONFIG_MCC200) \|\| defined(CONFIG_O2DNT) \|\| \
884	884	defined(CONFIG_PM520) \|\| defined(CONFIG_TOP5200) \|\| \
885		- defined(CONFIG_TQM5200)
	885	+ defined(CONFIG_TQM5200) \|\| defined(CONFIG_V38B)
886	886	# ifndef CONFIG_FEC_10MBIT
887	887	fec->xcv_type = MII100;
888	888	# else
...	...	@@ -226,13 +226,19 @@
226	226	/*
227	227	* GPIO0 setup (select GPIO or alternate function)
228	228	*/
229		- out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
	229	+#if defined(CFG_GPIO0_OR)
	230	+ out32(GPIO0_OR, CFG_GPIO0_OR); /* set initial state of output pins */
	231	+#endif
	232	+#if defined(CFG_GPIO0_ODR)
	233	+ out32(GPIO0_ODR, CFG_GPIO0_ODR); /* open-drain select */
	234	+#endif
	235	+ out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
230	236	out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
231		- out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
	237	+ out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
232	238	out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
233		- out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
	239	+ out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
234	240	out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
235		- out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
	241	+ out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
236	242
237	243	/*
238	244	* Set EMAC noise filter bits
...	...	@@ -1697,7 +1697,8 @@
1697	1697	mtdcr ebccfgd,r3
1698	1698	#endif
1699	1699
1700		- addi r3,0,CPC0_PCI_HOST_CFG_EN
	1700	+#ifndef CFG_CPC0_PCI
	1701	+ li r3,CPC0_PCI_HOST_CFG_EN
1701	1702	#ifdef CONFIG_BUBINGA
1702	1703	/*
1703	1704	!-----------------------------------------------------------------------
...	...	@@ -1712,6 +1713,9 @@
1712	1713	beq ..pci_cfg_set /* if not set, then bypass reg write*/
1713	1714	#endif
1714	1715	ori r3,r3,CPC0_PCI_ARBIT_EN
	1716	+#else /* CFG_CPC0_PCI */
	1717	+ li r3,CFG_CPC0_PCI
	1718	+#endif /* CFG_CPC0_PCI */
1715	1719	..pci_cfg_set:
1716	1720	mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/
1717	1721