Eric Lee / smarc-uboot

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Commit d81572c272d4b0980fb9b8a02e1357090b002398

Authored by Tom Rini
2 parents 1131d4e22c 8b0044ff59
Exists in v2017.01-smarct4x and in 34 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Merge git://git.denx.de/u-boot-mpc85xx

Showing 89 changed files Side-by-side Diff

arch/powerpc/cpu/mpc512x/Makefile
Diff comments   View file @ d81572c
... ... @@ -17,7 +17,4 @@
17 17 obj-$(CONFIG_FSL_DIU_FB) += diu.o
18 18 obj-$(CONFIG_CMD_IDE) += ide.o
19 19 obj-$(CONFIG_PCI) += pci.o
20   -
21   -# Stub implementations of cache management functions for USB
22   -obj-$(CONFIG_USB_EHCI) += cache.o
arch/powerpc/cpu/mpc512x/cache.c
View file @ d81572c
1   -/*
2   - * Copyright (C) 2012 Marek Vasut <marex@denx.de>
3   - *
4   - * This file contains stub implementation of
5   - * invalidate_dcache_range()
6   - * flush_dcache_range()
7   - *
8   - * SPDX-License-Identifier: GPL-2.0+
9   - */
10   -
11   -void invalidate_dcache_range(unsigned long start, unsigned long stop)
12   -{
13   -}
14   -
15   -void flush_dcache_range(unsigned long start, unsigned long stop)
16   -{
17   -}
arch/powerpc/cpu/mpc5xxx/Makefile
Diff comments   View file @ d81572c
... ... @@ -7,7 +7,6 @@
7 7  
8 8 extra-y = start.o
9 9 extra-y += traps.o
10   -obj-y += cache.o
11 10 obj-y += io.o
12 11 obj-y += firmware_sc_task_bestcomm.impl.o
13 12 obj-y += i2c.o
arch/powerpc/cpu/mpc5xxx/cache.c
View file @ d81572c
1   -/*
2   - * This file contains stub implementation of
3   - * invalidate_dcache_range()
4   - * flush_dcache_range()
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -void invalidate_dcache_range(unsigned long start, unsigned long stop)
10   -{
11   -}
12   -
13   -void flush_dcache_range(unsigned long start, unsigned long stop)
14   -{
15   -}
arch/powerpc/cpu/mpc83xx/Makefile
Diff comments   View file @ d81572c
... ... @@ -35,9 +35,6 @@
35 35 obj-$(CONFIG_PCIE) += pcie.o
36 36 obj-$(CONFIG_OF_LIBFDT) += fdt.o
37 37  
38   -# Stub implementations of cache management functions for USB
39   -obj-y += cache.o
40   -
41 38 ifndef CONFIG_SYS_FSL_DDRC_GEN2
42 39 obj-y += spd_sdram.o
43 40 endif
arch/powerpc/cpu/mpc83xx/cache.c
View file @ d81572c
1   -/*
2   - * Copyright (C) 2012 Marek Vasut <marex@denx.de>
3   - *
4   - * This file contains stub implementation of
5   - * invalidate_dcache_range()
6   - * flush_dcache_range()
7   - *
8   - * SPDX-License-Identifier: GPL-2.0+
9   - */
10   -
11   -void invalidate_dcache_range(unsigned long start, unsigned long stop)
12   -{
13   -}
14   -
15   -void flush_dcache_range(unsigned long start, unsigned long stop)
16   -{
17   -}
arch/powerpc/cpu/mpc85xx/Kconfig
Diff comments   View file @ d81572c
... ... @@ -122,15 +122,13 @@
122 122 bool "Support T208xRDB"
123 123 select SUPPORT_SPL
124 124  
125   -config TARGET_T4240EMU
126   - bool "Support T4240EMU"
127   -
128 125 config TARGET_T4240QDS
129 126 bool "Support T4240QDS"
130 127 select SUPPORT_SPL
131 128  
132 129 config TARGET_T4240RDB
133 130 bool "Support T4240RDB"
  131 + select SUPPORT_SPL
134 132  
135 133 config TARGET_CONTROLCENTERD
136 134 bool "Support controlcenterd"
... ... @@ -153,6 +151,9 @@
153 151 config TARGET_XPEDITE550X
154 152 bool "Support xpedite550x"
155 153  
  154 +config TARGET_UCP1020
  155 + bool "Support uCP1020"
  156 +
156 157 endchoice
157 158  
158 159 source "board/freescale/b4860qds/Kconfig"
... ... @@ -194,6 +195,7 @@
194 195 source "board/xes/xpedite520x/Kconfig"
195 196 source "board/xes/xpedite537x/Kconfig"
196 197 source "board/xes/xpedite550x/Kconfig"
  198 +source "board/Arcturus/ucp1020/Kconfig"
197 199  
198 200 endmenu
arch/powerpc/cpu/mpc85xx/Makefile
Diff comments   View file @ d81572c
... ... @@ -114,8 +114,5 @@
114 114 obj-y += tlb.o
115 115 obj-y += traps.o
116 116  
117   -# Stub implementations of cache management functions for USB
118   -obj-y += cache.o
119   -
120 117 endif # not minimal
arch/powerpc/cpu/mpc85xx/cache.c
View file @ d81572c
1   -/*
2   - * Copyright (C) 2012 Marek Vasut <marex@denx.de>
3   - *
4   - * This file contains stub implementation of
5   - * invalidate_dcache_range()
6   - * flush_dcache_range()
7   - *
8   - * SPDX-License-Identifier: GPL-2.0+
9   - */
10   -
11   -void invalidate_dcache_range(unsigned long start, unsigned long stop)
12   -{
13   -}
14   -
15   -void flush_dcache_range(unsigned long start, unsigned long stop)
16   -{
17   -}
arch/powerpc/cpu/mpc85xx/cmd_errata.c
Diff comments   View file @ d81572c
... ... @@ -299,6 +299,10 @@
299 299 if (has_erratum_a007798())
300 300 puts("Work-around for Erratum A007798 enabled\n");
301 301 #endif
  302 +#ifdef CONFIG_SYS_FSL_ERRATUM_A004477
  303 + if (has_erratum_a004477())
  304 + puts("Work-around for Erratum A004477 enabled\n");
  305 +#endif
302 306 #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
303 307 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
304 308 (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
arch/powerpc/cpu/mpc85xx/portals.c
Diff comments   View file @ d81572c
... ... @@ -249,8 +249,13 @@
249 249 #ifdef CONFIG_FSL_CORENET
250 250 u32 liodns[2];
251 251 #endif
252   - const int *ci = fdt_getprop(blob, off, "cell-index", NULL);
253   - int i = *ci;
  252 + const int *ci = fdt_getprop(blob, off, "cell-index", &err);
  253 + int i;
  254 +
  255 + if (!ci)
  256 + goto err;
  257 +
  258 + i = *ci;
254 259 #ifdef CONFIG_SYS_DPAA_FMAN
255 260 int j;
256 261 #endif
arch/powerpc/cpu/mpc85xx/speed.c
Diff comments   View file @ d81572c
... ... @@ -73,7 +73,8 @@
73 73 [14] = 4, /* CC4 PPL / 4 */
74 74 };
75 75 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
76   -#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
  76 +#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV) || \
  77 + defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
77 78 uint rcw_tmp;
78 79 #endif
79 80 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
... ... @@ -453,6 +454,48 @@
453 454 #endif
454 455 #endif
455 456  
  457 +#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
  458 +#if defined(CONFIG_PPC_T2080)
  459 +#define ESDHC_CLK_SEL 0x00000007
  460 +#define ESDHC_CLK_SHIFT 0
  461 +#define ESDHC_CLK_RCWSR 15
  462 +#else /* Support T1040 T1024 by now */
  463 +#define ESDHC_CLK_SEL 0xe0000000
  464 +#define ESDHC_CLK_SHIFT 29
  465 +#define ESDHC_CLK_RCWSR 7
  466 +#endif
  467 + rcw_tmp = in_be32(&gur->rcwsr[ESDHC_CLK_RCWSR]);
  468 + switch ((rcw_tmp & ESDHC_CLK_SEL) >> ESDHC_CLK_SHIFT) {
  469 + case 1:
  470 + sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK];
  471 + break;
  472 + case 2:
  473 + sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 2;
  474 + break;
  475 + case 3:
  476 + sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 3;
  477 + break;
  478 +#if defined(CONFIG_SYS_SDHC_CLK_2_PLL)
  479 + case 4:
  480 + sys_info->freq_sdhc = freq_c_pll[CONFIG_SYS_SDHC_CLK] / 4;
  481 + break;
  482 +#if defined(CONFIG_PPC_T2080)
  483 + case 5:
  484 + sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK];
  485 + break;
  486 +#endif
  487 + case 6:
  488 + sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 2;
  489 + break;
  490 + case 7:
  491 + sys_info->freq_sdhc = freq_c_pll[1 - CONFIG_SYS_SDHC_CLK] / 3;
  492 + break;
  493 +#endif
  494 + default:
  495 + sys_info->freq_sdhc = 0;
  496 + printf("Error: Unknown SDHC peripheral clock select!\n");
  497 + }
  498 +#endif
456 499 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
457 500  
458 501 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
459 502  
... ... @@ -660,11 +703,15 @@
660 703 gd->arch.i2c2_clk = gd->arch.i2c1_clk;
661 704  
662 705 #if defined(CONFIG_FSL_ESDHC)
  706 +#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
  707 + gd->arch.sdhc_clk = sys_info.freq_sdhc / 2;
  708 +#else
663 709 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
664 710 defined(CONFIG_P1014)
665 711 gd->arch.sdhc_clk = gd->bus_clk;
666 712 #else
667 713 gd->arch.sdhc_clk = gd->bus_clk / 2;
  714 +#endif
668 715 #endif
669 716 #endif /* defined(CONFIG_FSL_ESDHC) */
670 717  
arch/powerpc/cpu/mpc85xx/start.S
Diff comments   View file @ d81572c
... ... @@ -1664,41 +1664,46 @@
1664 1664 */
1665 1665 .globl trap_init
1666 1666 trap_init:
  1667 + mflr r11
  1668 + bl _GLOBAL_OFFSET_TABLE_-4
  1669 + mflr r12
  1670 +
1667 1671 /* Update IVORs as per relocation */
1668 1672 mtspr IVPR,r3
1669 1673  
1670   - li r4,CriticalInput@l
  1674 + lwz r4,CriticalInput@got(r12)
1671 1675 mtspr IVOR0,r4 /* 0: Critical input */
1672   - li r4,MachineCheck@l
  1676 + lwz r4,MachineCheck@got(r12)
1673 1677 mtspr IVOR1,r4 /* 1: Machine check */
1674   - li r4,DataStorage@l
  1678 + lwz r4,DataStorage@got(r12)
1675 1679 mtspr IVOR2,r4 /* 2: Data storage */
1676   - li r4,InstStorage@l
  1680 + lwz r4,InstStorage@got(r12)
1677 1681 mtspr IVOR3,r4 /* 3: Instruction storage */
1678   - li r4,ExtInterrupt@l
  1682 + lwz r4,ExtInterrupt@got(r12)
1679 1683 mtspr IVOR4,r4 /* 4: External interrupt */
1680   - li r4,Alignment@l
  1684 + lwz r4,Alignment@got(r12)
1681 1685 mtspr IVOR5,r4 /* 5: Alignment */
1682   - li r4,ProgramCheck@l
  1686 + lwz r4,ProgramCheck@got(r12)
1683 1687 mtspr IVOR6,r4 /* 6: Program check */
1684   - li r4,FPUnavailable@l
  1688 + lwz r4,FPUnavailable@got(r12)
1685 1689 mtspr IVOR7,r4 /* 7: floating point unavailable */
1686   - li r4,SystemCall@l
  1690 + lwz r4,SystemCall@got(r12)
1687 1691 mtspr IVOR8,r4 /* 8: System call */
1688 1692 /* 9: Auxiliary processor unavailable(unsupported) */
1689   - li r4,Decrementer@l
  1693 + lwz r4,Decrementer@got(r12)
1690 1694 mtspr IVOR10,r4 /* 10: Decrementer */
1691   - li r4,IntervalTimer@l
  1695 + lwz r4,IntervalTimer@got(r12)
1692 1696 mtspr IVOR11,r4 /* 11: Interval timer */
1693   - li r4,WatchdogTimer@l
  1697 + lwz r4,WatchdogTimer@got(r12)
1694 1698 mtspr IVOR12,r4 /* 12: Watchdog timer */
1695   - li r4,DataTLBError@l
  1699 + lwz r4,DataTLBError@got(r12)
1696 1700 mtspr IVOR13,r4 /* 13: Data TLB error */
1697   - li r4,InstructionTLBError@l
  1701 + lwz r4,InstructionTLBError@got(r12)
1698 1702 mtspr IVOR14,r4 /* 14: Instruction TLB error */
1699   - li r4,DebugBreakpoint@l
  1703 + lwz r4,DebugBreakpoint@got(r12)
1700 1704 mtspr IVOR15,r4 /* 15: Debug */
1701 1705  
  1706 + mtlr r11
1702 1707 blr
1703 1708  
1704 1709 .globl unlock_ram_in_cache
arch/powerpc/cpu/mpc86xx/cache.S
Diff comments   View file @ d81572c
... ... @@ -115,51 +115,6 @@
115 115 blr
116 116  
117 117 /*
118   - * Write any modified data cache blocks out to memory
119   - * and invalidate the corresponding instruction cache blocks.
120   - *
121   - * flush_dcache_range(unsigned long start, unsigned long stop)
122   - */
123   -_GLOBAL(flush_dcache_range)
124   - li r5,CACHE_LINE_SIZE-1
125   - andc r3,r3,r5
126   - subf r4,r3,r4
127   - add r4,r4,r5
128   - srwi. r4,r4,LG_CACHE_LINE_SIZE
129   - beqlr
130   - mtctr r4
131   -
132   - sync
133   -1: dcbf 0,r3
134   - addi r3,r3,CACHE_LINE_SIZE
135   - bdnz 1b
136   - sync /* wait for dcbf's to get to ram */
137   - blr
138   -
139   -/*
140   - * Like above, but invalidate the D-cache. This is used by the 8xx
141   - * to invalidate the cache so the PPC core doesn't get stale data
142   - * from the CPM (no cache snooping here :-).
143   - *
144   - * invalidate_dcache_range(unsigned long start, unsigned long stop)
145   - */
146   -_GLOBAL(invalidate_dcache_range)
147   - li r5,CACHE_LINE_SIZE-1
148   - andc r3,r3,r5
149   - subf r4,r3,r4
150   - add r4,r4,r5
151   - srwi. r4,r4,LG_CACHE_LINE_SIZE
152   - beqlr
153   - mtctr r4
154   -
155   - sync
156   -1: dcbi 0,r3
157   - addi r3,r3,CACHE_LINE_SIZE
158   - bdnz 1b
159   - sync /* wait for dcbi's to get to ram */
160   - blr
161   -
162   -/*
163 118 * Flush a particular page from the data cache to RAM.
164 119 * Note: this is necessary because the instruction cache does *not*
165 120 * snoop from the data cache.
arch/powerpc/cpu/ppc4xx/cache.S
Diff comments   View file @ d81572c
... ... @@ -74,49 +74,6 @@
74 74 blr
75 75  
76 76 /*
77   - * Write any modified data cache blocks out to memory and invalidate them.
78   - * Does not invalidate the corresponding instruction cache blocks.
79   - *
80   - * flush_dcache_range(unsigned long start, unsigned long stop)
81   - */
82   -_GLOBAL(flush_dcache_range)
83   - li r5,L1_CACHE_BYTES-1
84   - andc r3,r3,r5
85   - subf r4,r3,r4
86   - add r4,r4,r5
87   - srwi. r4,r4,L1_CACHE_SHIFT
88   - beqlr
89   - mtctr r4
90   -
91   -1: dcbf 0,r3
92   - addi r3,r3,L1_CACHE_BYTES
93   - bdnz 1b
94   - sync /* wait for dcbst's to get to ram */
95   - blr
96   -
97   -/*
98   - * Like above, but invalidate the D-cache. This is used by the 8xx
99   - * to invalidate the cache so the PPC core doesn't get stale data
100   - * from the CPM (no cache snooping here :-).
101   - *
102   - * invalidate_dcache_range(unsigned long start, unsigned long stop)
103   - */
104   -_GLOBAL(invalidate_dcache_range)
105   - li r5,L1_CACHE_BYTES-1
106   - andc r3,r3,r5
107   - subf r4,r3,r4
108   - add r4,r4,r5
109   - srwi. r4,r4,L1_CACHE_SHIFT
110   - beqlr
111   - mtctr r4
112   -
113   -1: dcbi 0,r3
114   - addi r3,r3,L1_CACHE_BYTES
115   - bdnz 1b
116   - sync /* wait for dcbi's to get to ram */
117   - blr
118   -
119   -/*
120 77 * 40x cores have 8K or 16K dcache and 32 byte line size.
121 78 * 44x has a 32K dcache and 32 byte line size.
122 79 * 8xx has 1, 2, 4, 8K variants.
arch/powerpc/include/asm/arch-mpc85xx/gpio.h
Diff comments   View file @ d81572c
... ... @@ -12,5 +12,7 @@
12 12 #ifndef __ASM_ARCH_MX85XX_GPIO_H
13 13 #define __ASM_ARCH_MX85XX_GPIO_H
14 14  
  15 +#include <asm/mpc85xx_gpio.h>
  16 +
15 17 #endif
arch/powerpc/include/asm/config_mpc85xx.h
Diff comments   View file @ d81572c
... ... @@ -163,6 +163,7 @@
163 163 #define CONFIG_SYS_FSL_ERRATUM_A004508
164 164 #define CONFIG_SYS_FSL_ERRATUM_A007075
165 165 #define CONFIG_SYS_FSL_ERRATUM_A006261
  166 +#define CONFIG_SYS_FSL_ERRATUM_A004477
166 167 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
167 168 #define CONFIG_ESDHC_HC_BLK_ADDR
168 169  
... ... @@ -294,6 +295,7 @@
294 295 #define CONFIG_FSL_SATA_ERRATUM_A001
295 296 #define CONFIG_SYS_FSL_ERRATUM_A004508
296 297 #define CONFIG_SYS_FSL_ERRATUM_A005125
  298 +#define CONFIG_SYS_FSL_ERRATUM_A004477
297 299  
298 300 #elif defined(CONFIG_P1023)
299 301 #define CONFIG_MAX_CPUS 2
... ... @@ -374,6 +376,7 @@
374 376 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
375 377 #define CONFIG_SYS_FSL_ERRATUM_A004508
376 378 #define CONFIG_SYS_FSL_ERRATUM_A005125
  379 +#define CONFIG_SYS_FSL_ERRATUM_A004477
377 380 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
378 381  
379 382 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
... ... @@ -591,6 +594,7 @@
591 594 #define CONFIG_NAND_FSL_IFC
592 595 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
593 596 #define CONFIG_SYS_FSL_ERRATUM_A005125
  597 +#define CONFIG_SYS_FSL_ERRATUM_A004477
594 598 #define CONFIG_ESDHC_HC_BLK_ADDR
595 599  
596 600 #elif defined(CONFIG_BSC9132)
... ... @@ -615,6 +619,7 @@
615 619 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
616 620 #define CONFIG_SYS_FSL_ERRATUM_A005125
617 621 #define CONFIG_SYS_FSL_ERRATUM_A005434
  622 +#define CONFIG_SYS_FSL_ERRATUM_A004477
618 623 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
619 624 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
620 625 #define CONFIG_ESDHC_HC_BLK_ADDR
... ... @@ -723,6 +728,7 @@
723 728 #define CONFIG_SYS_FSL_ERRATUM_A006475
724 729 #define CONFIG_SYS_FSL_ERRATUM_A006384
725 730 #define CONFIG_SYS_FSL_ERRATUM_A007212
  731 +#define CONFIG_SYS_FSL_ERRATUM_A004477
726 732 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
727 733 #define CONFIG_SYS_FSL_SFP_VER_3_0
728 734  
... ... @@ -769,7 +775,6 @@
769 775 #endif
770 776 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
771 777 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
772   -#define CONFIG_SYS_SDHC_CLOCK 0
773 778 #define CONFIG_SYS_FSL_NUM_LAWS 16
774 779 #define CONFIG_SYS_FSL_SRDS_1
775 780 #define CONFIG_SYS_FSL_SEC_COMPAT 5
... ... @@ -785,6 +790,9 @@
785 790 #define CONFIG_SYS_FMAN_V3
786 791 #define CONFIG_FM_PLAT_CLK_DIV 1
787 792 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
  793 +#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
  794 + per rcw field value */
  795 +#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
788 796 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
789 797 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
790 798 #define CONFIG_SYS_FSL_TBCLK_DIV 16
... ... @@ -817,7 +825,6 @@
817 825 #endif
818 826 #define CONFIG_SYS_FSL_NUM_CC_PLL 2
819 827 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
820   -#define CONFIG_SYS_SDHC_CLOCK 0
821 828 #define CONFIG_SYS_FSL_NUM_LAWS 16
822 829 #define CONFIG_SYS_FSL_SRDS_1
823 830 #define CONFIG_SYS_FSL_SEC_COMPAT 5
... ... @@ -830,6 +837,8 @@
830 837 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
831 838 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
832 839 #define CONFIG_SYS_FM1_CLK 0
  840 +#define CONFIG_SYS_SDHC_CLK 0/* Select SDHC CLK begining from PLL1
  841 + per rcw field value */
833 842 #define CONFIG_QBMAN_CLK_DIV 1
834 843 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
835 844 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
... ... @@ -877,6 +886,9 @@
877 886 #define CONFIG_PME_PLAT_CLK_DIV 1
878 887 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
879 888 #define CONFIG_SYS_FM1_CLK 0
  889 +#define CONFIG_SYS_SDHC_CLK 1/* Select SDHC CLK begining from PLL2
  890 + per rcw field value */
  891 +#define CONFIG_SYS_SDHC_CLK_2_PLL /* Select SDHC CLK from 2 PLLs */
880 892 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
881 893 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
882 894 #define CONFIG_SYS_FMAN_V3
arch/powerpc/include/asm/fsl_pci.h
Diff comments   View file @ d81572c
... ... @@ -19,6 +19,7 @@
19 19 #define FSL_PCI_PBFR 0x44
20 20  
21 21 #define FSL_PCIE_CFG_RDY 0x4b0
  22 +#define FSL_PCIE_V3_CFG_RDY 0x1
22 23 #define FSL_PROG_IF_AGENT 0x1
23 24  
24 25 #define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
arch/powerpc/include/asm/global_data.h
Diff comments   View file @ d81572c
... ... @@ -15,6 +15,9 @@
15 15 struct arch_global_data {
16 16 #if defined(CONFIG_FSL_ESDHC)
17 17 u32 sdhc_clk;
  18 +#if defined(CONFIG_FSL_ESDHC_ADAPTER_IDENT)
  19 + u8 sdhc_adapter;
  20 +#endif
18 21 #endif
19 22 #if defined(CONFIG_8xx)
20 23 unsigned long brg_clk;
arch/powerpc/include/asm/mpc85xx_gpio.h
Diff comments   View file @ d81572c
... ... @@ -72,9 +72,10 @@
72 72 return 0;
73 73 }
74 74  
75   -static inline void gpio_free(unsigned gpio)
  75 +static inline int gpio_free(unsigned gpio)
76 76 {
77 77 /* Compatibility shim */
  78 + return 0;
78 79 }
79 80  
80 81 static inline int gpio_direction_input(unsigned gpio)
81 82  
... ... @@ -97,12 +98,13 @@
97 98 return !!mpc85xx_gpio_get(1U << gpio);
98 99 }
99 100  
100   -static inline void gpio_set_value(unsigned gpio, int value)
  101 +static inline int gpio_set_value(unsigned gpio, int value)
101 102 {
102 103 if (value)
103 104 mpc85xx_gpio_set_high(1U << gpio);
104 105 else
105 106 mpc85xx_gpio_set_low(1U << gpio);
  107 + return 0;
106 108 }
107 109  
108 110 static inline int gpio_is_valid(int gpio)
arch/powerpc/lib/ppccache.S
Diff comments   View file @ d81572c
... ... @@ -9,7 +9,10 @@
9 9  
10 10 #include <config.h>
11 11 #include <ppc_asm.tmpl>
  12 +#include <ppc_defs.h>
12 13  
  14 +#include <asm/cache.h>
  15 +
13 16 /*------------------------------------------------------------------------------- */
14 17 /* Function: ppcDcbf */
15 18 /* Description: Data Cache block flush */
... ... @@ -53,5 +56,49 @@
53 56 .globl ppcSync
54 57 ppcSync:
55 58 sync
  59 + blr
  60 +
  61 +/*
  62 + * Write any modified data cache blocks out to memory and invalidate them.
  63 + * Does not invalidate the corresponding instruction cache blocks.
  64 + *
  65 + * flush_dcache_range(unsigned long start, unsigned long stop)
  66 + */
  67 +_GLOBAL(flush_dcache_range)
  68 + li r5,L1_CACHE_BYTES-1
  69 + andc r3,r3,r5
  70 + subf r4,r3,r4
  71 + add r4,r4,r5
  72 + srwi. r4,r4,L1_CACHE_SHIFT
  73 + beqlr
  74 + mtctr r4
  75 +
  76 +1: dcbf 0,r3
  77 + addi r3,r3,L1_CACHE_BYTES
  78 + bdnz 1b
  79 + sync /* wait for dcbst's to get to ram */
  80 + blr
  81 +
  82 +/*
  83 + * Like above, but invalidate the D-cache. This is used by the 8xx
  84 + * to invalidate the cache so the PPC core doesn't get stale data
  85 + * from the CPM (no cache snooping here :-).
  86 + *
  87 + * invalidate_dcache_range(unsigned long start, unsigned long stop)
  88 + */
  89 +_GLOBAL(invalidate_dcache_range)
  90 + li r5,L1_CACHE_BYTES-1
  91 + andc r3,r3,r5
  92 + subf r4,r3,r4
  93 + add r4,r4,r5
  94 + srwi. r4,r4,L1_CACHE_SHIFT
  95 + beqlr
  96 + mtctr r4
  97 +
  98 + sync
  99 +1: dcbi 0,r3
  100 + addi r3,r3,L1_CACHE_BYTES
  101 + bdnz 1b
  102 + sync /* wait for dcbi's to get to ram */
56 103 blr
board/Arcturus/ucp1020/Kconfig
Diff comments   View file @ d81572c
  1 +if TARGET_UCP1020
  2 +
  3 +config SYS_BOARD
  4 + string
  5 + default "ucp1020"
  6 +
  7 +config SYS_VENDOR
  8 + string
  9 + default "Arcturus"
  10 +
  11 +config SYS_CONFIG_NAME
  12 + string
  13 + default "UCP1020"
  14 +
  15 +config SPI_FLASH
  16 + bool
  17 + default y
  18 +
  19 +config SPI_PCI
  20 + bool
  21 + default y
  22 +
  23 +choice
  24 + prompt "Target image select"
  25 +
  26 +config TARGET_UCP1020_NOR
  27 + bool "NOR flash u-boot image"
  28 +
  29 +config TARGET_UCP1020_SPIFLASH
  30 + bool "SPI flash u-boot image"
  31 +
  32 +endchoice
  33 +
  34 +if TARGET_UCP1020_SPIFLASH
  35 +config UCBOOT
  36 + bool
  37 + default y
  38 +
  39 +config SPIFLASH
  40 + bool
  41 + default y
  42 +endif
  43 +
  44 +endif
board/Arcturus/ucp1020/MAINTAINERS
Diff comments   View file @ d81572c
  1 +UCP1020 BOARD
  2 +M: Oleksandr Zhadan and Michael Durrant <arcsupport@arcturusnetworks.com>
  3 +S: Maintained
  4 +F: board/Arcturus/ucp1020/
  5 +F: include/configs/UCP1020.h
  6 +F: configs/UCP1020_defconfig
  7 +F: configs/UCP1020_SPIFLASH_defconfig
board/Arcturus/ucp1020/Makefile
Diff comments   View file @ d81572c
  1 +#
  2 +# Copyright 2013-2015 Arcturus Networks, Inc.
  3 +# based on board/freescale/p1_p2_rdb_pc/Makefile
  4 +# original copyright follows:
  5 +# Copyright 2010-2011 Freescale Semiconductor, Inc.
  6 +#
  7 +# SPDX-License-Identifier: GPL-2.0+
  8 +#
  9 +
  10 +MINIMAL=
  11 +
  12 +ifdef CONFIG_SPL_BUILD
  13 +ifdef CONFIG_SPL_INIT_MINIMAL
  14 +MINIMAL=y
  15 +endif
  16 +endif
  17 +
  18 +ifdef MINIMAL
  19 +
  20 +obj-y += spl_minimal.o tlb.o law.o
  21 +
  22 +else
  23 +ifdef CONFIG_SPL_BUILD
  24 +obj-y += spl.o
  25 +endif
  26 +
  27 +obj-y += ucp1020.o
  28 +obj-y += ddr.o
  29 +obj-y += law.o
  30 +obj-y += tlb.o
  31 +obj-y += cmd_arc.o
  32 +
  33 +endif
board/Arcturus/ucp1020/README
Diff comments   View file @ d81572c
  1 +The uCP1020 product family (ucp1020) is an Arcturus Networks Inc. System on Modules
  2 +product featuring a Freescale P1020 CPU, optionally populated with 1, 2 or 3 Gig-Ethernet PHYs,
  3 +DDR3, NOR Flash, eMMC NAND Flash and/or SPI Flash.
  4 +
  5 +Information on the generic product family can be found here:
  6 + http://www.arcturusnetworks.com/products/ucp1020
  7 +
  8 +The UCP1020 several configurable options
  9 +========================================
  10 +
  11 +- the selection of populated phy(s):
  12 + KSZ9031 (current default for eTSEC 1 and 3)
  13 +
  14 +- the selection of boot location:
  15 + SPI Flash or NOR flash
  16 +
  17 +The UCP1020 includes 2 default configurations
  18 +=============================================
  19 +NOR boot image:
  20 + configs/UCP1020_defconfig
  21 +SPI boot image:
  22 + configs/UCP1020_SPIFLASH_defconfig
  23 +
  24 +The UCP1020 adds an additional command in cmd_arc.c to access and program
  25 +SPI resident factory defaults for serial number, and 1, 2 or 3 Ethernet
  26 +HW Addresses.
  27 +
  28 +
  29 +Build example
  30 +=============
  31 +
  32 +make distclean
  33 +make UCP1020_defconfig
  34 +make
  35 +
  36 +Default Scripts
  37 +===============
  38 +A default upgrade scripts is included in the default environment variable example:
  39 +
  40 +B$ run tftpflash
  41 +
  42 +Dual Environment
  43 +================
  44 +
  45 +This build enables dual / failover environment environment.
  46 +
  47 +NOR Flash Partition declarations and scripts
  48 +============================================
  49 +Several scripts are available to allow TFTP of images and programming directly
  50 +into defined NOR flash partitions. Examples:
  51 +
  52 +B$ run program0
  53 +B$ run program1
  54 +B$ run program2
board/Arcturus/ucp1020/cmd_arc.c
Diff comments   View file @ d81572c
  1 +/*
  2 + * Command for accessing Arcturus factory environment.
  3 + *
  4 + * Copyright 2013-2015 Arcturus Networks Inc.
  5 + * http://www.arcturusnetworks.com/products/ucp1020/
  6 + * by Oleksandr G Zhadan et al.
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
  9 + *
  10 + */
  11 +
  12 +#include <common.h>
  13 +#include <div64.h>
  14 +#include <malloc.h>
  15 +#include <spi_flash.h>
  16 +
  17 +#include <asm/io.h>
  18 +
  19 +#ifndef CONFIG_SF_DEFAULT_SPEED
  20 +# define CONFIG_SF_DEFAULT_SPEED 1000000
  21 +#endif
  22 +#ifndef CONFIG_SF_DEFAULT_MODE
  23 +# define CONFIG_SF_DEFAULT_MODE SPI_MODE0
  24 +#endif
  25 +#ifndef CONFIG_SF_DEFAULT_CS
  26 +# define CONFIG_SF_DEFAULT_CS 0
  27 +#endif
  28 +#ifndef CONFIG_SF_DEFAULT_BUS
  29 +# define CONFIG_SF_DEFAULT_BUS 0
  30 +#endif
  31 +
  32 +#define MAX_SERIAL_SIZE 15
  33 +#define MAX_HWADDR_SIZE 17
  34 +
  35 +#define FIRM_ADDR1 (0x200 - sizeof(smac))
  36 +#define FIRM_ADDR2 (0x400 - sizeof(smac))
  37 +#define FIRM_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac))
  38 +#define FIRM_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac))
  39 +
  40 +static struct spi_flash *flash;
  41 +char smac[4][18];
  42 +
  43 +static int ishwaddr(char *hwaddr)
  44 +{
  45 + if (strlen(hwaddr) == MAX_HWADDR_SIZE)
  46 + if (hwaddr[2] == ':' &&
  47 + hwaddr[5] == ':' &&
  48 + hwaddr[8] == ':' &&
  49 + hwaddr[11] == ':' &&
  50 + hwaddr[14] == ':')
  51 + return 0;
  52 + return -1;
  53 +}
  54 +
  55 +static int set_arc_product(int argc, char *const argv[])
  56 +{
  57 + int err = 0;
  58 + char *mystrerr = "ERROR: Failed to save factory info in spi location";
  59 +
  60 + if (argc != 5)
  61 + return -1;
  62 +
  63 + /* Check serial number */
  64 + if (strlen(argv[1]) != MAX_SERIAL_SIZE)
  65 + return -1;
  66 +
  67 + /* Check HWaddrs */
  68 + if (ishwaddr(argv[2]) || ishwaddr(argv[3]) || ishwaddr(argv[4]))
  69 + return -1;
  70 +
  71 + strcpy(smac[3], argv[1]);
  72 + strcpy(smac[2], argv[2]);
  73 + strcpy(smac[1], argv[3]);
  74 + strcpy(smac[0], argv[4]);
  75 +
  76 + flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
  77 + CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
  78 +
  79 + /*
  80 + * Save factory defaults
  81 + */
  82 +
  83 + if (spi_flash_write(flash, FIRM_ADDR1, sizeof(smac), smac)) {
  84 + printf("%s: %s [1]\n", __func__, mystrerr);
  85 + err++;
  86 + }
  87 + if (spi_flash_write(flash, FIRM_ADDR2, sizeof(smac), smac)) {
  88 + printf("%s: %s [2]\n", __func__, mystrerr);
  89 + err++;
  90 + }
  91 +
  92 + if (spi_flash_write(flash, FIRM_ADDR3, sizeof(smac), smac)) {
  93 + printf("%s: %s [3]\n", __func__, mystrerr);
  94 + err++;
  95 + }
  96 +
  97 + if (spi_flash_write(flash, FIRM_ADDR4, sizeof(smac), smac)) {
  98 + printf("%s: %s [4]\n", __func__, mystrerr);
  99 + err++;
  100 + }
  101 +
  102 + if (err == 4) {
  103 + printf("%s: %s [ALL]\n", __func__, mystrerr);
  104 + return -2;
  105 + }
  106 +
  107 + return 0;
  108 +}
  109 +
  110 +int get_arc_info(void)
  111 +{
  112 + int location = 1;
  113 + char *myerr = "ERROR: Failed to read all 4 factory info spi locations";
  114 +
  115 + flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
  116 + CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
  117 +
  118 + if (spi_flash_read(flash, FIRM_ADDR1, sizeof(smac), smac)) {
  119 + location++;
  120 + if (spi_flash_read(flash, FIRM_ADDR2, sizeof(smac), smac)) {
  121 + location++;
  122 + if (spi_flash_read(flash, FIRM_ADDR3, sizeof(smac),
  123 + smac)) {
  124 + location++;
  125 + if (spi_flash_read(flash, FIRM_ADDR4,
  126 + sizeof(smac), smac)) {
  127 + printf("%s: %s\n", __func__, myerr);
  128 + return -2;
  129 + }
  130 + }
  131 + }
  132 + }
  133 + if (smac[3][0] != 0) {
  134 + if (location > 1)
  135 + printf("Using region %d\n", location);
  136 + printf("SERIAL: ");
  137 + if (smac[3][0] == 0xFF) {
  138 + printf("\t<not found>\n");
  139 + } else {
  140 + printf("\t%s\n", smac[3]);
  141 + setenv("SERIAL", smac[3]);
  142 + }
  143 + }
  144 +
  145 + if (strcmp(smac[2], "00:00:00:00:00:00") == 0)
  146 + return 0;
  147 +
  148 + printf("HWADDR0:");
  149 + if (smac[2][0] == 0xFF) {
  150 + printf("\t<not found>\n");
  151 + } else {
  152 + char *ret = getenv("ethaddr");
  153 +
  154 + if (strcmp(ret, __stringify(CONFIG_ETHADDR)) == 0) {
  155 + setenv("ethaddr", smac[2]);
  156 + printf("\t%s (factory)\n", smac[2]);
  157 + } else {
  158 + printf("\t%s\n", ret);
  159 + }
  160 + }
  161 +
  162 + if (strcmp(smac[1], "00:00:00:00:00:00") == 0) {
  163 + setenv("eth1addr", smac[2]);
  164 + setenv("eth2addr", smac[2]);
  165 + return 0;
  166 + }
  167 +
  168 + printf("HWADDR1:");
  169 + if (smac[1][0] == 0xFF) {
  170 + printf("\t<not found>\n");
  171 + } else {
  172 + char *ret = getenv("eth1addr");
  173 +
  174 + if (strcmp(ret, __stringify(CONFIG_ETH1ADDR)) == 0) {
  175 + setenv("eth1addr", smac[1]);
  176 + printf("\t%s (factory)\n", smac[1]);
  177 + } else {
  178 + printf("\t%s\n", ret);
  179 + }
  180 + }
  181 +
  182 + if (strcmp(smac[0], "00:00:00:00:00:00") == 0) {
  183 + setenv("eth2addr", smac[1]);
  184 + return 0;
  185 + }
  186 +
  187 + printf("HWADDR2:");
  188 + if (smac[0][0] == 0xFF) {
  189 + printf("\t<not found>\n");
  190 + } else {
  191 + char *ret = getenv("eth2addr");
  192 +
  193 + if (strcmp(ret, __stringify(CONFIG_ETH2ADDR)) == 0) {
  194 + setenv("eth2addr", smac[0]);
  195 + printf("\t%s (factory)\n", smac[0]);
  196 + } else {
  197 + printf("\t%s\n", ret);
  198 + }
  199 + }
  200 +
  201 + return 0;
  202 +}
  203 +
  204 +static int do_arc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
  205 +{
  206 + const char *cmd;
  207 + int ret = -1;
  208 +
  209 + cmd = argv[1];
  210 + --argc;
  211 + ++argv;
  212 +
  213 + if (strcmp(cmd, "product") == 0) {
  214 + ret = set_arc_product(argc, argv);
  215 + goto done;
  216 + }
  217 + if (strcmp(cmd, "info") == 0) {
  218 + ret = get_arc_info();
  219 + goto done;
  220 + }
  221 +done:
  222 + if (ret == -1)
  223 + return CMD_RET_USAGE;
  224 +
  225 + return ret;
  226 +}
  227 +
  228 +U_BOOT_CMD(arc, 6, 1, do_arc_cmd,
  229 + "Arcturus product command sub-system",
  230 + "product serial hwaddr0 hwaddr1 hwaddr2 - save Arcturus factory env\n"
  231 + "info - show Arcturus factory env\n\n");
board/Arcturus/ucp1020/ddr.c
Diff comments   View file @ d81572c
  1 +/*
  2 + * Copyright 2013-2015 Arcturus Networks, Inc.
  3 + * http://www.arcturusnetworks.com/products/ucp1020/
  4 + * based on board/freescale/p1_p2_rdb_pc/spl.c
  5 + * original copyright follows:
  6 + * Copyright 2013 Freescale Semiconductor, Inc.
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#include <common.h>
  12 +#include <asm/mmu.h>
  13 +#include <asm/immap_85xx.h>
  14 +#include <asm/processor.h>
  15 +#include <fsl_ddr_sdram.h>
  16 +#include <fsl_ddr_dimm_params.h>
  17 +#include <asm/io.h>
  18 +#include <asm/fsl_law.h>
  19 +
  20 +#ifdef CONFIG_SYS_DDR_RAW_TIMING
  21 +#if defined(CONFIG_UCP1020) || defined(CONFIG_UCP1020T1)
  22 +/*
  23 + * Micron MT41J128M16HA-15E
  24 + * */
  25 +dimm_params_t ddr_raw_timing = {
  26 + .n_ranks = 1,
  27 + .rank_density = 536870912u,
  28 + .capacity = 536870912u,
  29 + .primary_sdram_width = 32,
  30 + .ec_sdram_width = 8,
  31 + .registered_dimm = 0,
  32 + .mirrored_dimm = 0,
  33 + .n_row_addr = 14,
  34 + .n_col_addr = 10,
  35 + .n_banks_per_sdram_device = 8,
  36 + .edc_config = 2,
  37 + .burst_lengths_bitmask = 0x0c,
  38 +
  39 + .tckmin_x_ps = 1650,
  40 + .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */
  41 + .taa_ps = 14050,
  42 + .twr_ps = 15000,
  43 + .trcd_ps = 13500,
  44 + .trrd_ps = 75000,
  45 + .trp_ps = 13500,
  46 + .tras_ps = 40000,
  47 + .trc_ps = 49500,
  48 + .trfc_ps = 160000,
  49 + .twtr_ps = 75000,
  50 + .trtp_ps = 75000,
  51 + .refresh_rate_ps = 7800000,
  52 + .tfaw_ps = 30000,
  53 +};
  54 +
  55 +#else
  56 +#error Missing raw timing data for this board
  57 +#endif
  58 +
  59 +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  60 + unsigned int controller_number,
  61 + unsigned int dimm_number)
  62 +{
  63 + const char dimm_model[] = "Fixed DDR on board";
  64 +
  65 + if ((controller_number == 0) && (dimm_number == 0)) {
  66 + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  67 + memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  68 + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  69 + }
  70 +
  71 + return 0;
  72 +}
  73 +#endif /* CONFIG_SYS_DDR_RAW_TIMING */
  74 +
  75 +#ifdef CONFIG_SYS_DDR_CS0_BNDS
  76 +/* Fixed sdram init -- doesn't use serial presence detect. */
  77 +phys_size_t fixed_sdram(void)
  78 +{
  79 + sys_info_t sysinfo;
  80 + char buf[32];
  81 + size_t ddr_size;
  82 + fsl_ddr_cfg_regs_t ddr_cfg_regs = {
  83 + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
  84 + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
  85 + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  86 +#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
  87 + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
  88 + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
  89 + .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
  90 +#endif
  91 + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
  92 + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
  93 + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
  94 + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
  95 + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
  96 + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
  97 + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
  98 + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
  99 + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  100 + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
  101 + .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
  102 + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
  103 + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
  104 + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
  105 + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
  106 + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
  107 + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
  108 + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
  109 + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
  110 + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
  111 + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
  112 + };
  113 +
  114 + get_sys_info(&sysinfo);
  115 + printf("Configuring DDR for %s MT/s data rate\n",
  116 + strmhz(buf, sysinfo.freq_ddrbus));
  117 +
  118 + ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  119 +
  120 + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
  121 +
  122 + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
  123 + ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
  124 + printf("ERROR setting Local Access Windows for DDR\n");
  125 + return 0;
  126 + };
  127 +
  128 + return ddr_size;
  129 +}
  130 +#endif
  131 +
  132 +void fsl_ddr_board_options(memctl_options_t *popts,
  133 + dimm_params_t *pdimm,
  134 + unsigned int ctrl_num)
  135 +{
  136 + int i;
  137 +
  138 + popts->clk_adjust = 6;
  139 + popts->cpo_override = 0x1f;
  140 + popts->write_data_delay = 2;
  141 + popts->half_strength_driver_enable = 1;
  142 + /* Write leveling override */
  143 + popts->wrlvl_en = 1;
  144 + popts->wrlvl_override = 1;
  145 + popts->wrlvl_sample = 0xf;
  146 + popts->wrlvl_start = 0x8;
  147 + popts->trwt_override = 1;
  148 + popts->trwt = 0;
  149 +
  150 + if (pdimm->primary_sdram_width == 64)
  151 + popts->data_bus_width = 0;
  152 + else if (pdimm->primary_sdram_width == 32)
  153 + popts->data_bus_width = 1;
  154 + else
  155 + printf("Error in DDR bus width configuration!\n");
  156 +
  157 + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  158 + popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
  159 + popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
  160 + }
  161 +}
board/Arcturus/ucp1020/law.c
Diff comments   View file @ d81572c
  1 +/*
  2 + * Copyright 2013-2015 Arcturus Networks, Inc.
  3 + * http://www.arcturusnetworks.com/products/ucp1020/
  4 + * based on board/freescale/p1_p2_rdb_pc/spl.c
  5 + * original copyright follows:
  6 + * Copyright 2013 Freescale Semiconductor, Inc.
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#include <common.h>
  12 +#include <asm/fsl_law.h>
  13 +#include <asm/mmu.h>
  14 +
  15 +struct law_entry law_table[] = {
  16 +#ifdef CONFIG_VSC7385_ENET
  17 + SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
  18 +#endif
  19 + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
  20 +#ifdef CONFIG_SYS_NAND_BASE_PHYS
  21 + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
  22 +#endif
  23 +};
  24 +
  25 +int num_law_entries = ARRAY_SIZE(law_table);
board/Arcturus/ucp1020/spl.c
Diff comments   View file @ d81572c
  1 +/*
  2 + * Copyright 2013-2015 Arcturus Networks, Inc.
  3 + * http://www.arcturusnetworks.com/products/ucp1020/
  4 + * based on board/freescale/p1_p2_rdb_pc/spl.c
  5 + * original copyright follows:
  6 + * Copyright 2013 Freescale Semiconductor, Inc.
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#include <common.h>
  12 +#include <ns16550.h>
  13 +#include <malloc.h>
  14 +#include <mmc.h>
  15 +#include <nand.h>
  16 +#include <i2c.h>
  17 +#include <fsl_esdhc.h>
  18 +#include <spi_flash.h>
  19 +
  20 +DECLARE_GLOBAL_DATA_PTR;
  21 +
  22 +static const u32 sysclk_tbl[] = {
  23 + 66666000, 7499900, 83332500, 8999900,
  24 + 99999000, 11111000, 12499800, 13333200
  25 +};
  26 +
  27 +phys_size_t get_effective_memsize(void)
  28 +{
  29 + return CONFIG_SYS_L2_SIZE;
  30 +}
  31 +
  32 +void board_init_f(ulong bootflag)
  33 +{
  34 + u32 plat_ratio, bus_clk;
  35 + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  36 +
  37 + console_init_f();
  38 +
  39 + /* Set pmuxcr to allow both i2c1 and i2c2 */
  40 + setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
  41 + setbits_be32(&gur->pmuxcr,
  42 + in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
  43 +
  44 + /* Read back the register to synchronize the write. */
  45 + in_be32(&gur->pmuxcr);
  46 +
  47 +#ifdef CONFIG_SPL_SPI_BOOT
  48 + clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
  49 +#endif
  50 +
  51 + /* initialize selected port with appropriate baud rate */
  52 + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
  53 + plat_ratio >>= 1;
  54 + bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
  55 + gd->bus_clk = bus_clk;
  56 +
  57 + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  58 + bus_clk / 16 / CONFIG_BAUDRATE);
  59 +#ifdef CONFIG_SPL_MMC_BOOT
  60 + puts("\nSD boot...\n");
  61 +#elif defined(CONFIG_SPL_SPI_BOOT)
  62 + puts("\nSPI Flash boot...\n");
  63 +#endif
  64 +
  65 + /* copy code to RAM and jump to it - this should not return */
  66 + /* NOTE - code has to be copied out of NAND buffer before
  67 + * other blocks can be read.
  68 + */
  69 + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
  70 +}
  71 +
  72 +void board_init_r(gd_t *gd, ulong dest_addr)
  73 +{
  74 + /* Pointer is writable since we allocated a register for it */
  75 + gd = (gd_t *)CONFIG_SPL_GD_ADDR;
  76 + bd_t *bd;
  77 +
  78 + memset(gd, 0, sizeof(gd_t));
  79 + bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
  80 + memset(bd, 0, sizeof(bd_t));
  81 + gd->bd = bd;
  82 + bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
  83 + bd->bi_memsize = CONFIG_SYS_L2_SIZE;
  84 +
  85 + probecpu();
  86 + get_clocks();
  87 + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
  88 + CONFIG_SPL_RELOC_MALLOC_SIZE);
  89 +
  90 +#ifndef CONFIG_SPL_NAND_BOOT
  91 + env_init();
  92 +#endif
  93 +#ifdef CONFIG_SPL_MMC_BOOT
  94 + mmc_initialize(bd);
  95 +#endif
  96 + /* relocate environment function pointers etc. */
  97 +#ifdef CONFIG_SPL_NAND_BOOT
  98 + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  99 + (uchar *)CONFIG_ENV_ADDR);
  100 + gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
  101 + gd->env_valid = 1;
  102 +#else
  103 + env_relocate();
  104 +#endif
  105 +
  106 +#ifdef CONFIG_SYS_I2C
  107 + i2c_init_all();
  108 +#else
  109 + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  110 +#endif
  111 +
  112 + gd->ram_size = initdram(0);
  113 +#ifdef CONFIG_SPL_NAND_BOOT
  114 + puts("Tertiary program loader running in sram...");
  115 +#else
  116 + puts("Second program loader running in sram...\n");
  117 +#endif
  118 +
  119 +#ifdef CONFIG_SPL_MMC_BOOT
  120 + mmc_boot();
  121 +#elif defined(CONFIG_SPL_SPI_BOOT)
  122 + spi_boot();
  123 +#elif defined(CONFIG_SPL_NAND_BOOT)
  124 + nand_boot();
  125 +#endif
  126 +}
board/Arcturus/ucp1020/spl_minimal.c
Diff comments   View file @ d81572c
  1 +/*
  2 + * Copyright 2013-2015 Arcturus Networks, Inc.
  3 + * http://www.arcturusnetworks.com/products/ucp1020/
  4 + * based on board/freescale/p1_p2_rdb_pc/spl_minimal.c
  5 + * original copyright follows:
  6 + * Copyright 2011 Freescale Semiconductor, Inc.
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#include <common.h>
  12 +#include <ns16550.h>
  13 +#include <asm/io.h>
  14 +#include <nand.h>
  15 +#include <linux/compiler.h>
  16 +#include <asm/fsl_law.h>
  17 +#include <fsl_ddr_sdram.h>
  18 +#include <asm/global_data.h>
  19 +
  20 +DECLARE_GLOBAL_DATA_PTR;
  21 +
  22 +void board_init_f(ulong bootflag)
  23 +{
  24 + u32 plat_ratio;
  25 + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  26 +
  27 +#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
  28 + set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
  29 + set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
  30 +#endif
  31 +
  32 + /* initialize selected port with appropriate baud rate */
  33 + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
  34 + plat_ratio >>= 1;
  35 + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
  36 +
  37 + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  38 + gd->bus_clk / 16 / CONFIG_BAUDRATE);
  39 +
  40 + puts("\nNAND boot... ");
  41 +
  42 + /* copy code to RAM and jump to it - this should not return */
  43 + /* NOTE - code has to be copied out of NAND buffer before
  44 + * other blocks can be read.
  45 + */
  46 + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
  47 +}
  48 +
  49 +void board_init_r(gd_t *gd, ulong dest_addr)
  50 +{
  51 + puts("\nSecond program loader running in sram...");
  52 + nand_boot();
  53 +}
  54 +
  55 +void putc(char c)
  56 +{
  57 + if (c == '\n')
  58 + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
  59 +
  60 + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
  61 +}
  62 +
  63 +void puts(const char *str)
  64 +{
  65 + while (*str)
  66 + putc(*str++);
  67 +}
board/Arcturus/ucp1020/tlb.c
Diff comments   View file @ d81572c
  1 +/*
  2 + * Copyright 2013-2015 Arcturus Networks, Inc
  3 + * http://www.arcturusnetworks.com/products/ucp1020/
  4 + * based on board/freescale/p1_p2_rdb_pc/tlb.c
  5 + * original copyright follows:
  6 + * Copyright 2010-2011 Freescale Semiconductor, Inc.
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#include <common.h>
  12 +#include <asm/mmu.h>
  13 +
  14 +struct fsl_e_tlb_entry tlb_table[] = {
  15 + /* TLB 0 - for temp stack in cache */
  16 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  17 + CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  18 + MAS3_SX | MAS3_SW | MAS3_SR, 0,
  19 + 0, 0, BOOKE_PAGESZ_4K, 0),
  20 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  21 + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  22 + MAS3_SX | MAS3_SW | MAS3_SR, 0,
  23 + 0, 0, BOOKE_PAGESZ_4K, 0),
  24 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  25 + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  26 + MAS3_SX | MAS3_SW | MAS3_SR, 0,
  27 + 0, 0, BOOKE_PAGESZ_4K, 0),
  28 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  29 + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  30 + MAS3_SX | MAS3_SW | MAS3_SR, 0,
  31 + 0, 0, BOOKE_PAGESZ_4K, 0),
  32 +
  33 + /* TLB 1 */
  34 + /* *I*** - Covers boot page */
  35 + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  36 + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I,
  37 + 0, 0, BOOKE_PAGESZ_4K, 1),
  38 +
  39 + /* *I*G* - CCSRBAR */
  40 + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  41 + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  42 + 0, 1, BOOKE_PAGESZ_1M, 1),
  43 +
  44 +#ifndef CONFIG_SPL_BUILD
  45 + /* W**G* - Flash/promjet, localbus */
  46 + /* This will be changed to *I*G* after relocation to RAM. */
  47 + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  48 + MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
  49 + 0, 2, BOOKE_PAGESZ_64M, 1),
  50 +
  51 +#ifdef CONFIG_PCI
  52 + /* *I*G* - PCI memory 1.5G */
  53 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  54 + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  55 + 0, 3, BOOKE_PAGESZ_1G, 1),
  56 +
  57 + /* *I*G* - PCI I/O effective: 192K */
  58 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  59 + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  60 + 0, 4, BOOKE_PAGESZ_256K, 1),
  61 +#endif
  62 +
  63 +#ifdef CONFIG_VSC7385_ENET
  64 + /* *I*G - VSC7385 Switch */
  65 + SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
  66 + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  67 + 0, 5, BOOKE_PAGESZ_1M, 1),
  68 +#endif
  69 +#endif /* not SPL */
  70 +
  71 +#ifdef CONFIG_SYS_NAND_BASE
  72 + /* *I*G - NAND */
  73 + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  74 + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  75 + 0, 7, BOOKE_PAGESZ_1M, 1),
  76 +#endif
  77 +
  78 +#if defined(CONFIG_SYS_RAMBOOT) || \
  79 + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
  80 + /* *I*G - eSDHC/eSPI/NAND boot */
  81 + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
  82 + MAS3_SX | MAS3_SW | MAS3_SR, 0,
  83 + 0, 8, BOOKE_PAGESZ_1G, 1),
  84 +
  85 +#endif /* RAMBOOT/SPL */
  86 +
  87 +#ifdef CONFIG_SYS_INIT_L2_ADDR
  88 + /* *I*G - L2SRAM */
  89 + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
  90 + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G,
  91 + 0, 11, BOOKE_PAGESZ_256K, 1),
  92 +#if CONFIG_SYS_L2_SIZE >= (256 << 10)
  93 + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
  94 + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
  95 + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  96 + 0, 12, BOOKE_PAGESZ_256K, 1)
  97 +#endif
  98 +#endif
  99 +};
  100 +
  101 +int num_tlb_entries = ARRAY_SIZE(tlb_table);
board/Arcturus/ucp1020/ucp1020.c
Diff comments   View file @ d81572c
  1 +/*
  2 + * Copyright 2013-2015 Arcturus Networks, Inc.
  3 + * http://www.arcturusnetworks.com/products/ucp1020/
  4 + * by Oleksandr G Zhadan et al.
  5 + * based on board/freescale/p1_p2_rdb_pc/spl.c
  6 + * original copyright follows:
  7 + * Copyright 2013 Freescale Semiconductor, Inc.
  8 + *
  9 + * SPDX-License-Identifier: GPL-2.0+
  10 + */
  11 +
  12 +#include <common.h>
  13 +#include <command.h>
  14 +#include <hwconfig.h>
  15 +#include <pci.h>
  16 +#include <i2c.h>
  17 +#include <miiphy.h>
  18 +#include <libfdt.h>
  19 +#include <fdt_support.h>
  20 +#include <fsl_mdio.h>
  21 +#include <tsec.h>
  22 +#include <ioports.h>
  23 +#include <netdev.h>
  24 +#include <micrel.h>
  25 +#include <spi_flash.h>
  26 +#include <mmc.h>
  27 +#include <linux/ctype.h>
  28 +#include <asm/fsl_serdes.h>
  29 +#include <asm/gpio.h>
  30 +#include <asm/processor.h>
  31 +#include <asm/mmu.h>
  32 +#include <asm/cache.h>
  33 +#include <asm/immap_85xx.h>
  34 +#include <asm/fsl_pci.h>
  35 +#include <fsl_ddr_sdram.h>
  36 +#include <asm/io.h>
  37 +#include <asm/fsl_law.h>
  38 +#include <asm/fsl_lbc.h>
  39 +#include <asm/mp.h>
  40 +#include "ucp1020.h"
  41 +
  42 +void spi_set_speed(struct spi_slave *slave, uint hz)
  43 +{
  44 + /* TO DO: It's actially have to be in spi/ */
  45 +}
  46 +
  47 +/*
  48 + * To be compatible with cmd_gpio
  49 + */
  50 +int name_to_gpio(const char *name)
  51 +{
  52 + int gpio = 31 - simple_strtoul(name, NULL, 10);
  53 +
  54 + if (gpio < 16)
  55 + gpio = -1;
  56 +
  57 + return gpio;
  58 +}
  59 +
  60 +void board_gpio_init(void)
  61 +{
  62 + int i;
  63 + char envname[8], *val;
  64 +
  65 + for (i = 0; i < GPIO_MAX_NUM; i++) {
  66 + sprintf(envname, "GPIO%d", i);
  67 + val = getenv(envname);
  68 + if (val) {
  69 + char direction = toupper(val[0]);
  70 + char level = toupper(val[1]);
  71 +
  72 + if (direction == 'I') {
  73 + gpio_direction_input(i);
  74 + } else {
  75 + if (direction == 'O') {
  76 + if (level == '1')
  77 + gpio_direction_output(i, 1);
  78 + else
  79 + gpio_direction_output(i, 0);
  80 + }
  81 + }
  82 + }
  83 + }
  84 +
  85 + val = getenv("PCIE_OFF");
  86 + if (val) {
  87 + gpio_direction_input(GPIO_PCIE1_EN);
  88 + gpio_direction_input(GPIO_PCIE2_EN);
  89 + } else {
  90 + gpio_direction_output(GPIO_PCIE1_EN, 1);
  91 + gpio_direction_output(GPIO_PCIE2_EN, 1);
  92 + }
  93 +
  94 + val = getenv("SDHC_CDWP_OFF");
  95 + if (!val) {
  96 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  97 +
  98 + setbits_be32(&gur->pmuxcr,
  99 + (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
  100 + }
  101 +}
  102 +
  103 +int board_early_init_f(void)
  104 +{
  105 + return 0; /* Just in case. Could be disable in config file */
  106 +}
  107 +
  108 +int checkboard(void)
  109 +{
  110 + printf("Board: %s\n", CONFIG_BOARDNAME_LOCAL);
  111 + board_gpio_init();
  112 + printf("SD/MMC: 4-bit Mode\n");
  113 +
  114 + return 0;
  115 +}
  116 +
  117 +#ifdef CONFIG_PCI
  118 +void pci_init_board(void)
  119 +{
  120 + fsl_pcie_init_board(0);
  121 +}
  122 +#endif
  123 +
  124 +int board_early_init_r(void)
  125 +{
  126 + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  127 + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  128 +
  129 + /*
  130 + * Remap Boot flash region to caching-inhibited
  131 + * so that flash can be erased properly.
  132 + */
  133 +
  134 + /* Flush d-cache and invalidate i-cache of any FLASH data */
  135 + flush_dcache();
  136 + invalidate_icache();
  137 +
  138 + /* invalidate existing TLB entry for flash */
  139 + disable_tlb(flash_esel);
  140 +
  141 + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
  142 + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, /* perms, wimge */
  143 + 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
  144 +
  145 + return 0;
  146 +}
  147 +
  148 +int board_phy_config(struct phy_device *phydev)
  149 +{
  150 +#if defined(CONFIG_PHY_MICREL_KSZ9021)
  151 + int regval;
  152 + static int cnt;
  153 +
  154 + if (cnt++ == 0)
  155 + printf("PHYs address [");
  156 +
  157 + if (phydev->addr == TSEC1_PHY_ADDR || phydev->addr == TSEC3_PHY_ADDR) {
  158 + regval =
  159 + ksz9021_phy_extended_read(phydev,
  160 + MII_KSZ9021_EXT_STRAP_STATUS);
  161 + /*
  162 + * min rx data delay
  163 + */
  164 + ksz9021_phy_extended_write(phydev,
  165 + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
  166 + 0x6666);
  167 + /*
  168 + * max rx/tx clock delay, min rx/tx control
  169 + */
  170 + ksz9021_phy_extended_write(phydev,
  171 + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
  172 + 0xf6f6);
  173 + printf("0x%x", (regval & 0x1f));
  174 + } else {
  175 + printf("0x%x", (TSEC2_PHY_ADDR & 0x1f));
  176 + }
  177 + if (cnt == 3)
  178 + printf("] ");
  179 + else
  180 + printf(",");
  181 +#endif
  182 +
  183 +#if defined(CONFIG_PHY_MICREL_KSZ9031_DEBUG)
  184 + regval = ksz9031_phy_extended_read(phydev, 2, 0x01, 0x4000);
  185 + if (regval >= 0)
  186 + printf(" (ADDR 0x%x) ", regval & 0x1f);
  187 +#endif
  188 +
  189 + return 0;
  190 +}
  191 +
  192 +int last_stage_init(void)
  193 +{
  194 + static char newkernelargs[256];
  195 + static u8 id1[16];
  196 + static u8 id2;
  197 + struct mmc *mmc;
  198 + char *sval, *kval;
  199 +
  200 + if (i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 7, 1, &id1[0], 2) < 0) {
  201 + printf("Error reading i2c IDT6V49205B information!\n");
  202 + } else {
  203 + printf("IDT6V49205B(0x%02x): ready\n", id1[1]);
  204 + i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
  205 + if (!(id1[1] & 0x02)) {
  206 + id1[1] |= 0x02;
  207 + i2c_write(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
  208 + asm("nop; nop");
  209 + }
  210 + }
  211 +
  212 + if (i2c_read(CONFIG_SYS_I2C_NCT72_ADDR, 0xFE, 1, &id2, 1) < 0)
  213 + printf("Error reading i2c NCT72 information!\n");
  214 + else
  215 + printf("NCT72(0x%x): ready\n", id2);
  216 +
  217 + kval = getenv("kernelargs");
  218 +
  219 + mmc = find_mmc_device(0);
  220 + if (mmc)
  221 + if (!mmc_init(mmc)) {
  222 + printf("MMC/SD card detected\n");
  223 + if (kval) {
  224 + int n = strlen(defkargs);
  225 + char *tmp = strstr(kval, defkargs);
  226 +
  227 + *tmp = 0;
  228 + strcpy(newkernelargs, kval);
  229 + strcat(newkernelargs, " ");
  230 + strcat(newkernelargs, mmckargs);
  231 + strcat(newkernelargs, " ");
  232 + strcat(newkernelargs, &tmp[n]);
  233 + setenv("kernelargs", newkernelargs);
  234 + } else {
  235 + setenv("kernelargs", mmckargs);
  236 + }
  237 + }
  238 + get_arc_info();
  239 +
  240 + if (kval) {
  241 + sval = getenv("SERIAL");
  242 + if (sval) {
  243 + strcpy(newkernelargs, "SN=");
  244 + strcat(newkernelargs, sval);
  245 + strcat(newkernelargs, " ");
  246 + strcat(newkernelargs, kval);
  247 + setenv("kernelargs", newkernelargs);
  248 + }
  249 + } else {
  250 + printf("Error reading kernelargs env variable!\n");
  251 + }
  252 +
  253 + return 0;
  254 +}
  255 +
  256 +int board_eth_init(bd_t *bis)
  257 +{
  258 + struct fsl_pq_mdio_info mdio_info;
  259 + struct tsec_info_struct tsec_info[4];
  260 +#ifdef CONFIG_TSEC2
  261 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  262 +#endif
  263 + int num = 0;
  264 +
  265 +#ifdef CONFIG_TSEC1
  266 + SET_STD_TSEC_INFO(tsec_info[num], 1);
  267 + num++;
  268 +#endif
  269 +#ifdef CONFIG_TSEC2
  270 + SET_STD_TSEC_INFO(tsec_info[num], 2);
  271 + if (is_serdes_configured(SGMII_TSEC2)) {
  272 + if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_SGMII2_DIS)) {
  273 + puts("eTSEC2 is in sgmii mode.\n");
  274 + tsec_info[num].flags |= TSEC_SGMII;
  275 + tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
  276 + }
  277 + }
  278 + num++;
  279 +#endif
  280 +#ifdef CONFIG_TSEC3
  281 + SET_STD_TSEC_INFO(tsec_info[num], 3);
  282 + num++;
  283 +#endif
  284 +
  285 + if (!num) {
  286 + printf("No TSECs initialized\n");
  287 + return 0;
  288 + }
  289 +
  290 + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  291 + mdio_info.name = DEFAULT_MII_NAME;
  292 +
  293 + fsl_pq_mdio_init(bis, &mdio_info);
  294 +
  295 + tsec_eth_init(bis, tsec_info, num);
  296 +
  297 + return pci_eth_init(bis);
  298 +}
  299 +
  300 +#ifdef CONFIG_OF_BOARD_SETUP
  301 +int ft_board_setup(void *blob, bd_t *bd)
  302 +{
  303 + phys_addr_t base;
  304 + phys_size_t size;
  305 + const char *soc_usb_compat = "fsl-usb2-dr";
  306 + int err, usb1_off, usb2_off;
  307 +
  308 + ft_cpu_setup(blob, bd);
  309 +
  310 + base = getenv_bootm_low();
  311 + size = getenv_bootm_size();
  312 +
  313 + fdt_fixup_memory(blob, (u64)base, (u64)size);
  314 +
  315 + FT_FSL_PCI_SETUP;
  316 +
  317 +#if defined(CONFIG_HAS_FSL_DR_USB)
  318 + fdt_fixup_dr_usb(blob, bd);
  319 +#endif
  320 +
  321 +#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  322 + /* Delete eLBC node as it is muxed with USB2 controller */
  323 + if (hwconfig("usb2")) {
  324 + const char *soc_elbc_compat = "fsl,p1020-elbc";
  325 + int off = fdt_node_offset_by_compatible(blob, -1,
  326 + soc_elbc_compat);
  327 + if (off < 0) {
  328 + printf
  329 + ("WARNING: could not find compatible node %s: %s\n",
  330 + soc_elbc_compat, fdt_strerror(off));
  331 + return off;
  332 + }
  333 + err = fdt_del_node(blob, off);
  334 + if (err < 0) {
  335 + printf("WARNING: could not remove %s: %s\n",
  336 + soc_elbc_compat, fdt_strerror(err));
  337 + }
  338 + return err;
  339 + }
  340 +#endif
  341 +
  342 +/* Delete USB2 node as it is muxed with eLBC */
  343 + usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat);
  344 + if (usb1_off < 0) {
  345 + printf("WARNING: could not find compatible node %s: %s.\n",
  346 + soc_usb_compat, fdt_strerror(usb1_off));
  347 + return usb1_off;
  348 + }
  349 + usb2_off =
  350 + fdt_node_offset_by_compatible(blob, usb1_off, soc_usb_compat);
  351 + if (usb2_off < 0) {
  352 + printf("WARNING: could not find compatible node %s: %s.\n",
  353 + soc_usb_compat, fdt_strerror(usb2_off));
  354 + return usb2_off;
  355 + }
  356 + err = fdt_del_node(blob, usb2_off);
  357 + if (err < 0) {
  358 + printf("WARNING: could not remove %s: %s.\n",
  359 + soc_usb_compat, fdt_strerror(err));
  360 + }
  361 + return 0;
  362 +}
  363 +#endif
board/Arcturus/ucp1020/ucp1020.h
Diff comments   View file @ d81572c
  1 +/*
  2 + * Copyright 2013-2015 Arcturus Networks, Inc.
  3 + * http://www.arcturusnetworks.com/products/ucp1020/
  4 + * by Oleksandr G Zhadan et al.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __UCP1020_H__
  10 +#define __UCP1020_H__
  11 +
  12 +#define GPIO0 31
  13 +#define GPIO1 30
  14 +#define GPIO2 29
  15 +#define GPIO3 28
  16 +#define GPIO4 27
  17 +#define GPIO5 26
  18 +#define GPIO6 25
  19 +#define GPIO7 24
  20 +#define GPIO8 23
  21 +#define GPIO9 22
  22 +#define GPIO10 21
  23 +#define GPIO11 20
  24 +#define GPIO12 19
  25 +#define GPIO13 18
  26 +#define GPIO14 17
  27 +#define GPIO15 16
  28 +#define GPIO_MAX_NUM 16
  29 +
  30 +#define GPIO_SDHC_CD GPIO8
  31 +#define GPIO_SDHC_WP GPIO9
  32 +#define GPIO_USB_PCTL0 GPIO10
  33 +#define GPIO_PCIE1_EN GPIO11
  34 +#define GPIO_PCIE2_EN GPIO10
  35 +#define GPIO_USB_PCTL1 GPIO11
  36 +
  37 +#define GPIO_WD GPIO15
  38 +
  39 +static char *defkargs = "root=/dev/mtdblock1 rootfstype=cramfs ro";
  40 +static char *mmckargs = "root=/dev/mmcblk0p1 rootwait rw";
  41 +
  42 +int get_arc_info(void);
  43 +
  44 +#endif
board/freescale/common/mpc85xx_sleep.c
Diff comments   View file @ d81572c
... ... @@ -43,16 +43,16 @@
43 43 */
44 44 static void dp_ddr_restore(void)
45 45 {
46   - volatile u64 *src, *dst;
  46 + u64 *src, *dst;
47 47 int i;
48 48 struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG;
49 49  
50 50 /* get the address of ddr date from SPARECR3 */
51   - src = (u64 *)in_be32(&scfg->sparecr[2]);
52   - dst = (u64 *)CONFIG_SYS_SDRAM_BASE;
  51 + src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8);
  52 + dst = (u64 *)(CONFIG_SYS_SDRAM_BASE + DDR_BUFF_LEN - 8);
53 53  
54 54 for (i = 0; i < DDR_BUFF_LEN / 8; i++)
55   - *dst++ = *src++;
  55 + *dst-- = *src--;
56 56  
57 57 flush_dcache();
58 58 }
board/freescale/common/qixis.h
Diff comments   View file @ d81572c
... ... @@ -115,5 +115,19 @@
115 115 qixis_write_i2c(offsetof(struct qixis, reg), value)
116 116 #endif
117 117  
  118 +/* Use for SDHC adapter card type identification and operation */
  119 +#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
  120 +#define QIXIS_SDID_MASK 0x07
  121 +#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC45 0x1 /* eMMC Card Rev4.5 */
  122 +#define QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY 0x2 /* SD/MMC Legacy Card */
  123 +#define QIXIS_ESDHC_ADAPTER_TYPE_EMMC44 0x3 /* eMMC Card Rev4.4 */
  124 +#define QIXIS_ESDHC_ADAPTER_TYPE_RSV 0x4 /* Reserved */
  125 +#define QIXIS_ESDHC_ADAPTER_TYPE_MMC 0x5 /* MMC Card */
  126 +#define QIXIS_ESDHC_ADAPTER_TYPE_SD 0x6 /* SD Card Rev2.0 3.0 */
  127 +#define QIXIS_ESDHC_NO_ADAPTER 0x7 /* No Card is Present*/
  128 +#define QIXIS_SDCLKIN 0x08
  129 +#define QIXIS_SDCLKOUT 0x02
  130 +#endif
  131 +
118 132 #endif
board/freescale/t102xqds/eth_t102xqds.c
Diff comments   View file @ d81572c
... ... @@ -172,8 +172,8 @@
172 172 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_RGMII) {
173 173 if (port == FM1_DTSEC3) {
174 174 fdt_set_phy_handle(fdt, compat, addr, "rgmii_phy2");
175   - fdt_setprop(fdt, offset, "phy-connection-type",
176   - "rgmii", 5);
  175 + fdt_setprop_string(fdt, offset, "phy-connection-type",
  176 + "rgmii");
177 177 fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
178 178 }
179 179 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
... ... @@ -207,7 +207,8 @@
207 207 break;
208 208 }
209 209 fdt_delprop(fdt, offset, "phy-connection-type");
210   - fdt_setprop(fdt, offset, "phy-connection-type", "qsgmii", 6);
  210 + fdt_setprop_string(fdt, offset, "phy-connection-type",
  211 + "qsgmii");
211 212 fdt_status_okay_by_alias(fdt, "emi1_slot2");
212 213 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
213 214 /* XFI interface */
... ... @@ -219,7 +220,7 @@
219 220 /* no PHY for XFI */
220 221 fdt_delprop(fdt, offset, "phy-handle");
221 222 fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
222   - fdt_setprop(fdt, offset, "phy-connection-type", "xgmii", 5);
  223 + fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
223 224 }
224 225 }
225 226  
board/freescale/t102xrdb/MAINTAINERS
Diff comments   View file @ d81572c
... ... @@ -8,4 +8,9 @@
8 8 F: configs/T1024RDB_SDCARD_defconfig
9 9 F: configs/T1024RDB_SPIFLASH_defconfig
10 10 F: configs/T1024RDB_SECURE_BOOT_defconfig
  11 +F: configs/T1023RDB_defconfig
  12 +F: configs/T1023RDB_NAND_defconfig
  13 +F: configs/T1023RDB_SDCARD_defconfig
  14 +F: configs/T1023RDB_SPIFLASH_defconfig
  15 +F: configs/T1023RDB_SECURE_BOOT_defconfig
board/freescale/t102xrdb/Makefile
Diff comments   View file @ d81572c
... ... @@ -8,7 +8,7 @@
8 8 obj-y += spl.o
9 9 else
10 10 obj-y += t102xrdb.o
11   -obj-y += cpld.o
  11 +obj-$(CONFIG_T1024RDB) += cpld.o
12 12 obj-y += eth_t102xrdb.o
13 13 obj-$(CONFIG_PCI) += pci.o
14 14 endif
board/freescale/t102xrdb/README
Diff comments   View file @ d81572c
... ... @@ -98,6 +98,30 @@
98 98 - Four I2C ports
99 99  
100 100  
  101 +T1023RDB board Overview
  102 +-----------------------
  103 +- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
  104 +- CoreNet fabric supporting coherent and noncoherent transactions with
  105 + prioritization and bandwidth allocation
  106 +- SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 w/o ECC
  107 +- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
  108 +- Ethernet interfaces:
  109 + - one 1G RGMII port on-board(RTL8211FS PHY)
  110 + - one 1G SGMII port on-board(RTL8211FS PHY)
  111 + - one 2.5G SGMII port on-board(AQR105 PHY)
  112 +- PCIe: Two Mini-PCIe connectors on-board.
  113 +- SerDes: 4 lanes up to 10.3125GHz
  114 +- NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash
  115 +- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
  116 +- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash.
  117 +- USB: one Type-A USB 2.0 port with internal PHY
  118 +- eSDHC: support SD/MMC and eMMC card
  119 +- 256Kbit M24256 I2C EEPROM
  120 +- RTC: Real-time clock DS1339U on I2C bus
  121 +- UART: one serial port on-board with RJ45 connector
  122 +- Debugging: JTAG/COP for T1023 debugging
  123 +
  124 +
101 125 Memory map on T1024RDB
102 126 ----------------------
103 127 Start Address End Address Description Size
104 128  
105 129  
106 130  
107 131  
108 132  
... ... @@ -117,29 +141,39 @@
117 141 0x0_0000_0000 0x0_ffff_ffff DDR 4GB
118 142  
119 143  
120   -128MB NOR Flash memory Map
121   ---------------------------
  144 +128MB NOR Flash Memory Layout
  145 +-----------------------------
122 146 Start Address End Address Definition Max size
123 147 0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
124 148 0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
125 149 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
126 150 0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB
127   -0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
  151 +0xED300000 0xEFDFFFFF rootfs (alt bank) 44MB
  152 +0xED000000 0xED2FFFFF Guest image #3 (alternate bank) 3MB
  153 +0xECD00000 0xECFFFFFF Guest image #2 (alternate bank) 3MB
  154 +0xECA00000 0xECCFFFFF Guest image #1 (alternate bank) 3MB
  155 +0xEC900000 0xEC9FFFFF HV config device tree(alt bank) 1MB
128 156 0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
129   -0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
  157 +0xEC700000 0xEC7FFFFF HV.uImage (alternate bank) 1MB
  158 +0xEC020000 0xEC6FFFFF Linux.uImage (alt bank) ~7MB
130 159 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
131 160 0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
132 161 0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
133 162 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
134 163 0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB
135   -0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
  164 +0xE9300000 0xEBDFFFFF rootfs (current bank) 44MB
  165 +0xE9000000 0xE92FFFFF Guest image #3 (current bank) 3MB
  166 +0xE8D00000 0xE8FFFFFF Guest image #2 (current bank) 3MB
  167 +0xE8A00000 0xE8CFFFFF Guest image #1 (current bank) 3MB
  168 +0xE8900000 0xE89FFFFF HV config device tree(cur bank) 1MB
136 169 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
137   -0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
  170 +0xE8700000 0xE87FFFFF HV.uImage (current bank) 1MB
  171 +0xE8020000 0xE86FFFFF Linux.uImage (current bank) ~7MB
138 172 0xE8000000 0xE801FFFF RCW (current bank) 128KB
139 173  
140 174  
141   -T1024 Clock frequency
142   ----------------------
  175 +T1024/T1023 Clock frequency
  176 +---------------------------
143 177 BIN Core DDR Platform FMan
144 178 Bin1: 1400MHz 1600MT/s 400MHz 700MHz
145 179 Bin2: 1200MHz 1600MT/s 400MHz 600MHz
146 180  
147 181  
... ... @@ -155,16 +189,27 @@
155 189 b. program u-boot.bin image to NOR flash
156 190 => tftp 1000000 u-boot.bin
157 191 => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
158   - set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
  192 + on T1024RDB:
  193 + set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
  194 + on T1023RDB:
  195 + set SW1[1:8] = '00010110', SW2[1] = '0', SW3[4] = '0' for NOR boot
159 196  
160 197 Switching between default bank0 and alternate bank4 on NOR flash
161 198 To change boot source to vbank4:
162   - via software: run command 'cpld reset altbank' in u-boot.
163   - via DIP-switch: set SW3[5:7] = '100'
  199 + on T1024RDB:
  200 + via software: run command 'cpld reset altbank' in u-boot.
  201 + via DIP-switch: set SW3[5:7] = '100'
  202 + on T1023RDB:
  203 + via software: run command 'gpio vbank4' in u-boot.
  204 + via DIP-switch: set SW3[5:7] = '100'
164 205  
165 206 To change boot source to vbank0:
166   - via software: run command 'cpld reset' in u-boot.
167   - via DIP-Switch: set SW3[5:7] = '000'
  207 + on T1024RDB:
  208 + via software: run command 'cpld reset' in u-boot.
  209 + via DIP-Switch: set SW3[5:7] = '000'
  210 + on T1023RDB:
  211 + via software: run command 'gpio vbank0' in u-boot.
  212 + via DIP-switch: set SW3[5:7] = '000'
168 213  
169 214 2. NAND Boot:
170 215 a. build PBL image for NAND boot
171 216  
... ... @@ -183,8 +228,11 @@
183 228 b. program u-boot-with-spl-pbl.bin to SPI flash
184 229 => tftp 1000000 u-boot-with-spl-pbl.bin
185 230 => sf probe 0
186   - => sf erase 0 f0000
  231 + => sf erase 0 100000
187 232 => sf write 1000000 0 $filesize
  233 + => tftp 1000000 fsl_fman_ucode_t1024_xx.bin
  234 + => sf erase 100000 100000
  235 + => sf write 1000000 110000 20000
188 236 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
189 237  
190 238 4. SD Boot:
191 239  
192 240  
193 241  
194 242  
... ... @@ -236,24 +284,35 @@
236 284 0x200000 0x27FFFF QE Firmware 512KB(1 block)
237 285  
238 286  
  287 +NAND Flash memory Map on T1023RDB
  288 +----------------------------------------------------
  289 +Start End Definition Size
  290 +0x000000 0x0FFFFF u-boot 1MB
  291 +0x100000 0x15FFFF u-boot env 8KB
  292 +0x160000 0x17FFFF FMAN Ucode 128KB
  293 +
  294 +
239 295 SD Card memory Map on T1024RDB
240 296 ----------------------------------------------------
241 297 Block #blocks Definition Size
242 298 0x008 2048 u-boot img 1MB
243 299 0x800 0016 u-boot env 8KB
244 300 0x820 0256 FMAN Ucode 128KB
245   -0x920 0256 QE Firmware 128KB
  301 +0x920 0256 QE Firmware 128KB(only T1024RDB)
246 302  
247 303  
248   -SPI Flash memory Map on T1024RDB
  304 +64MB SPI Flash memory Map on T102xRDB
249 305 ----------------------------------------------------
250 306 Start End Definition Size
251 307 0x000000 0x0FFFFF u-boot img 1MB
252 308 0x100000 0x101FFF u-boot env 8KB
253 309 0x110000 0x12FFFF FMAN Ucode 128KB
254   -0x130000 0x14FFFF QE Firmware 128KB
  310 +0x130000 0x14FFFF QE Firmware 128KB(only T1024RDB)
  311 +0x300000 0x3FFFFF device tree 128KB
  312 +0x400000 0x9FFFFF Linux kernel 6MB
  313 +0xa00000 0x3FFFFFF rootfs 54MB
255 314  
256 315  
257   -For more details, please refer to T1024RDB Reference Manual and access
258   -website www.freescale.com and Freescale QorIQ SDK Infocenter document.
  316 +For more details, please refer to T1024RDB Reference Manual
  317 +and Freescale QorIQ SDK Infocenter document.
board/freescale/t102xrdb/ddr.c
Diff comments   View file @ d81572c
... ... @@ -135,8 +135,83 @@
135 135 /* for DDR bus 32bit test on T1024 */
136 136 popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
137 137 #endif
  138 +
  139 +#ifdef CONFIG_T1023RDB
  140 + popts->wrlvl_ctl_2 = 0x07070606;
  141 + popts->half_strength_driver_enable = 1;
  142 +#endif
138 143 }
139 144  
  145 +#ifdef CONFIG_SYS_DDR_RAW_TIMING
  146 +/* 2GB discrete DDR4 MT40A512M8HX on T1023RDB */
  147 +dimm_params_t ddr_raw_timing = {
  148 + .n_ranks = 1,
  149 + .rank_density = 0x80000000,
  150 + .capacity = 0x80000000,
  151 + .primary_sdram_width = 32,
  152 + .ec_sdram_width = 8,
  153 + .registered_dimm = 0,
  154 + .mirrored_dimm = 0,
  155 + .n_row_addr = 15,
  156 + .n_col_addr = 10,
  157 + .bank_addr_bits = 2,
  158 + .bank_group_bits = 2,
  159 + .edc_config = 0,
  160 + .burst_lengths_bitmask = 0x0c,
  161 + .tckmin_x_ps = 938,
  162 + .tckmax_ps = 1500,
  163 + .caslat_x = 0x000DFA00,
  164 + .taa_ps = 13500,
  165 + .trcd_ps = 13500,
  166 + .trp_ps = 13500,
  167 + .tras_ps = 33000,
  168 + .trc_ps = 46500,
  169 + .trfc1_ps = 260000,
  170 + .trfc2_ps = 160000,
  171 + .trfc4_ps = 110000,
  172 + .tfaw_ps = 25000,
  173 + .trrds_ps = 3700,
  174 + .trrdl_ps = 5300,
  175 + .tccdl_ps = 5355,
  176 + .refresh_rate_ps = 7800000,
  177 + .dq_mapping[0] = 0x0,
  178 + .dq_mapping[1] = 0x0,
  179 + .dq_mapping[2] = 0x0,
  180 + .dq_mapping[3] = 0x0,
  181 + .dq_mapping[4] = 0x0,
  182 + .dq_mapping[5] = 0x0,
  183 + .dq_mapping[6] = 0x0,
  184 + .dq_mapping[7] = 0x0,
  185 + .dq_mapping[8] = 0x0,
  186 + .dq_mapping[9] = 0x0,
  187 + .dq_mapping[10] = 0x0,
  188 + .dq_mapping[11] = 0x0,
  189 + .dq_mapping[12] = 0x0,
  190 + .dq_mapping[13] = 0x0,
  191 + .dq_mapping[14] = 0x0,
  192 + .dq_mapping[15] = 0x0,
  193 + .dq_mapping[16] = 0x0,
  194 + .dq_mapping[17] = 0x0,
  195 + .dq_mapping_ors = 1,
  196 +};
  197 +
  198 +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  199 + unsigned int controller_number,
  200 + unsigned int dimm_number)
  201 +{
  202 + const char dimm_model[] = "Fixed DDR4 on board";
  203 +
  204 + if (((controller_number == 0) && (dimm_number == 0)) ||
  205 + ((controller_number == 1) && (dimm_number == 0))) {
  206 + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  207 + memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  208 + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  209 + }
  210 +
  211 + return 0;
  212 +}
  213 +#endif
  214 +
140 215 #if defined(CONFIG_DEEP_SLEEP)
141 216 void board_mem_sleep_setup(void)
142 217 {
143 218  
... ... @@ -155,8 +230,9 @@
155 230 phys_size_t dram_size;
156 231  
157 232 #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
  233 +#ifndef CONFIG_SYS_DDR_RAW_TIMING
158 234 puts("Initializing....using SPD\n");
159   -
  235 +#endif
160 236 dram_size = fsl_ddr_sdram();
161 237 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
162 238 dram_size *= 0x100000;
board/freescale/t102xrdb/eth_t102xrdb.c
Diff comments   View file @ d81572c
1 1 /*
2 2 * Copyright 2014 Freescale Semiconductor, Inc.
3 3 *
  4 + * Shengzhou Liu <Shengzhou.Liu@freescale.com>
  5 + *
4 6 * SPDX-License-Identifier: GPL-2.0+
5 7 */
6 8  
... ... @@ -56,6 +58,7 @@
56 58 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
57 59  
58 60 switch (srds_s1) {
  61 +#ifdef CONFIG_T1024RDB
59 62 case 0x95:
60 63 /* set the on-board RGMII2 PHY */
61 64 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
62 65  
... ... @@ -63,10 +66,17 @@
63 66 /* set 10G XFI with Aquantia AQR105 PHY */
64 67 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
65 68 break;
  69 +#endif
  70 + case 0x6a:
  71 + case 0x6b:
66 72 case 0x77:
67 73 case 0x135:
68 74 /* set the on-board 2.5G SGMII AQR105 PHY */
69   - fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY1_ADDR);
  75 + fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
  76 +#ifdef CONFIG_T1023RDB
  77 + /* set the on-board 1G SGMII RTL8211F PHY */
  78 + fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
  79 +#endif
70 80 break;
71 81 default:
72 82 printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
... ... @@ -81,6 +91,14 @@
81 91 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
82 92 fm_info_set_mdio(i, dev);
83 93 break;
  94 + case PHY_INTERFACE_MODE_SGMII:
  95 +#if defined(CONFIG_T1023RDB)
  96 + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
  97 +#elif defined(CONFIG_T1024RDB)
  98 + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
  99 +#endif
  100 + fm_info_set_mdio(i, dev);
  101 + break;
84 102 case PHY_INTERFACE_MODE_SGMII_2500:
85 103 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
86 104 fm_info_set_mdio(i, dev);
87 105  
88 106  
... ... @@ -110,13 +128,16 @@
110 128 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
111 129 enum fm_port port, int offset)
112 130 {
113   - if ((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) &&
114   - (port == FM1_DTSEC3)) {
  131 +#if defined(CONFIG_T1024RDB)
  132 + if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
  133 + (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
  134 + (port == FM1_DTSEC3)) {
115 135 fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
116   - fdt_setprop(fdt, offset, "phy-connection-type",
117   - "sgmii-2500", 10);
  136 + fdt_setprop_string(fdt, offset, "phy-connection-type",
  137 + "sgmii-2500");
118 138 fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
119 139 }
  140 +#endif
120 141 }
121 142  
122 143 void fdt_fixup_board_enet(void *fdt)
board/freescale/t102xrdb/t1023_rcw.cfg
Diff comments   View file @ d81572c
  1 +#PBL preamble and RCW header for T1023RDB
  2 +aa55aa55 010e0100
  3 +#SerDes Protocol: 0x77
  4 +#Core/DDR: 1400Mhz/1600MT/s with single source clock
  5 +0810000e 00000000 00000000 00000000
  6 +3b800003 00000012 e8104000 21000000
  7 +00000000 00000000 00000000 00020800
  8 +00000130 04020200 00000000 00000006
board/freescale/t102xrdb/t102xrdb.c
Diff comments   View file @ d81572c
... ... @@ -18,11 +18,25 @@
18 18 #include <asm/fsl_liodn.h>
19 19 #include <fm_eth.h>
20 20 #include "t102xrdb.h"
  21 +#ifdef CONFIG_T1024RDB
21 22 #include "cpld.h"
  23 +#endif
22 24 #include "../common/sleep.h"
23 25  
24 26 DECLARE_GLOBAL_DATA_PTR;
25 27  
  28 +#ifdef CONFIG_T1023RDB
  29 +enum {
  30 + GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: EMMC, 1:SD/MMC */
  31 + GPIO1_EMMC_SEL,
  32 + GPIO1_VBANK0,
  33 + GPIO1_VBANK4 = 0x00008000, /* GPIO1_16/20/22, 100:vBank4 */
  34 + GPIO1_VBANK_MASK = 0x00008a00,
  35 + GPIO1_DIR_OUTPUT = 0x00028a00,
  36 + GPIO1_GET_VAL,
  37 +};
  38 +#endif
  39 +
26 40 int checkboard(void)
27 41 {
28 42 struct cpu_type *cpu = gd->arch.cpu;
29 43  
30 44  
... ... @@ -34,14 +48,17 @@
34 48 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
35 49  
36 50 printf("Board: %sRDB, ", cpu->name);
37   - printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
  51 +#ifdef CONFIG_T1024RDB
  52 + printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
38 53 CPLD_READ(hw_ver), CPLD_READ(sw_ver));
  54 +#endif
  55 + printf("boot from ");
39 56  
40 57 #ifdef CONFIG_SDCARD
41 58 puts("SD/MMC\n");
42 59 #elif CONFIG_SPIFLASH
43 60 puts("SPI\n");
44   -#else
  61 +#elif defined(CONFIG_T1024RDB)
45 62 u8 reg;
46 63  
47 64 reg = CPLD_READ(flash_csr);
48 65  
49 66  
50 67  
... ... @@ -52,17 +69,25 @@
52 69 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
53 70 printf("NOR vBank%d\n", reg);
54 71 }
  72 +#elif defined(CONFIG_T1023RDB)
  73 +#ifdef CONFIG_NAND
  74 + puts("NAND\n");
  75 +#else
  76 + printf("NOR vBank%d\n", (t1023rdb_gpio_ctrl(GPIO1_GET_VAL) &
  77 + GPIO1_VBANK4) >> 15 ? 4 : 0);
55 78 #endif
  79 +#endif
56 80  
57 81 puts("SERDES Reference Clocks:\n");
58 82 if (srds_s1 == 0x95)
59 83 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
60 84 else
61   - printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[0]);
  85 + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);
62 86  
63 87 return 0;
64 88 }
65 89  
  90 +#ifdef CONFIG_T1024RDB
66 91 static void board_mux_lane(void)
67 92 {
68 93 ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
... ... @@ -82,6 +107,7 @@
82 107 }
83 108 CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
84 109 }
  110 +#endif
85 111  
86 112 int board_early_init_f(void)
87 113 {
88 114  
... ... @@ -124,7 +150,9 @@
124 150 #ifdef CONFIG_SYS_DPAA_QBMAN
125 151 setup_portals();
126 152 #endif
  153 +#ifdef CONFIG_T1024RDB
127 154 board_mux_lane();
  155 +#endif
128 156  
129 157 return 0;
130 158 }
... ... @@ -170,4 +198,63 @@
170 198  
171 199 return 0;
172 200 }
  201 +
  202 +
  203 +#ifdef CONFIG_T1023RDB
  204 +static u32 t1023rdb_gpio_ctrl(u32 ctrl_type)
  205 +{
  206 + ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  207 + u32 gpioval;
  208 +
  209 + setbits_be32(&pgpio->gpdir, GPIO1_DIR_OUTPUT);
  210 + gpioval = in_be32(&pgpio->gpdat);
  211 +
  212 + switch (ctrl_type) {
  213 + case GPIO1_SD_SEL:
  214 + gpioval |= GPIO1_SD_SEL;
  215 + break;
  216 + case GPIO1_EMMC_SEL:
  217 + gpioval &= ~GPIO1_SD_SEL;
  218 + break;
  219 + case GPIO1_VBANK0:
  220 + gpioval &= ~GPIO1_VBANK_MASK;
  221 + break;
  222 + case GPIO1_VBANK4:
  223 + gpioval &= ~GPIO1_VBANK_MASK;
  224 + gpioval |= GPIO1_VBANK4;
  225 + break;
  226 + case GPIO1_GET_VAL:
  227 + return gpioval;
  228 + default:
  229 + break;
  230 + }
  231 + out_be32(&pgpio->gpdat, gpioval);
  232 +
  233 + return 0;
  234 +}
  235 +
  236 +static int gpio_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
  237 + char * const argv[])
  238 +{
  239 + if (argc < 2)
  240 + return CMD_RET_USAGE;
  241 + if (!strcmp(argv[1], "vbank0"))
  242 + t1023rdb_gpio_ctrl(GPIO1_VBANK0);
  243 + else if (!strcmp(argv[1], "vbank4"))
  244 + t1023rdb_gpio_ctrl(GPIO1_VBANK4);
  245 + else if (!strcmp(argv[1], "sd"))
  246 + t1023rdb_gpio_ctrl(GPIO1_SD_SEL);
  247 + else if (!strcmp(argv[1], "EMMC"))
  248 + t1023rdb_gpio_ctrl(GPIO1_EMMC_SEL);
  249 + else
  250 + return CMD_RET_USAGE;
  251 + return 0;
  252 +}
  253 +
  254 +U_BOOT_CMD(
  255 + gpio, 2, 0, gpio_cmd,
  256 + "for vbank0/vbank4/SD/eMMC switch control in runtime",
  257 + "command (e.g. gpio vbank4)"
  258 +);
  259 +#endif
board/freescale/t102xrdb/t102xrdb.h
Diff comments   View file @ d81572c
... ... @@ -9,6 +9,8 @@
9 9  
10 10 void fdt_fixup_board_enet(void *blob);
11 11 void pci_of_setup(void *blob, bd_t *bd);
12   -
  12 +#ifdef CONFIG_T1023RDB
  13 +static u32 t1023rdb_gpio_ctrl(u32 ctrl_type);
  14 +#endif
13 15 #endif
board/freescale/t208xrdb/cpld.h
Diff comments   View file @ d81572c
... ... @@ -40,4 +40,7 @@
40 40 #define CPLD_LBMAP_RESET 0xFF
41 41 #define CPLD_LBMAP_SHIFT 0x03
42 42 #define CPLD_BOOT_SEL 0x80
  43 +
  44 +/* RSTCON Register */
  45 +#define CPLD_RSTCON_EDC_RST 0x04
board/freescale/t208xrdb/t2080_rcw.cfg
Diff comments   View file @ d81572c
... ... @@ -10,7 +10,10 @@
10 10  
11 11 #For T2080 v1.1
12 12 #SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
13   -1206001b 15000000 00000000 00000000
  13 +#1206001b 15000000 00000000 00000000
  14 +
  15 +#SerDes=0x66_0x15, Core:1800MHz, DDR:1867MT/s
  16 +1207001b 15000000 00000000 00000000
14 17 66150002 00000000 e8104000 c1000000
15 18 00800000 00000000 00000000 000307fc
16 19 00000000 00000000 00000000 00000004
board/freescale/t208xrdb/t208xrdb.c
Diff comments   View file @ d81572c
... ... @@ -107,6 +107,13 @@
107 107  
108 108 int misc_init_r(void)
109 109 {
  110 + u8 reg;
  111 +
  112 + /* Reset CS4315 PHY */
  113 + reg = CPLD_READ(reset_ctl);
  114 + reg |= CPLD_RSTCON_EDC_RST;
  115 + CPLD_WRITE(reset_ctl, reg);
  116 +
110 117 return 0;
111 118 }
112 119  
board/freescale/t4qds/Kconfig
Diff comments   View file @ d81572c
1   -if TARGET_T4240EMU
2   -
3   -config SYS_BOARD
4   - default "t4qds"
5   -
6   -config SYS_VENDOR
7   - default "freescale"
8   -
9   -config SYS_CONFIG_NAME
10   - default "T4240EMU"
11   -
12   -endif
13   -
14 1 if TARGET_T4240QDS
15 2  
16 3 config SYS_BOARD
board/freescale/t4qds/MAINTAINERS
Diff comments   View file @ d81572c
1 1 T4QDS BOARD
2   -#M: -
  2 +M: Shaohui Xie <Shaohui.Xie@freescale.com>
3 3 S: Maintained
4 4 F: board/freescale/t4qds/
5 5 F: include/configs/T4240QDS.h
6 6 F: configs/T4160QDS_defconfig
7 7 F: configs/T4160QDS_NAND_defconfig
8 8 F: configs/T4160QDS_SDCARD_defconfig
9   -F: configs/T4160QDS_SPIFLASH_defconfig
10 9 F: configs/T4240QDS_defconfig
11 10 F: configs/T4240QDS_NAND_defconfig
12 11 F: configs/T4240QDS_SDCARD_defconfig
13   -F: configs/T4240QDS_SPIFLASH_defconfig
14 12 F: configs/T4240QDS_SRIO_PCIE_BOOT_defconfig
15 13  
16 14 T4160QDS_SECURE_BOOT BOARD
... ... @@ -18,10 +16,4 @@
18 16 S: Maintained
19 17 F: configs/T4160QDS_SECURE_BOOT_defconfig
20 18 F: configs/T4240QDS_SECURE_BOOT_defconfig
21   -
22   -T4240EMU BOARD
23   -M: York Sun <yorksun@freescale.com>
24   -S: Maintained
25   -F: include/configs/T4240EMU.h
26   -F: configs/T4240EMU_defconfig
board/freescale/t4qds/Makefile
Diff comments   View file @ d81572c
... ... @@ -8,7 +8,6 @@
8 8 obj-y += spl.o
9 9 else
10 10 obj-$(CONFIG_T4240QDS) += t4240qds.o
11   -obj-$(CONFIG_T4240EMU) += t4240emu.o
12 11 obj-$(CONFIG_T4240QDS)+= eth.o
13 12 obj-$(CONFIG_PCI) += pci.o
14 13 endif
board/freescale/t4qds/ddr.h
Diff comments   View file @ d81572c
... ... @@ -25,7 +25,6 @@
25 25 * for each n_ranks group.
26 26 */
27 27  
28   -#ifdef CONFIG_T4240QDS
29 28 static const struct board_specific_parameters udimm0[] = {
30 29 /*
31 30 * memory controller 0
... ... @@ -62,31 +61,6 @@
62 61 {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
63 62 {}
64 63 };
65   -
66   -#else /* CONFIG_T4240EMU */
67   -static const struct board_specific_parameters udimm0[] = {
68   - /*
69   - * memory controller 0
70   - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
71   - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
72   - */
73   - {2, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0},
74   - {1, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0},
75   - {}
76   -};
77   -
78   -static const struct board_specific_parameters rdimm0[] = {
79   - /*
80   - * memory controller 0
81   - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
82   - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
83   - */
84   - {4, 2140, 0, 5, 8, 0x0, 0x0, 0xff, 2, 0},
85   - {2, 2140, 0, 5, 8, 0x0, 0x0, 0xff, 2, 0},
86   - {1, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0},
87   - {}
88   -};
89   -#endif /* CONFIG_T4240EMU */
90 64  
91 65 /*
92 66 * The three slots have slightly different timing. The center values are good
board/freescale/t4qds/t4_rcw.cfg
Diff comments   View file @ d81572c
1 1 #PBL preamble and RCW header
2 2 aa55aa55 010e0100
3 3 #serdes protocol 1_27_5_11
4   -16070019 18101916 00000000 00000000
  4 +1607001b 18101b16 00000000 00000000
5 5 04362858 30548c00 ec020000 f5000000
6 6 00000000 ee0000ee 00000000 000307fc
7 7 00000000 00000000 00000000 00000028
board/freescale/t4rdb/MAINTAINERS
Diff comments   View file @ d81572c
... ... @@ -5,4 +5,5 @@
5 5 F: include/configs/T4240RDB.h
6 6 F: configs/T4160RDB_defconfig
7 7 F: configs/T4240RDB_defconfig
  8 +F: configs/T4240RDB_SDCARD_defconfig
board/freescale/t4rdb/Makefile
Diff comments   View file @ d81572c
... ... @@ -4,11 +4,15 @@
4 4 # SPDX-License-Identifier: GPL-2.0+
5 5 #
6 6  
  7 +ifdef CONFIG_SPL_BUILD
  8 +obj-y += spl.o
  9 +else
7 10 obj-$(CONFIG_T4240RDB) += t4240rdb.o
8 11 obj-y += cpld.o
9   -obj-y += ddr.o
10 12 obj-y += eth.o
11 13 obj-$(CONFIG_PCI) += pci.o
  14 +endif
  15 +obj-y += ddr.o
12 16 obj-y += law.o
13 17 obj-y += tlb.o
board/freescale/t4rdb/ddr.c
Diff comments   View file @ d81572c
... ... @@ -108,12 +108,16 @@
108 108  
109 109 puts("Initializing....using SPD\n");
110 110  
  111 +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
111 112 dram_size = fsl_ddr_sdram();
112 113  
113 114 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
114 115 dram_size *= 0x100000;
  116 +#else
  117 + /* DDR has been initialised by first stage boot loader */
  118 + dram_size = fsl_ddr_sdram_size();
  119 +#endif
115 120  
116   - puts(" DDR: ");
117 121 return dram_size;
118 122 }
board/freescale/t4rdb/spl.c
Diff comments   View file @ d81572c
  1 +/*
  2 + * Copyright 2015 Freescale Semiconductor, Inc.
  3 + *
  4 + * Author: Chunhe Lan <Chunhe.Lan@freescale.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <asm/spl.h>
  11 +#include <malloc.h>
  12 +#include <ns16550.h>
  13 +#include <nand.h>
  14 +#include <mmc.h>
  15 +#include <fsl_esdhc.h>
  16 +#include <i2c.h>
  17 +
  18 +#include "t4rdb.h"
  19 +
  20 +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
  21 +
  22 +DECLARE_GLOBAL_DATA_PTR;
  23 +
  24 +phys_size_t get_effective_memsize(void)
  25 +{
  26 + return CONFIG_SYS_L3_SIZE;
  27 +}
  28 +
  29 +unsigned long get_board_sys_clk(void)
  30 +{
  31 + return CONFIG_SYS_CLK_FREQ;
  32 +}
  33 +
  34 +unsigned long get_board_ddr_clk(void)
  35 +{
  36 + return CONFIG_DDR_CLK_FREQ;
  37 +}
  38 +
  39 +void board_init_f(ulong bootflag)
  40 +{
  41 + u32 plat_ratio, sys_clk, ccb_clk;
  42 + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  43 +
  44 + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
  45 + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
  46 +
  47 + /* Update GD pointer */
  48 + gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
  49 +
  50 + /* compiler optimization barrier needed for GCC >= 3.4 */
  51 + __asm__ __volatile__("" : : : "memory");
  52 +
  53 + console_init_f();
  54 +
  55 + /* initialize selected port with appropriate baud rate */
  56 + sys_clk = get_board_sys_clk();
  57 + plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
  58 + ccb_clk = sys_clk * plat_ratio / 2;
  59 +
  60 + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  61 + ccb_clk / 16 / CONFIG_BAUDRATE);
  62 +
  63 + puts("\nSD boot...\n");
  64 +
  65 + relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
  66 +}
  67 +
  68 +void board_init_r(gd_t *gd, ulong dest_addr)
  69 +{
  70 + bd_t *bd;
  71 +
  72 + bd = (bd_t *)(gd + sizeof(gd_t));
  73 + memset(bd, 0, sizeof(bd_t));
  74 + gd->bd = bd;
  75 + bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
  76 + bd->bi_memsize = CONFIG_SYS_L3_SIZE;
  77 +
  78 + probecpu();
  79 + get_clocks();
  80 + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
  81 + CONFIG_SPL_RELOC_MALLOC_SIZE);
  82 +
  83 + mmc_initialize(bd);
  84 + mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  85 + (uchar *)CONFIG_ENV_ADDR);
  86 +
  87 + gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
  88 + gd->env_valid = 1;
  89 +
  90 + i2c_init_all();
  91 +
  92 + gd->ram_size = initdram(0);
  93 +
  94 + mmc_boot();
  95 +}
board/freescale/t4rdb/t4_pbi.cfg
Diff comments   View file @ d81572c
... ... @@ -19,9 +19,6 @@
19 19 09000d00 00000000
20 20 09000d04 fff80000
21 21 09000d08 81000012
22   -#slow mdio clock
23   -095fc030 00008148
24   -095fd030 00808148
25 22 #Configure alternate space
26 23 09000010 00000000
27 24 09000014 ff000000
board/freescale/t4rdb/t4_rcw.cfg
Diff comments   View file @ d81572c
... ... @@ -2,7 +2,7 @@
2 2 aa55aa55 010e0100
3 3 #serdes protocol 27_55_1_9
4 4 16070019 18101916 00000000 00000000
5   -6c6e0848 00448c00 6c020000 f5000000
6   -00000000 ee0000ee 00000000 000287fc
7   -00000000 50000000 00000000 00000028
  5 +6c6e0848 00448c00 ec020000 f5000000
  6 +00000000 ee0000ee 00000000 000307fc
  7 +00000000 00000000 00000000 00000028
board/freescale/t4rdb/tlb.c
Diff comments   View file @ d81572c
... ... @@ -51,6 +51,7 @@
51 51 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
52 52 0, 2, BOOKE_PAGESZ_256M, 1),
53 53  
  54 +#ifndef CONFIG_SPL_BUILD
54 55 /* *I*G* - PCI */
55 56 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
56 57 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
... ... @@ -91,6 +92,8 @@
91 92 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
92 93 0, 12, BOOKE_PAGESZ_16M, 1),
93 94 #endif
  95 +#endif
  96 +
94 97 #ifdef CONFIG_SYS_DCSRBAR_PHYS
95 98 SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
96 99 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
... ... @@ -110,6 +113,11 @@
110 113 SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
111 114 MAS3_SW|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
112 115 0, 17, BOOKE_PAGESZ_4K, 1),
  116 +#endif
  117 +#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
  118 + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
  119 + MAS3_SX|MAS3_SW|MAS3_SR, 0,
  120 + 0, 18, BOOKE_PAGESZ_2G, 1)
113 121 #endif
114 122 };
115 123  
configs/T1023RDB_NAND_defconfig
Diff comments   View file @ d81572c
  1 +CONFIG_SPL=y
  2 +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
  3 +CONFIG_PPC=y
  4 +CONFIG_MPC85xx=y
  5 +CONFIG_TARGET_T102XRDB=y
configs/T1023RDB_SDCARD_defconfig
Diff comments   View file @ d81572c
  1 +CONFIG_SPL=y
  2 +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
  3 +CONFIG_PPC=y
  4 +CONFIG_MPC85xx=y
  5 +CONFIG_TARGET_T102XRDB=y
configs/T1023RDB_SECURE_BOOT_defconfig
Diff comments   View file @ d81572c
  1 +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,SECURE_BOOT"
  2 +CONFIG_PPC=y
  3 +CONFIG_MPC85xx=y
  4 +CONFIG_TARGET_T102XRDB=y
configs/T1023RDB_SPIFLASH_defconfig
Diff comments   View file @ d81572c
  1 +CONFIG_SPL=y
  2 +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
  3 +CONFIG_PPC=y
  4 +CONFIG_MPC85xx=y
  5 +CONFIG_TARGET_T102XRDB=y
configs/T1023RDB_defconfig
Diff comments   View file @ d81572c
  1 +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB"
  2 +CONFIG_PPC=y
  3 +CONFIG_MPC85xx=y
  4 +CONFIG_TARGET_T102XRDB=y
configs/T1024RDB_NAND_defconfig
Diff comments   View file @ d81572c
1 1 CONFIG_SPL=y
2   -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
  2 +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
3 3 CONFIG_PPC=y
4 4 CONFIG_MPC85xx=y
5 5 CONFIG_TARGET_T102XRDB=y
configs/T1024RDB_SDCARD_defconfig
Diff comments   View file @ d81572c
1 1 CONFIG_SPL=y
2   -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
  2 +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
3 3 CONFIG_PPC=y
4 4 CONFIG_MPC85xx=y
5 5 CONFIG_TARGET_T102XRDB=y
configs/T1024RDB_SECURE_BOOT_defconfig
Diff comments   View file @ d81572c
1   -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT"
  1 +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,SECURE_BOOT"
2 2 CONFIG_PPC=y
3 3 CONFIG_MPC85xx=y
4 4 CONFIG_TARGET_T102XRDB=y
configs/T1024RDB_SPIFLASH_defconfig
Diff comments   View file @ d81572c
1 1 CONFIG_SPL=y
2   -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
  2 +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
3 3 CONFIG_PPC=y
4 4 CONFIG_MPC85xx=y
5 5 CONFIG_TARGET_T102XRDB=y
configs/T1024RDB_defconfig
Diff comments   View file @ d81572c
1   -CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024"
  1 +CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB"
2 2 CONFIG_PPC=y
3 3 CONFIG_MPC85xx=y
4 4 CONFIG_TARGET_T102XRDB=y
configs/T4160QDS_SPIFLASH_defconfig
View file @ d81572c
1   -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
2   -CONFIG_PPC=y
3   -CONFIG_MPC85xx=y
4   -CONFIG_TARGET_T4240QDS=y
configs/T4240EMU_defconfig
View file @ d81572c
1   -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
2   -CONFIG_PPC=y
3   -CONFIG_MPC85xx=y
4   -CONFIG_TARGET_T4240EMU=y
configs/T4240QDS_SPIFLASH_defconfig
View file @ d81572c
1   -CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000"
2   -CONFIG_PPC=y
3   -CONFIG_MPC85xx=y
4   -CONFIG_TARGET_T4240QDS=y
configs/T4240RDB_SDCARD_defconfig
Diff comments   View file @ d81572c
  1 +CONFIG_SPL=y
  2 +CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
  3 +CONFIG_PPC=y
  4 +CONFIG_MPC85xx=y
  5 +CONFIG_TARGET_T4240RDB=y
configs/UCP1020_SPIFLASH_defconfig
Diff comments   View file @ d81572c
  1 +CONFIG_PPC=y
  2 +CONFIG_MPC85xx=y
  3 +CONFIG_TARGET_UCP1020=y
  4 +CONFIG_TARGET_UCP1020_SPIFLASH=y
  5 +CONFIG_SPI_FLASH=y
  6 +CONFIG_UCP1020=y
configs/UCP1020_defconfig
Diff comments   View file @ d81572c
  1 +CONFIG_PPC=y
  2 +CONFIG_MPC85xx=y
  3 +CONFIG_TARGET_UCP1020=y
  4 +CONFIG_SPI_FLASH=y
  5 +CONFIG_UCP1020=y
doc/README.fsl-esdhc
Diff comments   View file @ d81572c
1   -CONFIG_SYS_FSL_ESDHC_LE means ESDHC IP is in little-endian mode.
2   -CONFIG_SYS_FSL_ESDHC_BE means ESDHC IP is in big-endian mode.
3   -CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V.
  1 +Freescale esdhc-specific options
4 2  
5   -Accessing ESDHC registers can be determined by ESDHC IP's endian
6   -mode or processor's endian mode.
  3 + - CONFIG_FSL_ESDHC_ADAPTER_IDENT
  4 + Support Freescale adapter card type identification. This is implemented by
  5 + operating Qixis FPGA relevant registers. The STAT_PRES1 register has SDHC
  6 + Card ID[0:2] bits showing the type of card installed in the SDHC Adapter Slot.
  7 +
  8 + SDHC Card ID[0:2] Adapter Card Type
  9 + 0b000 reserved
  10 + 0b001 eMMC Card Rev4.5
  11 + 0b010 SD/MMC Legacy Card
  12 + 0b011 eMMC Card Rev4.4
  13 + 0b100 reserved
  14 + 0b101 MMC Card
  15 + 0b110 SD Card Rev2.0/3.0
  16 + 0b111 No card is present
  17 + - CONFIG_SYS_FSL_ESDHC_LE
  18 + ESDHC IP is in little-endian mode. Accessing ESDHC registers can be
  19 + determined by ESDHC IP's endian mode or processor's endian mode.
  20 + - CONFIG_SYS_FSL_ESDHC_BE
  21 + ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined
  22 + by ESDHC IP's endian mode or processor's endian mode.
  23 +
  24 + - CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT forces to run at 1.8V.
drivers/mmc/fsl_esdhc.c
Diff comments   View file @ d81572c
... ... @@ -506,11 +506,47 @@
506 506 esdhc_setbits32(&regs->sysctl, clk);
507 507 }
508 508  
  509 +#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
  510 +static void esdhc_clock_control(struct mmc *mmc, bool enable)
  511 +{
  512 + struct fsl_esdhc_cfg *cfg = mmc->priv;
  513 + struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
  514 + u32 value;
  515 + u32 time_out;
  516 +
  517 + value = esdhc_read32(&regs->sysctl);
  518 +
  519 + if (enable)
  520 + value |= SYSCTL_CKEN;
  521 + else
  522 + value &= ~SYSCTL_CKEN;
  523 +
  524 + esdhc_write32(&regs->sysctl, value);
  525 +
  526 + time_out = 20;
  527 + value = PRSSTAT_SDSTB;
  528 + while (!(esdhc_read32(&regs->prsstat) & value)) {
  529 + if (time_out == 0) {
  530 + printf("fsl_esdhc: Internal clock never stabilised.\n");
  531 + break;
  532 + }
  533 + time_out--;
  534 + mdelay(1);
  535 + }
  536 +}
  537 +#endif
  538 +
509 539 static void esdhc_set_ios(struct mmc *mmc)
510 540 {
511 541 struct fsl_esdhc_cfg *cfg = mmc->priv;
512 542 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
513 543  
  544 +#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
  545 + /* Select to use peripheral clock */
  546 + esdhc_clock_control(mmc, false);
  547 + esdhc_setbits32(&regs->scr, ESDHCCTL_PCS);
  548 + esdhc_clock_control(mmc, true);
  549 +#endif
514 550 /* Set the clock speed */
515 551 set_sysctl(mmc, mmc->clock);
516 552  
... ... @@ -694,6 +730,39 @@
694 730 return fsl_esdhc_initialize(bis, cfg);
695 731 }
696 732  
  733 +#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
  734 +void mmc_adapter_card_type_ident(void)
  735 +{
  736 + u8 card_id;
  737 + u8 value;
  738 +
  739 + card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
  740 + gd->arch.sdhc_adapter = card_id;
  741 +
  742 + switch (card_id) {
  743 + case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
  744 + break;
  745 + case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
  746 + break;
  747 + case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
  748 + value = QIXIS_READ(brdcfg[5]);
  749 + value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
  750 + QIXIS_WRITE(brdcfg[5], value);
  751 + break;
  752 + case QIXIS_ESDHC_ADAPTER_TYPE_RSV:
  753 + break;
  754 + case QIXIS_ESDHC_ADAPTER_TYPE_MMC:
  755 + break;
  756 + case QIXIS_ESDHC_ADAPTER_TYPE_SD:
  757 + break;
  758 + case QIXIS_ESDHC_NO_ADAPTER:
  759 + break;
  760 + default:
  761 + break;
  762 + }
  763 +}
  764 +#endif
  765 +
697 766 #ifdef CONFIG_OF_LIBFDT
698 767 void fdt_fixup_esdhc(void *blob, bd_t *bd)
699 768 {
700 769  
... ... @@ -707,9 +776,17 @@
707 776 }
708 777 #endif
709 778  
  779 +#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
  780 + do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
  781 + gd->arch.sdhc_clk, 1);
  782 +#else
710 783 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
711 784 gd->arch.sdhc_clk, 1);
712   -
  785 +#endif
  786 +#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
  787 + do_fixup_by_compat_u32(blob, compat, "adapter-type",
  788 + (u32)(gd->arch.sdhc_adapter), 1);
  789 +#endif
713 790 do_fixup_by_compat(blob, compat, "status", "okay",
714 791 4 + 1, 1);
715 792 }
... ... @@ -1593,6 +1593,9 @@
1593 1593 if (mmc->has_init)
1594 1594 return 0;
1595 1595  
  1596 +#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
  1597 + mmc_adapter_card_type_ident();
  1598 +#endif
1596 1599 board_mmc_power_init();
1597 1600  
1598 1601 /* made sure it's not NULL earlier */
... ... @@ -1744,6 +1747,9 @@
1744 1747 list_for_each(entry, &mmc_devices) {
1745 1748 m = list_entry(entry, struct mmc, link);
1746 1749  
  1750 +#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
  1751 + mmc_set_preinit(m, 1);
  1752 +#endif
1747 1753 if (m->preinit)
1748 1754 mmc_start_init(m);
1749 1755 }
drivers/mmc/mmc_private.h
Diff comments   View file @ d81572c
... ... @@ -16,6 +16,9 @@
16 16 struct mmc_data *data);
17 17 extern int mmc_send_status(struct mmc *mmc, int timeout);
18 18 extern int mmc_set_blocklen(struct mmc *mmc, int len);
  19 +#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
  20 +void mmc_adapter_card_type_ident(void);
  21 +#endif
19 22  
20 23 #ifndef CONFIG_SPL_BUILD
21 24  
drivers/pci/fsl_pci_init.c
Diff comments   View file @ d81572c
... ... @@ -444,6 +444,21 @@
444 444 ltssm = (in_be32(&pci->pex_csr0)
445 445 & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
446 446 enabled = (ltssm == 0x11) ? 1 : 0;
  447 +#ifdef CONFIG_FSL_PCIE_RESET
  448 + int i;
  449 + /* assert PCIe reset */
  450 + setbits_be32(&pci->pdb_stat, 0x08000000);
  451 + (void) in_be32(&pci->pdb_stat);
  452 + udelay(1000);
  453 + /* clear PCIe reset */
  454 + clrbits_be32(&pci->pdb_stat, 0x08000000);
  455 + asm("sync;isync");
  456 + for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
  457 + pci_hose_read_config_word(hose, dev, PCI_LTSSM,
  458 + &ltssm);
  459 + udelay(1000);
  460 + }
  461 +#endif
447 462 } else {
448 463 /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm); */
449 464 /* enabled = ltssm >= PCI_LTSSM_L0; */
450 465  
... ... @@ -682,8 +697,14 @@
682 697 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
683 698 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
684 699 if (pcie_cap != 0x0) {
  700 + ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr;
  701 + u32 block_rev = in_be32(&pci->block_rev1);
685 702 /* PCIe - set CFG_READY bit of Configuration Ready Register */
686   - pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
  703 + if (block_rev >= PEX_IP_BLK_REV_3_0)
  704 + setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY);
  705 + else
  706 + pci_hose_write_config_byte(hose, dev,
  707 + FSL_PCIE_CFG_RDY, 0x1);
687 708 } else {
688 709 /* PCI - clear ACL bit of PBFR */
689 710 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
drivers/usb/host/ehci-fsl.c
Diff comments   View file @ d81572c
... ... @@ -138,6 +138,16 @@
138 138 if (has_erratum_a007798())
139 139 set_txfifothresh(ehci, TXFIFOTHRESH);
140 140  
  141 + if (has_erratum_a004477()) {
  142 + /*
  143 + * When reset is issued while any ULPI transaction is ongoing
  144 + * then it may result to corruption of ULPI Function Control
  145 + * Register which eventually causes phy clock to enter low
  146 + * power mode which stops the clock. Thus delay is required
  147 + * before reset to let ongoing ULPI transaction complete.
  148 + */
  149 + udelay(1);
  150 + }
141 151 return 0;
142 152 }
143 153  
include/configs/T102xRDB.h
Diff comments   View file @ d81572c
... ... @@ -11,6 +11,12 @@
11 11 #ifndef __T1024RDB_H
12 12 #define __T1024RDB_H
13 13  
  14 +#if defined(CONFIG_T1023RDB)
  15 +#ifdef CONFIG_SPL
  16 +#define CONFIG_SYS_NO_FLASH
  17 +#endif
  18 +#endif
  19 +
14 20 /* High Level Configuration Options */
15 21 #define CONFIG_SYS_GENERIC_BOARD
16 22 #define CONFIG_DISPLAY_BOARDINFO
17 23  
... ... @@ -35,7 +41,9 @@
35 41 #define CONFIG_ENV_OVERWRITE
36 42  
37 43 /* support deep sleep */
  44 +#ifdef CONFIG_PPC_T1024
38 45 #define CONFIG_DEEP_SLEEP
  46 +#endif
39 47 #if defined(CONFIG_DEEP_SLEEP)
40 48 #define CONFIG_SILENT_CONSOLE
41 49 #define CONFIG_BOARD_EARLY_INIT_F
42 50  
... ... @@ -43,7 +51,11 @@
43 51  
44 52 #ifdef CONFIG_RAMBOOT_PBL
45 53 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
  54 +#if defined(CONFIG_T1024RDB)
46 55 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg
  56 +#elif defined(CONFIG_T1023RDB)
  57 +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg
  58 +#endif
47 59 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
48 60 #define CONFIG_SPL_ENV_SUPPORT
49 61 #define CONFIG_SPL_SERIAL_SUPPORT
50 62  
... ... @@ -177,7 +189,11 @@
177 189 #define CONFIG_ENV_SPI_MODE 0
178 190 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
179 191 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
  192 +#if defined(CONFIG_T1024RDB)
180 193 #define CONFIG_ENV_SECT_SIZE 0x10000
  194 +#elif defined(CONFIG_T1023RDB)
  195 +#define CONFIG_ENV_SECT_SIZE 0x40000
  196 +#endif
181 197 #elif defined(CONFIG_SDCARD)
182 198 #define CONFIG_SYS_EXTRA_ENV_RELOC
183 199 #define CONFIG_ENV_IS_IN_MMC
184 200  
... ... @@ -188,7 +204,11 @@
188 204 #define CONFIG_SYS_EXTRA_ENV_RELOC
189 205 #define CONFIG_ENV_IS_IN_NAND
190 206 #define CONFIG_ENV_SIZE 0x2000
  207 +#if defined(CONFIG_T1024RDB)
191 208 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
  209 +#elif defined(CONFIG_T1023RDB)
  210 +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
  211 +#endif
192 212 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
193 213 #define CONFIG_ENV_IS_IN_REMOTE
194 214 #define CONFIG_ENV_ADDR 0xffe20000
... ... @@ -209,7 +229,7 @@
209 229 #endif
210 230  
211 231 #define CONFIG_SYS_CLK_FREQ 100000000
212   -#define CONFIG_DDR_CLK_FREQ 66660000
  232 +#define CONFIG_DDR_CLK_FREQ 100000000
213 233  
214 234 /*
215 235 * These can be toggled for performance analysis, otherwise use default.
... ... @@ -224,6 +244,7 @@
224 244 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
225 245 #endif
226 246  
  247 +#define CONFIG_CMD_MEMTEST
227 248 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
228 249 #define CONFIG_SYS_MEMTEST_END 0x00400000
229 250 #define CONFIG_SYS_ALT_MEMTEST
230 251  
231 252  
232 253  
... ... @@ -265,13 +286,18 @@
265 286 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
266 287 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
267 288 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  289 +#define CONFIG_FSL_DDR_INTERACTIVE
  290 +#if defined(CONFIG_T1024RDB)
268 291 #define CONFIG_DDR_SPD
269 292 #define CONFIG_SYS_FSL_DDR3
270   -
271 293 #define CONFIG_SYS_SPD_BUS_NUM 0
272 294 #define SPD_EEPROM_ADDRESS 0x51
273   -
274 295 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  296 +#elif defined(CONFIG_T1023RDB)
  297 +#define CONFIG_SYS_FSL_DDR4
  298 +#define CONFIG_SYS_DDR_RAW_TIMING
  299 +#define CONFIG_SYS_SDRAM_SIZE 2048
  300 +#endif
275 301  
276 302 /*
277 303 * IFC Definitions
278 304  
... ... @@ -291,7 +317,12 @@
291 317 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
292 318  
293 319 /* NOR Flash Timing Params */
  320 +#if defined(CONFIG_T1024RDB)
294 321 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  322 +#elif defined(CONFIG_T1023RDB)
  323 +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
  324 + CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
  325 +#endif
295 326 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
296 327 FTIM0_NOR_TEADC(0x5) | \
297 328 FTIM0_NOR_TEAHC(0x5))
... ... @@ -315,6 +346,7 @@
315 346 #define CONFIG_SYS_FLASH_EMPTY_INFO
316 347 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
317 348  
  349 +#ifdef CONFIG_T1024RDB
318 350 /* CPLD on IFC */
319 351 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
320 352 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
... ... @@ -336,6 +368,7 @@
336 368 FTIM2_GPCM_TCH(0x8) | \
337 369 FTIM2_GPCM_TWP(0x1f))
338 370 #define CONFIG_SYS_CS2_FTIM3 0x0
  371 +#endif
339 372  
340 373 /* NAND Flash on IFC */
341 374 #define CONFIG_NAND_FSL_IFC
... ... @@ -352,6 +385,7 @@
352 385 | CSPR_V)
353 386 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
354 387  
  388 +#if defined(CONFIG_T1024RDB)
355 389 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
356 390 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
357 391 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
358 392  
... ... @@ -359,9 +393,17 @@
359 393 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
360 394 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
361 395 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  396 +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
  397 +#elif defined(CONFIG_T1023RDB)
  398 +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
  399 + | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
  400 + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  401 + | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
  402 + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  403 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  404 +#endif
362 405  
363 406 #define CONFIG_SYS_NAND_ONFI_DETECTION
364   -
365 407 /* ONFI NAND Flash mode0 Timing Params */
366 408 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
367 409 FTIM0_NAND_TWP(0x18) | \
... ... @@ -381,8 +423,6 @@
381 423 #define CONFIG_SYS_MAX_NAND_DEVICE 1
382 424 #define CONFIG_CMD_NAND
383 425  
384   -#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
385   -
386 426 #if defined(CONFIG_NAND)
387 427 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
388 428 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
389 429  
... ... @@ -536,7 +576,11 @@
536 576 */
537 577 #define CONFIG_FSL_ESPI
538 578 #define CONFIG_SPI_FLASH
  579 +#if defined(CONFIG_T1024RDB)
539 580 #define CONFIG_SPI_FLASH_STMICRO
  581 +#elif defined(CONFIG_T1023RDB)
  582 +#define CONFIG_SPI_FLASH_SPANSION
  583 +#endif
540 584 #define CONFIG_CMD_SF
541 585 #define CONFIG_SPI_FLASH_BAR
542 586 #define CONFIG_SF_DEFAULT_SPEED 10000000
543 587  
... ... @@ -736,8 +780,13 @@
736 780 #define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
737 781 #elif defined(CONFIG_NAND)
738 782 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
  783 +#if defined(CONFIG_T1024RDB)
739 784 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
740 785 #define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
  786 +#elif defined(CONFIG_T1023RDB)
  787 +#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
  788 +#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
  789 +#endif
741 790 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
742 791 /*
743 792 * Slave has no ucode locally, it can fetch this from remote. When implementing
744 793  
745 794  
746 795  
... ... @@ -762,11 +811,17 @@
762 811 #define CONFIG_PHYLIB_10G
763 812 #define CONFIG_PHY_REALTEK
764 813 #define CONFIG_PHY_AQUANTIA
  814 +#if defined(CONFIG_T1024RDB)
765 815 #define RGMII_PHY1_ADDR 0x2
766 816 #define RGMII_PHY2_ADDR 0x6
767   -#define SGMII_PHY1_ADDR 0x2
  817 +#define SGMII_AQR_PHY_ADDR 0x2
768 818 #define FM1_10GEC1_PHY_ADDR 0x1
  819 +#elif defined(CONFIG_T1023RDB)
  820 +#define RGMII_PHY1_ADDR 0x1
  821 +#define SGMII_RTK_PHY_ADDR 0x3
  822 +#define SGMII_AQR_PHY_ADDR 0x2
769 823 #endif
  824 +#endif
770 825  
771 826 #ifdef CONFIG_FMAN_ENET
772 827 #define CONFIG_MII /* MII PHY management */
773 828  
774 829  
775 830  
... ... @@ -855,21 +910,23 @@
855 910 */
856 911 #define CONFIG_ROOTPATH "/opt/nfsroot"
857 912 #define CONFIG_BOOTFILE "uImage"
858   -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
  913 +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
859 914 #define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
860 915 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
861 916 #define CONFIG_BAUDRATE 115200
862 917 #define __USB_PHY_TYPE utmi
863 918  
864 919 #ifdef CONFIG_PPC_T1024
865   -#define CONFIG_BOARDNAME "t1024rdb"
  920 +#define CONFIG_BOARDNAME t1024rdb
  921 +#define BANK_INTLV cs0_cs1
866 922 #else
867   -#define CONFIG_BOARDNAME "t1023rdb"
  923 +#define CONFIG_BOARDNAME t1023rdb
  924 +#define BANK_INTLV null
868 925 #endif
869 926  
870 927 #define CONFIG_EXTRA_ENV_SETTINGS \
871 928 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
872   - "bank_intlv=cs0_cs1\0" \
  929 + "bank_intlv=" __stringify(BANK_INTLV) "\0" \
873 930 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
874 931 "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
875 932 "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
include/configs/T208xQDS.h
Diff comments   View file @ d81572c
... ... @@ -575,6 +575,7 @@
575 575 #define CONFIG_PCIE2 /* PCIE controler 2 */
576 576 #define CONFIG_PCIE3 /* PCIE controler 3 */
577 577 #define CONFIG_PCIE4 /* PCIE controler 4 */
  578 +#define CONFIG_FSL_PCIE_RESET
578 579 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
579 580 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
580 581 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
... ... @@ -756,6 +757,7 @@
756 757 #ifdef CONFIG_MMC
757 758 #define CONFIG_CMD_MMC
758 759 #define CONFIG_FSL_ESDHC
  760 +#define define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
759 761 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
760 762 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
761 763 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
... ... @@ -763,6 +765,7 @@
763 765 #define CONFIG_CMD_EXT2
764 766 #define CONFIG_CMD_FAT
765 767 #define CONFIG_DOS_PARTITION
  768 +#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
766 769 #endif
767 770  
768 771  
include/configs/T4240EMU.h
View file @ d81572c
1   -/*
2   - * Copyright 2013 Freescale Semiconductor, Inc.
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -/*
8   - * T4240 EMU board configuration file
9   - */
10   -#ifndef __CONFIG_H
11   -#define __CONFIG_H
12   -
13   -#define CONFIG_T4240EMU
14   -#define CONFIG_PHYS_64BIT
15   -
16   -#define CONFIG_SYS_NO_FLASH 1
17   -#define CONFIG_SYS_FSL_DDR_EMU 1
18   -#define CONFIG_SYS_FSL_NO_QIXIS 1
19   -#define CONFIG_SYS_FSL_NO_SERDES 1
20   -
21   -#include "t4qds.h"
22   -
23   -#define CONFIG_CMD_CACHE
24   -#define CONFIG_CMD_CACHE_FLUSH
25   -
26   -#define CONFIG_ENV_IS_NOWHERE
27   -#define CONFIG_ENV_SIZE 0x2000
28   -
29   -#define CONFIG_SYS_CLK_FREQ 100000000
30   -#define CONFIG_DDR_CLK_FREQ 133333333
31   -#define CONFIG_FSL_TBCLK_EXTRA_DIV 100
32   -
33   -/*
34   - * DDR Setup
35   - */
36   -#define CONFIG_SYS_SPD_BUS_NUM 1
37   -#define SPD_EEPROM_ADDRESS1 0x51
38   -#define SPD_EEPROM_ADDRESS2 0x52
39   -#define SPD_EEPROM_ADDRESS3 0x53
40   -#define SPD_EEPROM_ADDRESS4 0x54
41   -#define SPD_EEPROM_ADDRESS5 0x55
42   -#define SPD_EEPROM_ADDRESS6 0x56
43   -#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
44   -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
45   -
46   -/*
47   - * IFC Definitions
48   - */
49   -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
50   -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
51   -/* NOR Flash Timing Params */
52   -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
53   - + 0x8000000) | \
54   - CSPR_PORT_SIZE_32 | \
55   - CSPR_MSEL_NOR | \
56   - CSPR_V)
57   -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(0)
58   -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
59   - FTIM0_NOR_TEADC(0x1) | \
60   - FTIM0_NOR_TEAHC(0x1))
61   -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
62   - FTIM1_NOR_TRAD_NOR(0x1))
63   -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
64   - FTIM2_NOR_TCH(0x0) | \
65   - FTIM2_NOR_TWP(0x1))
66   -#define CONFIG_SYS_NOR_FTIM3 0x04000000
67   -#define CONFIG_SYS_IFC_CCR 0x01000000
68   -
69   -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
70   -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
71   -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
72   -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
73   -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
74   -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
75   -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
76   -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
77   -
78   -/* I2C */
79   -#define CONFIG_SYS_FSL_I2C_SPEED 4000000 /* faster speed for emulator */
80   -#define CONFIG_SYS_FSL_I2C2_SPEED 4000000
81   -
82   -/* Qman/Bman */
83   -#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
84   -#define CONFIG_SYS_BMAN_NUM_PORTALS 50
85   -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
86   -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
87   -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
88   -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
89   -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
90   -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
91   -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
92   -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
93   - CONFIG_SYS_BMAN_CENA_SIZE)
94   -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
95   -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
96   -#define CONFIG_SYS_QMAN_NUM_PORTALS 50
97   -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
98   -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
99   -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
100   -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
101   -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
102   -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
103   -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
104   -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
105   - CONFIG_SYS_QMAN_CENA_SIZE)
106   -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
107   -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
108   -
109   -#define CONFIG_SYS_DPAA_FMAN
110   -#define CONFIG_SYS_DPAA_PME
111   -#define CONFIG_SYS_PMAN
112   -#define CONFIG_SYS_DPAA_DCE
113   -#define CONFIG_SYS_DPAA_RMAN
114   -#define CONFIG_SYS_INTERLAKEN
115   -
116   -#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
117   -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
118   -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
119   -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
120   -
121   -#define CONFIG_BOOTDELAY 0
122   -
123   -/*
124   - * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
125   - * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
126   - * interleaving. It can be cacheline, page, bank, superbank.
127   - * See doc/README.fsl-ddr for details.
128   - */
129   -#ifdef CONFIG_PPC_T4240
130   -#define CTRL_INTLV_PREFERED 3way_4KB
131   -#else
132   -#define CTRL_INTLV_PREFERED cacheline
133   -#endif
134   -
135   -#define CONFIG_EXTRA_ENV_SETTINGS \
136   - "hwconfig=fsl_ddr:" \
137   - "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
138   - "bank_intlv=auto;" \
139   - "netdev=eth0\0" \
140   - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
141   -"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
142   - "consoledev=ttyS0\0" \
143   - "ramdiskaddr=2000000\0" \
144   - "ramdiskfile=t4240emu/ramdisk.uboot\0" \
145   - "fdtaddr=c00000\0" \
146   - "fdtfile=t4240emu/t4240emu.dtb\0" \
147   - "bdev=sda3\0"
148   -
149   -/*
150   - * For emulation this causes u-boot to jump to the start of the proof point
151   - * app code automatically
152   - */
153   -#define CONFIG_PROOF_POINTS \
154   - "setenv bootargs root=/dev/$bdev rw " \
155   - "console=$consoledev,$baudrate $othbootargs;" \
156   - "cpu 1 release 0x29000000 - - -;" \
157   - "cpu 2 release 0x29000000 - - -;" \
158   - "cpu 3 release 0x29000000 - - -;" \
159   - "cpu 4 release 0x29000000 - - -;" \
160   - "cpu 5 release 0x29000000 - - -;" \
161   - "cpu 6 release 0x29000000 - - -;" \
162   - "cpu 7 release 0x29000000 - - -;" \
163   - "go 0x29000000"
164   -
165   -#define CONFIG_HVBOOT \
166   - "setenv bootargs config-addr=0x60000000; " \
167   - "bootm 0x01000000 - 0x00f00000"
168   -
169   -#define CONFIG_LINUX \
170   - "errata;" \
171   - "setenv othbootargs ignore_loglevel;" \
172   - "setenv bootargs root=/dev/ram rw " \
173   - "console=$consoledev,$baudrate $othbootargs;" \
174   - "setenv ramdiskaddr 0x02000000;" \
175   - "setenv fdtaddr 0x00c00000;" \
176   - "setenv loadaddr 0x1000000;" \
177   - "bootm $loadaddr $ramdiskaddr $fdtaddr"
178   -
179   -#define CONFIG_BOOTCOMMAND CONFIG_LINUX
180   -
181   -#endif /* __CONFIG_H */
include/configs/T4240RDB.h
Diff comments   View file @ d81572c
... ... @@ -21,12 +21,54 @@
21 21 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
22 22  
23 23 #ifdef CONFIG_RAMBOOT_PBL
24   -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
25   -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
26 24 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
27 25 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg
  26 +#ifndef CONFIG_SDCARD
  27 +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  28 +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  29 +#else
  30 +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  31 +#define CONFIG_SPL_ENV_SUPPORT
  32 +#define CONFIG_SPL_SERIAL_SUPPORT
  33 +#define CONFIG_SPL_FLUSH_IMAGE
  34 +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
  35 +#define CONFIG_SPL_LIBGENERIC_SUPPORT
  36 +#define CONFIG_SPL_LIBCOMMON_SUPPORT
  37 +#define CONFIG_SPL_I2C_SUPPORT
  38 +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  39 +#define CONFIG_FSL_LAW /* Use common FSL init code */
  40 +#define CONFIG_SYS_TEXT_BASE 0x00201000
  41 +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
  42 +#define CONFIG_SPL_PAD_TO 0x40000
  43 +#define CONFIG_SPL_MAX_SIZE 0x28000
  44 +#define RESET_VECTOR_OFFSET 0x27FFC
  45 +#define BOOT_PAGE_OFFSET 0x27000
  46 +
  47 +#ifdef CONFIG_SDCARD
  48 +#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
  49 +#define CONFIG_SPL_MMC_SUPPORT
  50 +#define CONFIG_SPL_MMC_MINIMAL
  51 +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
  52 +#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000
  53 +#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000
  54 +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
  55 +#ifndef CONFIG_SPL_BUILD
  56 +#define CONFIG_SYS_MPC85XX_NO_RESETVEC
28 57 #endif
  58 +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  59 +#define CONFIG_SPL_MMC_BOOT
  60 +#endif
29 61  
  62 +#ifdef CONFIG_SPL_BUILD
  63 +#define CONFIG_SPL_SKIP_RELOCATE
  64 +#define CONFIG_SPL_COMMON_INIT_DDR
  65 +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  66 +#define CONFIG_SYS_NO_FLASH
  67 +#endif
  68 +
  69 +#endif
  70 +#endif /* CONFIG_RAMBOOT_PBL */
  71 +
30 72 #define CONFIG_DDR_ECC
31 73  
32 74 #define CONFIG_CMD_REGINFO
... ... @@ -84,7 +126,16 @@
84 126 /*
85 127 * Config the L3 Cache as L3 SRAM
86 128 */
87   -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
  129 +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
  130 +#define CONFIG_SYS_L3_SIZE (512 << 10)
  131 +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
  132 +#ifdef CONFIG_RAMBOOT_PBL
  133 +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
  134 +#endif
  135 +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
  136 +#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
  137 +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
  138 +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
88 139  
89 140 #define CONFIG_SYS_DCSRBAR 0xf0000000
90 141 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
91 142  
... ... @@ -112,7 +163,11 @@
112 163 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
113 164  
114 165  
  166 +#ifdef CONFIG_SPL_BUILD
  167 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  168 +#else
115 169 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  170 +#endif
116 171  
117 172 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
118 173 #define CONFIG_MISC_INIT_R
... ... @@ -135,7 +190,7 @@
135 190 GENERATED_GBL_DATA_SIZE)
136 191 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
137 192  
138   -#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
  193 +#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
139 194 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
140 195  
141 196 /* Serial Port - controlled on board with jumper J8
... ... @@ -351,7 +406,7 @@
351 406 #define CONFIG_ENV_IS_IN_MMC
352 407 #define CONFIG_SYS_MMC_ENV_DEV 0
353 408 #define CONFIG_ENV_SIZE 0x2000
354   -#define CONFIG_ENV_OFFSET (512 * 1658)
  409 +#define CONFIG_ENV_OFFSET (512 * 0x800)
355 410 #elif defined(CONFIG_NAND)
356 411 #define CONFIG_SYS_EXTRA_ENV_RELOC
357 412 #define CONFIG_ENV_IS_IN_NAND
358 413  
... ... @@ -617,11 +672,11 @@
617 672 #elif defined(CONFIG_SDCARD)
618 673 /*
619 674 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
620   - * about 825KB (1650 blocks), Env is stored after the image, and the env size is
621   - * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  675 + * about 1MB (2048 blocks), Env is stored after the image, and the env size is
  676 + * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
622 677 */
623 678 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
624   -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
  679 +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
625 680 #elif defined(CONFIG_NAND)
626 681 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
627 682 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
include/configs/UCP1020.h
Diff comments   View file @ d81572c
Changes suppressed. Click to show
  1 +/*
  2 + * Copyright 2013-2015 Arcturus Networks, Inc.
  3 + * http://www.arcturusnetworks.com/products/ucp1020/
  4 + * based on include/configs/p1_p2_rdb_pc.h
  5 + * original copyright follows:
  6 + * Copyright 2009-2011 Freescale Semiconductor, Inc.
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +/*
  12 + * QorIQ uCP1020-xx boards configuration file
  13 + */
  14 +#ifndef __CONFIG_H
  15 +#define __CONFIG_H
  16 +
  17 +#define CONFIG_SYS_GENERIC_BOARD
  18 +#define CONFIG_DISPLAY_BOARDINFO
  19 +
  20 +#define CONFIG_FSL_ELBC
  21 +#define CONFIG_PCI
  22 +#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
  23 +#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
  24 +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  25 +#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
  26 +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
  27 +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  28 +
  29 +#if defined(CONFIG_TARTGET_UCP1020T1)
  30 +
  31 +#define CONFIG_UCP1020_REV_1_3
  32 +
  33 +#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
  34 +#define CONFIG_P1020
  35 +
  36 +#define CONFIG_TSEC_ENET
  37 +#define CONFIG_TSEC1
  38 +#define CONFIG_TSEC3
  39 +#define CONFIG_HAS_ETH0
  40 +#define CONFIG_HAS_ETH1
  41 +#define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
  42 +#define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
  43 +#define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
  44 +#define CONFIG_IPADDR 10.80.41.229
  45 +#define CONFIG_SERVERIP 10.80.41.227
  46 +#define CONFIG_NETMASK 255.255.252.0
  47 +#define CONFIG_ETHPRIME "eTSEC3"
  48 +
  49 +#ifndef CONFIG_SPI_FLASH
  50 +#define CONFIG_SPI_FLASH y
  51 +#endif
  52 +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
  53 +
  54 +#define CONFIG_MMC
  55 +#define CONFIG_SYS_L2_SIZE (256 << 10)
  56 +
  57 +#define CONFIG_LAST_STAGE_INIT
  58 +
  59 +#if !defined(CONFIG_DONGLE)
  60 +#define CONFIG_SILENT_CONSOLE
  61 +#endif
  62 +
  63 +#endif
  64 +
  65 +#if defined(CONFIG_TARGET_UCP1020)
  66 +
  67 +#define CONFIG_UCP1020
  68 +#define CONFIG_UCP1020_REV_1_3
  69 +
  70 +#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
  71 +#define CONFIG_P1020
  72 +
  73 +#define CONFIG_TSEC_ENET
  74 +#define CONFIG_TSEC1
  75 +#define CONFIG_TSEC2
  76 +#define CONFIG_TSEC3
  77 +#define CONFIG_HAS_ETH0
  78 +#define CONFIG_HAS_ETH1
  79 +#define CONFIG_HAS_ETH2
  80 +#define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
  81 +#define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
  82 +#define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
  83 +#define CONFIG_IPADDR 192.168.1.81
  84 +#define CONFIG_IPADDR1 192.168.1.82
  85 +#define CONFIG_IPADDR2 192.168.1.83
  86 +#define CONFIG_SERVERIP 192.168.1.80
  87 +#define CONFIG_GATEWAYIP 102.168.1.1
  88 +#define CONFIG_NETMASK 255.255.255.0
  89 +#define CONFIG_ETHPRIME "eTSEC1"
  90 +
  91 +#ifndef CONFIG_SPI_FLASH
  92 +#define CONFIG_SPI_FLASH y
  93 +#endif
  94 +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
  95 +
  96 +#define CONFIG_MMC
  97 +#define CONFIG_SYS_L2_SIZE (256 << 10)
  98 +
  99 +#define CONFIG_LAST_STAGE_INIT
  100 +
  101 +#endif
  102 +
  103 +#ifdef CONFIG_SDCARD
  104 +#define CONFIG_RAMBOOT_SDCARD
  105 +#define CONFIG_SYS_RAMBOOT
  106 +#define CONFIG_SYS_EXTRA_ENV_RELOC
  107 +#define CONFIG_SYS_TEXT_BASE 0x11000000
  108 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
  109 +#endif
  110 +
  111 +#ifdef CONFIG_SPIFLASH
  112 +#define CONFIG_RAMBOOT_SPIFLASH
  113 +#define CONFIG_SYS_RAMBOOT
  114 +#define CONFIG_SYS_EXTRA_ENV_RELOC
  115 +#define CONFIG_SYS_TEXT_BASE 0x11000000
  116 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
  117 +#endif
  118 +
  119 +#ifndef CONFIG_SYS_TEXT_BASE
  120 +#define CONFIG_SYS_TEXT_BASE 0xeff80000
  121 +#endif
  122 +#define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
  123 +
  124 +#ifndef CONFIG_RESET_VECTOR_ADDRESS
  125 +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  126 +#endif
  127 +
  128 +#ifndef CONFIG_SYS_MONITOR_BASE
  129 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  130 +#endif
  131 +
  132 +/* High Level Configuration Options */
  133 +#define CONFIG_BOOKE
  134 +#define CONFIG_E500
  135 +/* #define CONFIG_MPC85xx */
  136 +
  137 +#define CONFIG_MP
  138 +
  139 +#define CONFIG_FSL_LAW
  140 +
  141 +#define CONFIG_ENV_OVERWRITE
  142 +
  143 +#define CONFIG_CMD_SATA
  144 +#define CONFIG_SATA_SIL
  145 +#define CONFIG_SYS_SATA_MAX_DEVICE 2
  146 +#define CONFIG_LIBATA
  147 +#define CONFIG_LBA48
  148 +
  149 +#define CONFIG_SYS_CLK_FREQ 66666666
  150 +#define CONFIG_DDR_CLK_FREQ 66666666
  151 +
  152 +#define CONFIG_HWCONFIG
  153 +
  154 +#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
  155 +#define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */
  156 +#define CONFIG_DTT_SENSORS { 0, 1 } /* Sensor index */
  157 +/*
  158 + * ADM1021/NCT72 temp sensor configuration (see dtt/adm1021.c for details).
  159 + * there will be one entry in this array for each two (dummy) sensors in
  160 + * CONFIG_DTT_SENSORS.
  161 + *
  162 + * For uCP1020 module:
  163 + * - only one ADM1021/NCT72
  164 + * - i2c addr 0x41
  165 + * - conversion rate 0x02 = 0.25 conversions/second
  166 + * - ALERT output disabled
  167 + * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
  168 + * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
  169 + */
  170 +#define CONFIG_SYS_DTT_ADM1021 { { CONFIG_SYS_I2C_NCT72_ADDR, \
  171 + 0x02, 0, 1, 0, 85, 1, 0, 85} }
  172 +
  173 +#define CONFIG_CMD_DTT
  174 +
  175 +/*
  176 + * These can be toggled for performance analysis, otherwise use default.
  177 + */
  178 +#define CONFIG_L2_CACHE
  179 +#define CONFIG_BTB
  180 +
  181 +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
  182 +
  183 +#define CONFIG_ENABLE_36BIT_PHYS
  184 +
  185 +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  186 +#define CONFIG_SYS_MEMTEST_END 0x1fffffff
  187 +#define CONFIG_PANIC_HANG /* do not reset board on panic */
  188 +
  189 +#define CONFIG_SYS_CCSRBAR 0xffe00000
  190 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  191 +
  192 +/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
  193 + SPL code*/
  194 +#ifdef CONFIG_SPL_BUILD
  195 +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  196 +#endif
  197 +
  198 +/* DDR Setup */
  199 +#define CONFIG_DDR_ECC_ENABLE
  200 +#define CONFIG_SYS_FSL_DDR3
  201 +#ifndef CONFIG_DDR_ECC_ENABLE
  202 +#define CONFIG_SYS_DDR_RAW_TIMING
  203 +#define CONFIG_DDR_SPD
  204 +#endif
  205 +#define CONFIG_SYS_SPD_BUS_NUM 1
  206 +#undef CONFIG_FSL_DDR_INTERACTIVE
  207 +
  208 +#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
  209 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1
  210 +#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
  211 +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  212 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  213 +
  214 +#define CONFIG_NUM_DDR_CONTROLLERS 1
  215 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1
  216 +
  217 +/* Default settings for DDR3 */
  218 +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
  219 +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
  220 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
  221 +#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
  222 +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
  223 +#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
  224 +
  225 +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  226 +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
  227 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
  228 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
  229 +
  230 +#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
  231 +#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
  232 +#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
  233 +#define CONFIG_SYS_DDR_RCW_1 0x00000000
  234 +#define CONFIG_SYS_DDR_RCW_2 0x00000000
  235 +#ifdef CONFIG_DDR_ECC_ENABLE
  236 +#define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
  237 +#else
  238 +#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
  239 +#endif
  240 +#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
  241 +#define CONFIG_SYS_DDR_TIMING_4 0x00220001
  242 +#define CONFIG_SYS_DDR_TIMING_5 0x03402400
  243 +
  244 +#define CONFIG_SYS_DDR_TIMING_3 0x00020000
  245 +#define CONFIG_SYS_DDR_TIMING_0 0x00330004
  246 +#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
  247 +#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
  248 +#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
  249 +#define CONFIG_SYS_DDR_MODE_1 0x40461520
  250 +#define CONFIG_SYS_DDR_MODE_2 0x8000c000
  251 +#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
  252 +
  253 +#undef CONFIG_CLOCKS_IN_MHZ
  254 +
  255 +/*
  256 + * Memory map
  257 + *
  258 + * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
  259 + * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
  260 + * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
  261 + * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
  262 + * (early boot only)
  263 + * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
  264 + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
  265 + * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  266 + */
  267 +
  268 +/*
  269 + * Local Bus Definitions
  270 + */
  271 +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
  272 +#define CONFIG_SYS_FLASH_BASE 0xec000000
  273 +
  274 +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  275 +
  276 +#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
  277 + | BR_PS_16 | BR_V)
  278 +
  279 +#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
  280 +
  281 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  282 +#define CONFIG_SYS_FLASH_QUIET_TEST
  283 +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  284 +
  285 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  286 +
  287 +#undef CONFIG_SYS_FLASH_CHECKSUM
  288 +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  289 +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  290 +
  291 +#define CONFIG_FLASH_CFI_DRIVER
  292 +#define CONFIG_SYS_FLASH_CFI
  293 +#define CONFIG_SYS_FLASH_EMPTY_INFO
  294 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  295 +
  296 +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
  297 +
  298 +#define CONFIG_SYS_INIT_RAM_LOCK
  299 +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
  300 +/* Initial L1 address */
  301 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
  302 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  303 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  304 +/* Size of used area in RAM */
  305 +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  306 +
  307 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  308 + GENERATED_GBL_DATA_SIZE)
  309 +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  310 +
  311 +#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
  312 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
  313 +
  314 +#define CONFIG_SYS_PMC_BASE 0xff980000
  315 +#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
  316 +#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
  317 + BR_PS_8 | BR_V)
  318 +#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
  319 + OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
  320 + OR_GPCM_EAD)
  321 +
  322 +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  323 +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  324 +#ifdef CONFIG_NAND_FSL_ELBC
  325 +#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
  326 +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  327 +#endif
  328 +
  329 +/* Serial Port - controlled on board with jumper J8
  330 + * open - index 2
  331 + * shorted - index 1
  332 + */
  333 +#define CONFIG_CONS_INDEX 1
  334 +#undef CONFIG_SERIAL_SOFTWARE_FIFO
  335 +#define CONFIG_SYS_NS16550
  336 +#define CONFIG_SYS_NS16550_SERIAL
  337 +#define CONFIG_SYS_NS16550_REG_SIZE 1
  338 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  339 +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
  340 +#define CONFIG_NS16550_MIN_FUNCTIONS
  341 +#endif
  342 +
  343 +#define CONFIG_SYS_BAUDRATE_TABLE \
  344 + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  345 +
  346 +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
  347 +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
  348 +
  349 +/* Use the HUSH parser */
  350 +#define CONFIG_SYS_HUSH_PARSER
  351 +
  352 +/*
  353 + * Pass open firmware flat tree
  354 + */
  355 +#define CONFIG_OF_LIBFDT
  356 +#define CONFIG_OF_BOARD_SETUP
  357 +#define CONFIG_OF_STDOUT_VIA_ALIAS
  358 +
  359 +/* new uImage format support */
  360 +#define CONFIG_FIT
  361 +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
  362 +
  363 +/* I2C */
  364 +#define CONFIG_SYS_I2C
  365 +#define CONFIG_SYS_I2C_FSL
  366 +#define CONFIG_SYS_FSL_I2C_SPEED 400000
  367 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  368 +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  369 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000
  370 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  371 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  372 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
  373 +#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
  374 +
  375 +#define CONFIG_RTC_DS1337
  376 +#define CONFIG_SYS_RTC_DS1337_NOOSC
  377 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68
  378 +#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
  379 +#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
  380 +#define CONFIG_SYS_I2C_IDT6V49205B 0x69
  381 +
  382 +/*
  383 + * eSPI - Enhanced SPI
  384 + */
  385 +#define CONFIG_HARD_SPI
  386 +#define CONFIG_FSL_ESPI
  387 +
  388 +#define CONFIG_SPI_FLASH_SST 1
  389 +#define CONFIG_SPI_FLASH_STMICRO 1
  390 +#define CONFIG_SPI_FLASH_WINBOND 1
  391 +#define CONFIG_CMD_SF 1
  392 +#define CONFIG_CMD_SPI 1
  393 +#define CONFIG_SF_DEFAULT_SPEED 10000000
  394 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
  395 +
  396 +#if defined(CONFIG_PCI)
  397 +/*
  398 + * General PCI
  399 + * Memory space is mapped 1-1, but I/O space must start from 0.
  400 + */
  401 +
  402 +/* controller 2, direct to uli, tgtid 2, Base address 9000 */
  403 +#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
  404 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  405 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  406 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  407 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  408 +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
  409 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  410 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
  411 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  412 +
  413 +/* controller 1, Slot 2, tgtid 1, Base address a000 */
  414 +#define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
  415 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  416 +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  417 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
  418 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  419 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
  420 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  421 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
  422 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  423 +
  424 +#define CONFIG_PCI_PNP /* do pci plug-and-play */
  425 +#define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/
  426 +#define CONFIG_CMD_PCI
  427 +#define CONFIG_CMD_NET
  428 +
  429 +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  430 +#define CONFIG_DOS_PARTITION
  431 +#endif /* CONFIG_PCI */
  432 +
  433 +/*
  434 + * Environment
  435 + */
  436 +#ifdef CONFIG_ENV_FIT_UCBOOT
  437 +
  438 +#define CONFIG_ENV_IS_IN_FLASH
  439 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
  440 +#define CONFIG_ENV_SIZE 0x20000
  441 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  442 +
  443 +#else
  444 +
  445 +#define CONFIG_ENV_SPI_BUS 0
  446 +#define CONFIG_ENV_SPI_CS 0
  447 +#define CONFIG_ENV_SPI_MAX_HZ 10000000
  448 +#define CONFIG_ENV_SPI_MODE 0
  449 +
  450 +#ifdef CONFIG_RAMBOOT_SPIFLASH
  451 +
  452 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  453 +#define CONFIG_ENV_SIZE 0x3000 /* 12KB */
  454 +#define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
  455 +#define CONFIG_ENV_SECT_SIZE 0x1000
  456 +
  457 +#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
  458 +/* Address and size of Redundant Environment Sector */
  459 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
  460 +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
  461 +#endif
  462 +
  463 +#elif defined(CONFIG_RAMBOOT_SDCARD)
  464 +#define CONFIG_ENV_IS_IN_MMC
  465 +#define CONFIG_FSL_FIXED_MMC_LOCATION
  466 +#define CONFIG_ENV_SIZE 0x2000
  467 +#define CONFIG_SYS_MMC_ENV_DEV 0
  468 +
  469 +#elif defined(CONFIG_SYS_RAMBOOT)
  470 +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
  471 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  472 +#define CONFIG_ENV_SIZE 0x2000
  473 +
  474 +#else
  475 +#define CONFIG_ENV_IS_IN_FLASH
  476 +#define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE)
  477 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  478 +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
  479 +#define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
  480 +#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
  481 +/* Address and size of Redundant Environment Sector */
  482 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
  483 +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
  484 +#endif
  485 +
  486 +#endif
  487 +
  488 +#endif /* CONFIG_ENV_FIT_UCBOOT */
  489 +
  490 +#define CONFIG_LOADS_ECHO /* echo on for serial download */
  491 +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  492 +
  493 +/*
  494 + * Command line configuration.
  495 + */
  496 +#include <config_cmd_default.h>
  497 +
  498 +#define CONFIG_CMD_IRQ
  499 +#define CONFIG_CMD_PING
  500 +#define CONFIG_CMD_I2C
  501 +#define CONFIG_CMD_MII
  502 +#define CONFIG_CMD_DATE
  503 +#define CONFIG_CMD_ELF
  504 +#define CONFIG_CMD_I2C
  505 +#define CONFIG_CMD_IRQ
  506 +#define CONFIG_CMD_MII
  507 +#define CONFIG_CMD_PING
  508 +#define CONFIG_CMD_SETEXPR
  509 +#define CONFIG_CMD_REGINFO
  510 +#define CONFIG_CMD_ERRATA
  511 +#define CONFIG_CMD_CRAMFS
  512 +#define CONFIG_CRAMFS_CMDLINE
  513 +
  514 +/*
  515 + * USB
  516 + */
  517 +#define CONFIG_HAS_FSL_DR_USB
  518 +
  519 +#if defined(CONFIG_HAS_FSL_DR_USB)
  520 +#define CONFIG_USB_EHCI
  521 +
  522 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  523 +
  524 +#ifdef CONFIG_USB_EHCI
  525 +#define CONFIG_CMD_USB
  526 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  527 +#define CONFIG_USB_EHCI_FSL
  528 +#define CONFIG_USB_STORAGE
  529 +#endif
  530 +#endif
  531 +
  532 +#undef CONFIG_WATCHDOG /* watchdog disabled */
  533 +
  534 +#ifdef CONFIG_MMC
  535 +#define CONFIG_FSL_ESDHC
  536 +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  537 +#define CONFIG_CMD_MMC
  538 +#define CONFIG_MMC_SPI
  539 +#define CONFIG_CMD_MMC_SPI
  540 +#define CONFIG_GENERIC_MMC
  541 +#endif
  542 +
  543 +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) || defined(CONFIG_FSL_SATA)
  544 +#define CONFIG_CMD_EXT2
  545 +#define CONFIG_CMD_FAT
  546 +#define CONFIG_DOS_PARTITION
  547 +#endif
  548 +
  549 +/* Misc Extra Settings */
  550 +#define CONFIG_CMD_GPIO 1
  551 +#undef CONFIG_WATCHDOG /* watchdog disabled */
  552 +
  553 +/*
  554 + * Miscellaneous configurable options
  555 + */
  556 +#define CONFIG_SYS_LONGHELP /* undef to save memory */
  557 +#define CONFIG_CMDLINE_EDITING /* Command-line editing */
  558 +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  559 +#define CONFIG_SYS_PROMPT "B$ " /* Monitor Command Prompt */
  560 +#if defined(CONFIG_CMD_KGDB)
  561 +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  562 +#else
  563 +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  564 +#endif
  565 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  566 + /* Print Buffer Size */
  567 +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  568 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
  569 +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
  570 +
  571 +/*
  572 + * For booting Linux, the board info and command line data
  573 + * have to be in the first 64 MB of memory, since this is
  574 + * the maximum mapped by the Linux kernel during initialization.
  575 + */
  576 +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
  577 +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  578 +
  579 +#if defined(CONFIG_CMD_KGDB)
  580 +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  581 +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  582 +#endif
  583 +
  584 +/*
  585 + * Environment Configuration
  586 + */
  587 +
  588 +#if defined(CONFIG_TSEC_ENET)
  589 +
  590 +#if defined(CONFIG_UCP1020_REV_1_2)
  591 +#define CONFIG_PHY_MICREL_KSZ9021
  592 +#elif defined(CONFIG_UCP1020_REV_1_3)
  593 +#define CONFIG_PHY_MICREL_KSZ9031
  594 +#else
  595 +#error "UCP1020 module revision is not defined !!!"
  596 +#endif
  597 +
  598 +#define CONFIG_CMD_DHCP
  599 +#define CONFIG_BOOTP_SERVERIP
  600 +
  601 +#define CONFIG_MII /* MII PHY management */
  602 +#define CONFIG_TSEC1_NAME "eTSEC1"
  603 +#define CONFIG_TSEC2_NAME "eTSEC2"
  604 +#define CONFIG_TSEC3_NAME "eTSEC3"
  605 +
  606 +#define TSEC1_PHY_ADDR 4
  607 +#define TSEC2_PHY_ADDR 0
  608 +#define TSEC2_PHY_ADDR_SGMII 0x00
  609 +#define TSEC3_PHY_ADDR 6
  610 +
  611 +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  612 +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  613 +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  614 +
  615 +#define TSEC1_PHYIDX 0
  616 +#define TSEC2_PHYIDX 0
  617 +#define TSEC3_PHYIDX 0
  618 +
  619 +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
  620 +
  621 +#endif
  622 +
  623 +#define CONFIG_HOSTNAME UCP1020
  624 +#define CONFIG_ROOTPATH "/opt/nfsroot"
  625 +#define CONFIG_BOOTFILE "uImage"
  626 +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  627 +
  628 +/* default location for tftp and bootm */
  629 +#define CONFIG_LOADADDR 1000000
  630 +
  631 +/*
  632 + * Autobooting
  633 + */
  634 +#define CONFIG_AUTOBOOT_KEYED
  635 +#define CONFIG_AUTOBOOT_STOP_STR "\x1b"
  636 +#define DEBUG_BOOTKEYS 0
  637 +#undef CONFIG_AUTOBOOT_DELAY_STR
  638 +#undef CONFIG_BOOTARGS
  639 +#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \
  640 + "press \"<Esc>\" to stop\n", bootdelay
  641 +
  642 +#define CONFIG_BOOTARGS /* the boot command will set bootargs */
  643 +
  644 +#define CONFIG_BAUDRATE 115200
  645 +
  646 +#if defined(CONFIG_DONGLE)
  647 +
  648 +#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
  649 +#define CONFIG_EXTRA_ENV_SETTINGS \
  650 +"bootcmd=run prog_spi_mbrbootcramfs\0" \
  651 +"bootfile=uImage\0" \
  652 +"consoledev=ttyS0\0" \
  653 +"cramfsfile=image.cramfs\0" \
  654 +"dtbaddr=0x00c00000\0" \
  655 +"dtbfile=image.dtb\0" \
  656 +"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
  657 +"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
  658 +"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
  659 +"fileaddr=0x01000000\0" \
  660 +"filesize=0x00080000\0" \
  661 +"flashmbr=sf probe 0; " \
  662 + "tftp $loadaddr $mbr; " \
  663 + "sf erase $mbr_offset +$filesize; " \
  664 + "sf write $loadaddr $mbr_offset $filesize\0" \
  665 +"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
  666 + "protect off $nor_recoveryaddr +$filesize; " \
  667 + "erase $nor_recoveryaddr +$filesize; " \
  668 + "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
  669 + "protect on $nor_recoveryaddr +$filesize\0 " \
  670 +"flashuboot=tftp $ubootaddr $ubootfile; " \
  671 + "protect off $nor_ubootaddr +$filesize; " \
  672 + "erase $nor_ubootaddr +$filesize; " \
  673 + "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
  674 + "protect on $nor_ubootaddr +$filesize\0 " \
  675 +"flashworking=tftp $workingaddr $cramfsfile; " \
  676 + "protect off $nor_workingaddr +$filesize; " \
  677 + "erase $nor_workingaddr +$filesize; " \
  678 + "cp.b $workingaddr $nor_workingaddr $filesize; " \
  679 + "protect on $nor_workingaddr +$filesize\0 " \
  680 +"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
  681 +"kerneladdr=0x01100000\0" \
  682 +"kernelfile=uImage\0" \
  683 +"loadaddr=0x01000000\0" \
  684 +"mbr=uCP1020d.mbr\0" \
  685 +"mbr_offset=0x00000000\0" \
  686 +"mmbr=uCP1020Quiet.mbr\0" \
  687 +"mmcpart=0:2\0" \
  688 +"mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
  689 + "mmc erase 1 1; " \
  690 + "mmc write $loadaddr 1 1\0" \
  691 +"mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
  692 + "mmc erase 0x40 0x400; " \
  693 + "mmc write $loadaddr 0x40 0x400\0" \
  694 +"netdev=eth0\0" \
  695 +"nor_recoveryaddr=0xEC0A0000\0" \
  696 +"nor_ubootaddr=0xEFF80000\0" \
  697 +"nor_workingaddr=0xECFA0000\0" \
  698 +"norbootrecovery=setenv bootargs $recoverybootargs" \
  699 + " console=$consoledev,$baudrate $othbootargs; " \
  700 + "run norloadrecovery; " \
  701 + "bootm $kerneladdr - $dtbaddr\0" \
  702 +"norbootworking=setenv bootargs $workingbootargs" \
  703 + " console=$consoledev,$baudrate $othbootargs; " \
  704 + "run norloadworking; " \
  705 + "bootm $kerneladdr - $dtbaddr\0" \
  706 +"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
  707 + "setenv cramfsaddr $nor_recoveryaddr; " \
  708 + "cramfsload $dtbaddr $dtbfile; " \
  709 + "cramfsload $kerneladdr $kernelfile\0" \
  710 +"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
  711 + "setenv cramfsaddr $nor_workingaddr; " \
  712 + "cramfsload $dtbaddr $dtbfile; " \
  713 + "cramfsload $kerneladdr $kernelfile\0" \
  714 +"prog_spi_mbr=run spi__mbr\0" \
  715 +"prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
  716 +"prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
  717 + "run spi__cramfs\0" \
  718 +"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
  719 + " console=$consoledev,$baudrate $othbootargs; " \
  720 + "tftp $rootfsaddr $rootfsfile; " \
  721 + "tftp $loadaddr $kernelfile; " \
  722 + "tftp $dtbaddr $dtbfile; " \
  723 + "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
  724 +"ramdisk_size=120000\0" \
  725 +"ramdiskfile=rootfs.ext2.gz.uboot\0" \
  726 +"recoveryaddr=0x02F00000\0" \
  727 +"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
  728 +"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
  729 + "mw.l 0xffe0f008 0x00400000\0" \
  730 +"rootfsaddr=0x02F00000\0" \
  731 +"rootfsfile=rootfs.ext2.gz.uboot\0" \
  732 +"rootpath=/opt/nfsroot\0" \
  733 +"spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
  734 + "protect off 0xeC000000 +$filesize; " \
  735 + "erase 0xEC000000 +$filesize; " \
  736 + "cp.b $loadaddr 0xEC000000 $filesize; " \
  737 + "cmp.b $loadaddr 0xEC000000 $filesize; " \
  738 + "protect on 0xeC000000 +$filesize\0" \
  739 +"spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
  740 + "protect off 0xeFF80000 +$filesize; " \
  741 + "erase 0xEFF80000 +$filesize; " \
  742 + "cp.b $loadaddr 0xEFF80000 $filesize; " \
  743 + "cmp.b $loadaddr 0xEFF80000 $filesize; " \
  744 + "protect on 0xeFF80000 +$filesize\0" \
  745 +"spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
  746 + "sf probe 0; sf erase 0x8000 +$filesize; " \
  747 + "sf write $loadaddr 0x8000 $filesize\0" \
  748 +"spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
  749 + "protect off 0xec0a0000 +$filesize; " \
  750 + "erase 0xeC0A0000 +$filesize; " \
  751 + "cp.b $loadaddr 0xeC0A0000 $filesize; " \
  752 + "protect on 0xec0a0000 +$filesize\0" \
  753 +"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
  754 + "sf probe 1; sf erase 0 +$filesize; " \
  755 + "sf write $loadaddr 0 $filesize\0" \
  756 +"spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
  757 + "sf probe 0; sf erase 0 +$filesize; " \
  758 + "sf write $loadaddr 0 $filesize\0" \
  759 +"tftpflash=tftpboot $loadaddr $uboot; " \
  760 + "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  761 + "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  762 + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
  763 + "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  764 + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
  765 +"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
  766 +"ubootaddr=0x01000000\0" \
  767 +"ubootfile=u-boot.bin\0" \
  768 +"ubootd=u-boot4dongle.bin\0" \
  769 +"upgrade=run flashworking\0" \
  770 +"usb_phy_type=ulpi\0 " \
  771 +"workingaddr=0x02F00000\0" \
  772 +"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
  773 +
  774 +#else
  775 +
  776 +#if defined(CONFIG_UCP1020T1)
  777 +
  778 +#define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */
  779 +#define CONFIG_EXTRA_ENV_SETTINGS \
  780 +"bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
  781 +"bootfile=uImage\0" \
  782 +"consoledev=ttyS0\0" \
  783 +"cramfsfile=image.cramfs\0" \
  784 +"dtbaddr=0x00c00000\0" \
  785 +"dtbfile=image.dtb\0" \
  786 +"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
  787 +"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
  788 +"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
  789 +"fileaddr=0x01000000\0" \
  790 +"filesize=0x00080000\0" \
  791 +"flashmbr=sf probe 0; " \
  792 + "tftp $loadaddr $mbr; " \
  793 + "sf erase $mbr_offset +$filesize; " \
  794 + "sf write $loadaddr $mbr_offset $filesize\0" \
  795 +"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
  796 + "protect off $nor_recoveryaddr +$filesize; " \
  797 + "erase $nor_recoveryaddr +$filesize; " \
  798 + "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
  799 + "protect on $nor_recoveryaddr +$filesize\0 " \
  800 +"flashuboot=tftp $ubootaddr $ubootfile; " \
  801 + "protect off $nor_ubootaddr +$filesize; " \
  802 + "erase $nor_ubootaddr +$filesize; " \
  803 + "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
  804 + "protect on $nor_ubootaddr +$filesize\0 " \
  805 +"flashworking=tftp $workingaddr $cramfsfile; " \
  806 + "protect off $nor_workingaddr +$filesize; " \
  807 + "erase $nor_workingaddr +$filesize; " \
  808 + "cp.b $workingaddr $nor_workingaddr $filesize; " \
  809 + "protect on $nor_workingaddr +$filesize\0 " \
  810 +"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
  811 +"kerneladdr=0x01100000\0" \
  812 +"kernelfile=uImage\0" \
  813 +"loadaddr=0x01000000\0" \
  814 +"mbr=uCP1020.mbr\0" \
  815 +"mbr_offset=0x00000000\0" \
  816 +"netdev=eth0\0" \
  817 +"nor_recoveryaddr=0xEC0A0000\0" \
  818 +"nor_ubootaddr=0xEFF80000\0" \
  819 +"nor_workingaddr=0xECFA0000\0" \
  820 +"norbootrecovery=setenv bootargs $recoverybootargs" \
  821 + " console=$consoledev,$baudrate $othbootargs; " \
  822 + "run norloadrecovery; " \
  823 + "bootm $kerneladdr - $dtbaddr\0" \
  824 +"norbootworking=setenv bootargs $workingbootargs" \
  825 + " console=$consoledev,$baudrate $othbootargs; " \
  826 + "run norloadworking; " \
  827 + "bootm $kerneladdr - $dtbaddr\0" \
  828 +"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
  829 + "setenv cramfsaddr $nor_recoveryaddr; " \
  830 + "cramfsload $dtbaddr $dtbfile; " \
  831 + "cramfsload $kerneladdr $kernelfile\0" \
  832 +"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
  833 + "setenv cramfsaddr $nor_workingaddr; " \
  834 + "cramfsload $dtbaddr $dtbfile; " \
  835 + "cramfsload $kerneladdr $kernelfile\0" \
  836 +"othbootargs=quiet\0" \
  837 +"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
  838 + " console=$consoledev,$baudrate $othbootargs; " \
  839 + "tftp $rootfsaddr $rootfsfile; " \
  840 + "tftp $loadaddr $kernelfile; " \
  841 + "tftp $dtbaddr $dtbfile; " \
  842 + "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
  843 +"ramdisk_size=120000\0" \
  844 +"ramdiskfile=rootfs.ext2.gz.uboot\0" \
  845 +"recoveryaddr=0x02F00000\0" \
  846 +"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
  847 +"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
  848 + "mw.l 0xffe0f008 0x00400000\0" \
  849 +"rootfsaddr=0x02F00000\0" \
  850 +"rootfsfile=rootfs.ext2.gz.uboot\0" \
  851 +"rootpath=/opt/nfsroot\0" \
  852 +"silent=1\0" \
  853 +"tftpflash=tftpboot $loadaddr $uboot; " \
  854 + "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  855 + "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  856 + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
  857 + "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  858 + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
  859 +"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
  860 +"ubootaddr=0x01000000\0" \
  861 +"ubootfile=u-boot.bin\0" \
  862 +"upgrade=run flashworking\0" \
  863 +"workingaddr=0x02F00000\0" \
  864 +"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
  865 +
  866 +#else /* For Arcturus Modules */
  867 +
  868 +#define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */
  869 +#define CONFIG_EXTRA_ENV_SETTINGS \
  870 +"bootcmd=run norkernel\0" \
  871 +"bootfile=uImage\0" \
  872 +"consoledev=ttyS0\0" \
  873 +"dtbaddr=0x00c00000\0" \
  874 +"dtbfile=image.dtb\0" \
  875 +"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
  876 +"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
  877 +"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
  878 +"fileaddr=0x01000000\0" \
  879 +"filesize=0x00080000\0" \
  880 +"flashmbr=sf probe 0; " \
  881 + "tftp $loadaddr $mbr; " \
  882 + "sf erase $mbr_offset +$filesize; " \
  883 + "sf write $loadaddr $mbr_offset $filesize\0" \
  884 +"flashuboot=tftp $loadaddr $ubootfile; " \
  885 + "protect off $nor_ubootaddr0 +$filesize; " \
  886 + "erase $nor_ubootaddr0 +$filesize; " \
  887 + "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
  888 + "protect on $nor_ubootaddr0 +$filesize; " \
  889 + "protect off $nor_ubootaddr1 +$filesize; " \
  890 + "erase $nor_ubootaddr1 +$filesize; " \
  891 + "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
  892 + "protect on $nor_ubootaddr1 +$filesize\0 " \
  893 +"format0=protect off $part0base +$part0size; " \
  894 + "erase $part0base +$part0size\0" \
  895 +"format1=protect off $part1base +$part1size; " \
  896 + "erase $part1base +$part1size\0" \
  897 +"format2=protect off $part2base +$part2size; " \
  898 + "erase $part2base +$part2size\0" \
  899 +"format3=protect off $part3base +$part3size; " \
  900 + "erase $part3base +$part3size\0" \
  901 +"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
  902 +"kerneladdr=0x01100000\0" \
  903 +"kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
  904 +"kernelfile=uImage\0" \
  905 +"loadaddr=0x01000000\0" \
  906 +"mbr=uCP1020.mbr\0" \
  907 +"mbr_offset=0x00000000\0" \
  908 +"netdev=eth0\0" \
  909 +"nor_ubootaddr0=0xEC000000\0" \
  910 +"nor_ubootaddr1=0xEFF80000\0" \
  911 +"norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
  912 + "run norkernelload; " \
  913 + "bootm $kerneladdr - $dtbaddr\0" \
  914 +"norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
  915 + "setenv cramfsaddr $part0base; " \
  916 + "cramfsload $dtbaddr $dtbfile; " \
  917 + "cramfsload $kerneladdr $kernelfile\0" \
  918 +"part0base=0xEC100000\0" \
  919 +"part0size=0x00700000\0" \
  920 +"part1base=0xEC800000\0" \
  921 +"part1size=0x02000000\0" \
  922 +"part2base=0xEE800000\0" \
  923 +"part2size=0x00800000\0" \
  924 +"part3base=0xEF000000\0" \
  925 +"part3size=0x00F80000\0" \
  926 +"partENVbase=0xEC080000\0" \
  927 +"partENVsize=0x00080000\0" \
  928 +"program0=tftp part0-000000.bin; " \
  929 + "protect off $part0base +$filesize; " \
  930 + "erase $part0base +$filesize; " \
  931 + "cp.b $loadaddr $part0base $filesize; " \
  932 + "echo Verifying...; " \
  933 + "cmp.b $loadaddr $part0base $filesize\0" \
  934 +"program1=tftp part1-000000.bin; " \
  935 + "protect off $part1base +$filesize; " \
  936 + "erase $part1base +$filesize; " \
  937 + "cp.b $loadaddr $part1base $filesize; " \
  938 + "echo Verifying...; " \
  939 + "cmp.b $loadaddr $part1base $filesize\0" \
  940 +"program2=tftp part2-000000.bin; " \
  941 + "protect off $part2base +$filesize; " \
  942 + "erase $part2base +$filesize; " \
  943 + "cp.b $loadaddr $part2base $filesize; " \
  944 + "echo Verifying...; " \
  945 + "cmp.b $loadaddr $part2base $filesize\0" \
  946 +"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
  947 + " console=$consoledev,$baudrate $othbootargs; " \
  948 + "tftp $rootfsaddr $rootfsfile; " \
  949 + "tftp $loadaddr $kernelfile; " \
  950 + "tftp $dtbaddr $dtbfile; " \
  951 + "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
  952 +"ramdisk_size=120000\0" \
  953 +"ramdiskfile=rootfs.ext2.gz.uboot\0" \
  954 +"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
  955 + "mw.l 0xffe0f008 0x00400000\0" \
  956 +"rootfsaddr=0x02F00000\0" \
  957 +"rootfsfile=rootfs.ext2.gz.uboot\0" \
  958 +"rootpath=/opt/nfsroot\0" \
  959 +"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
  960 + "sf probe 0; sf erase 0 +$filesize; " \
  961 + "sf write $loadaddr 0 $filesize\0" \
  962 +"spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
  963 + "protect off 0xeC000000 +$filesize; " \
  964 + "erase 0xEC000000 +$filesize; " \
  965 + "cp.b $loadaddr 0xEC000000 $filesize; " \
  966 + "cmp.b $loadaddr 0xEC000000 $filesize; " \
  967 + "protect on 0xeC000000 +$filesize\0" \
  968 +"tftpflash=tftpboot $loadaddr $uboot; " \
  969 + "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  970 + "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  971 + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
  972 + "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  973 + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
  974 +"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
  975 +"ubootfile=u-boot.bin\0" \
  976 +"upgrade=run flashuboot\0" \
  977 +"usb_phy_type=ulpi\0 " \
  978 +"boot_nfs= " \
  979 + "setenv bootargs root=/dev/nfs rw " \
  980 + "nfsroot=$serverip:$rootpath " \
  981 + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  982 + "console=$consoledev,$baudrate $othbootargs;" \
  983 + "tftp $loadaddr $bootfile;" \
  984 + "tftp $fdtaddr $fdtfile;" \
  985 + "bootm $loadaddr - $fdtaddr\0" \
  986 +"boot_hd = " \
  987 + "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
  988 + "console=$consoledev,$baudrate $othbootargs;" \
  989 + "usb start;" \
  990 + "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
  991 + "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
  992 + "bootm $loadaddr - $fdtaddr\0" \
  993 +"boot_usb_fat = " \
  994 + "setenv bootargs root=/dev/ram rw " \
  995 + "console=$consoledev,$baudrate $othbootargs " \
  996 + "ramdisk_size=$ramdisk_size;" \
  997 + "usb start;" \
  998 + "fatload usb 0:2 $loadaddr $bootfile;" \
  999 + "fatload usb 0:2 $fdtaddr $fdtfile;" \
  1000 + "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
  1001 + "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
  1002 +"boot_usb_ext2 = " \
  1003 + "setenv bootargs root=/dev/ram rw " \
  1004 + "console=$consoledev,$baudrate $othbootargs " \
  1005 + "ramdisk_size=$ramdisk_size;" \
  1006 + "usb start;" \
  1007 + "ext2load usb 0:4 $loadaddr $bootfile;" \
  1008 + "ext2load usb 0:4 $fdtaddr $fdtfile;" \
  1009 + "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
  1010 + "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
  1011 +"boot_nor = " \
  1012 + "setenv bootargs root=/dev/$jffs2nor rw " \
  1013 + "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
  1014 + "bootm $norbootaddr - $norfdtaddr\0 " \
  1015 +"boot_ram = " \
  1016 + "setenv bootargs root=/dev/ram rw " \
  1017 + "console=$consoledev,$baudrate $othbootargs " \
  1018 + "ramdisk_size=$ramdisk_size;" \
  1019 + "tftp $ramdiskaddr $ramdiskfile;" \
  1020 + "tftp $loadaddr $bootfile;" \
  1021 + "tftp $fdtaddr $fdtfile;" \
  1022 + "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
  1023 +
  1024 +#endif
  1025 +#endif
  1026 +
  1027 +#endif /* __CONFIG_H */
... ... @@ -18,6 +18,7 @@
18 18 unsigned long freq_ddrbus;
19 19 unsigned long freq_localbus;
20 20 unsigned long freq_qe;
  21 + unsigned long freq_sdhc;
21 22 #ifdef CONFIG_SYS_DPAA_FMAN
22 23 unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
23 24 #endif
... ... @@ -16,6 +16,10 @@
16 16 /* needed for the mmc_cfg definition */
17 17 #include <mmc.h>
18 18  
  19 +#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
  20 +#include "../board/freescale/common/qixis.h"
  21 +#endif
  22 +
19 23 /* FSL eSDHC-specific constants */
20 24 #define SYSCTL 0x0002e02c
21 25 #define SYSCTL_INITA 0x08000000
... ... @@ -74,6 +78,9 @@
74 78 #define IRQSTATEN_TC (0x00000002)
75 79 #define IRQSTATEN_CC (0x00000001)
76 80  
  81 +#define ESDHCCTL 0x0002e40c
  82 +#define ESDHCCTL_PCS (0x00080000)
  83 +
77 84 #define PRSSTAT 0x0002e024
78 85 #define PRSSTAT_DAT0 (0x01000000)
79 86 #define PRSSTAT_CLSL (0x00800000)
... ... @@ -82,6 +89,7 @@
82 89 #define PRSSTAT_CINS (0x00010000)
83 90 #define PRSSTAT_BREN (0x00000800)
84 91 #define PRSSTAT_BWEN (0x00000400)
  92 +#define PRSSTAT_SDSTB (0X00000008)
85 93 #define PRSSTAT_DLA (0x00000004)
86 94 #define PRSSTAT_CICHB (0x00000002)
87 95 #define PRSSTAT_CIDHB (0x00000001)
... ... @@ -209,6 +209,30 @@
209 209 return false;
210 210 }
211 211  
  212 +static inline bool has_erratum_a004477(void)
  213 +{
  214 + u32 svr = get_svr();
  215 + u32 soc = SVR_SOC_VER(svr);
  216 +
  217 + switch (soc) {
  218 + case SVR_P1010:
  219 + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
  220 + case SVR_P1022:
  221 + case SVR_9131:
  222 + case SVR_9132:
  223 + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1);
  224 + case SVR_P2020:
  225 + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0) ||
  226 + IS_SVR_REV(svr, 2, 1);
  227 + case SVR_B4860:
  228 + case SVR_B4420:
  229 + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
  230 + case SVR_P4080:
  231 + return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
  232 + }
  233 +
  234 + return false;
  235 +}
212 236 #else
213 237 static inline bool has_dual_phy(void)
214 238 {
... ... @@ -236,6 +260,11 @@
236 260 }
237 261  
238 262 static inline bool has_erratum_a005697(void)
  263 +{
  264 + return false;
  265 +}
  266 +
  267 +static inline bool has_erratum_a004477(void)
239 268 {
240 269 return false;
241 270 }