ppc4xx: Add Sequoia RAM-booting target

This patch adds another build target for the AMCC Sequoia PPC440EPx eval board. This RAM-booting version is targeted for boards without NOR FLASH (NAND booting) which need a possibility to initially program their NAND FLASH. Using a JTAG debugger (e.g. BDI2000/3000) configured to setup the SDRAM, this debugger can load this RAM- booting image to the target address in SDRAM (in this case 0x1000000) and start it there. Then U-Boot's standard NAND commands can be used to program the NAND FLASH (e.g. "nand write ..."). Here the commands to load and start this image from the BDI2000: 440EPX>reset halt 440EPX>load 0x1000000 /tftpboot/sequoia/u-boot.bin 440EPX>go 0x1000000 Please note that this image automatically scans for an already initialized SDRAM TLB (detected by EPN=0). This TLB will not be cleared. This TLB doesn't need to be TLB #0, this RAM-booting version will detect it and preserve it. So booting via BDI2000 will work and booting with a complete different TLB init via U-Boot works as well. Signed-off-by: Stefan Roese <sr@denx.de>

ppc4xx: Add Sequoia RAM-booting target
This patch adds another build target for the AMCC Sequoia PPC440EPx eval board. This RAM-booting version is targeted for boards without NOR FLASH (NAND booting) which need a possibility to initially program their NAND FLASH. Using a JTAG debugger (e.g. BDI2000/3000) configured to setup the SDRAM, this debugger can load this RAM- booting image to the target address in SDRAM (in this case 0x1000000) and start it there. Then U-Boot's standard NAND commands can be used to program the NAND FLASH (e.g. "nand write ..."). Here the commands to load and start this image from the BDI2000: 440EPX>reset halt 440EPX>load 0x1000000 /tftpboot/sequoia/u-boot.bin 440EPX>go 0x1000000 Please note that this image automatically scans for an already initialized SDRAM TLB (detected by EPN=0). This TLB will not be cleared. This TLB doesn't need to be TLB #0, this RAM-booting version will detect it and preserve it. So booting via BDI2000 will work and booting with a complete different TLB init via U-Boot works as well. Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese · Wolfgang Denk
1 parent 837db3d87f
Showing 8 changed files with 215 additions and 16 deletions Side-by-side Diff
Makefile
board/amcc/sequoia/init.S
board/amcc/sequoia/sdram.c
board/amcc/sequoia/sequoia.c
board/amcc/sequoia/u-boot-ram.lds
cpu/ppc4xx/start.S
include/configs/amcc-common.h
include/configs/sequoia.h
@@ -1533,6 +1533,17 @@
 	@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
 	@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
  
+sequoia_ramboot_config \
+rainier_ramboot_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/amcc/sequoia
+	@echo "#define CONFIG_SYS_RAMBOOT" > $(obj)include/config.h
+	@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
+		tr '[:lower:]' '[:upper:]')" >> $(obj)include/config.h
+	@$(MKCONFIG) -n $@ -a sequoia ppc ppc4xx sequoia amcc
+	@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
+	@echo "LDSCRIPT = board/amcc/sequoia/u-boot-ram.lds" >> \
+		$(obj)board/amcc/sequoia/config.tmp
+
 taihu_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx taihu amcc
  
@@ -43,12 +43,19 @@
 	/* vxWorks needs this as first entry for the Machine Check interrupt */
 	tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
  
+	/*
+	 * The RAM-boot version skips the SDRAM TLB (identified by EPN=0). This
+	 * entry is already configured for SDRAM via the JTAG debugger and mustn't
+	 * be re-initialized by this RAM-booting U-Boot version.
+	 */
+#ifndef CONFIG_SYS_RAMBOOT
 	/* TLB-entry for DDR SDRAM (Up to 2GB) */
 #ifdef CONFIG_4xx_DCACHE
 	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
 #else
 	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
 #endif
+#endif /* CONFIG_SYS_RAMBOOT */
  
 	/* TLB-entry for EBC */
 	tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
@@ -54,7 +54,8 @@
  ************************************************************************/
 phys_size_t initdram (int board_type)
 {
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)) || \
+    defined(CONFIG_NAND_SPL)
 	ulong speed = get_bus_freq(0);
  
 	mtsdram(DDR0_02, 0x00000000);
@@ -33,7 +33,9 @@
  
 DECLARE_GLOBAL_DATA_PTR;
  
+#if !defined(CONFIG_SYS_NO_FLASH)
 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+#endif
  
 extern void __ft_board_setup(void *blob, bd_t *bd);
 ulong flash_get_size(ulong base, int banknum);
  
  
  
@@ -122,16 +124,19 @@
  
 int misc_init_r(void)
 {
+#if !defined(CONFIG_SYS_NO_FLASH)
 	uint pbcr;
 	int size_val = 0;
-	u32 reg;
+#endif
 #ifdef CONFIG_440EPX
 	unsigned long usb2d0cr = 0;
 	unsigned long usb2phy0cr, usb2h0cr = 0;
 	unsigned long sdr0_pfc1;
 	char *act = getenv("usbact");
 #endif
+	u32 reg;
  
+#if !defined(CONFIG_SYS_NO_FLASH)
 	/* Re-do flash sizing to get full correct info */
  
 	/* adjust flash start and offset */
@@ -171,6 +176,7 @@
 			    CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
 			    &flash_info[0]);
 #endif
+#endif /* CONFIG_SYS_NO_FLASH */
  
 	/*
 	 * USB suff...
@@ -515,7 +521,7 @@
 }
 #endif /* CONFIG_POST */
  
-#if defined(CONFIG_NAND_U_BOOT)
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
 /*
  * On NAND-booting sequoia, we need to patch the chips select numbers
  * in the dtb (CS0 - NAND, CS3 - NOR)
+/*
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/ppc4xx/start.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
@@ -257,6 +257,14 @@
 	bl	board_init_f
 #endif
  
+#if defined(CONFIG_SYS_RAMBOOT)
+	/*
+	 * 4xx RAM-booting U-Boot image is started from offset 0
+	 */
+	.text
+	bl	_start_440
+#endif
+
 /*
  * 440 Startup -- on reset only the top 4k of the effective
  * address space is mapped in by an entry in the instruction
@@ -444,10 +452,17 @@
 	addis	r0,0,0x0000
 	li	r1,0x003f	/* 64 TLB entries */
 	mtctr	r1
-rsttlb:	tlbwe	r0,r1,0x0000	/* Invalidate all entries (V=0)*/
-	tlbwe	r0,r1,0x0001
-	tlbwe	r0,r1,0x0002
-	subi	r1,r1,0x0001
+	li	r4,0		/* Start with TLB #0 */
+rsttlb:
+#ifdef CONFIG_SYS_RAMBOOT
+	tlbre	r3,r4,0		/* Read contents from TLB word #0 to get EPN */
+	rlwinm.	r3,r3,0,0xfffffc00	/* Mask EPN */
+	beq	tlbnxt		/* Skip EPN=0 TLB, this is the SDRAM TLB */
+#endif
+	tlbwe	r0,r4,0		/* Invalidate all entries (V=0)*/
+	tlbwe	r0,r4,1
+	tlbwe	r0,r4,2
+tlbnxt:	addi	r4,r4,1		/* Next TLB */
 	bdnz	rsttlb
  
 	/*----------------------------------------------------------------*/
@@ -476,7 +491,13 @@
 	li	r4,0		/* TLB # */
  
 	addi	r5,r5,-4
-1:	lwzu	r0,4(r5)
+1:
+#ifdef CONFIG_SYS_RAMBOOT
+	tlbre	r3,r4,0		/* Read contents from TLB word #0 */
+	rlwinm.	r3,r3,0,0x00000200	/* Mask V (valid) bit */
+	bne	tlbnx2		/* Skip V=1 TLB, this is the SDRAM TLB */
+#endif
+	lwzu	r0,4(r5)
 	cmpwi	r0,0
 	beq	2f		/* 0 marks end */
 	lwzu	r1,4(r5)
@@ -484,7 +505,7 @@
 	tlbwe	r0,r4,0		/* TLB Word 0 */
 	tlbwe	r1,r4,1		/* TLB Word 1 */
 	tlbwe	r2,r4,2		/* TLB Word 2 */
-	addi	r4,r4,1		/* Next TLB */
+tlbnx2:	addi	r4,r4,1		/* Next TLB */
 	bdnz	1b
  
 	/*----------------------------------------------------------------*/
@@ -76,6 +76,17 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
  
+#if defined(CONFIG_SYS_RAMBOOT)
+/*
+ * Disable NOR FLASH commands on RAM-booting version. One main reason for this
+ * RAM-booting version is boards with NAND and without NOR. This image can
+ * be used for initial NAND programming.
+ */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#endif
+
 /*
  * Miscellaneous configurable options
  */
@@ -112,13 +112,26 @@
 /*
  * Environment
  */
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environ vars	*/
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+#define CONFIG_ENV_IS_IN_NAND		/* use NAND for environ vars	*/
+#define CONFIG_ENV_IS_EMBEDDED		/* use embedded environment	*/
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_IS_NOWHERE		/* Store env in memory only	*/
+#define CONFIG_ENV_SIZE		(8 << 10)
+/*
+ * In RAM-booting version, we have no environment storage. So we need to
+ * provide at least preliminary MAC addresses for the 4xx EMAC driver to
+ * register the interfaces. Those two addresses are generated via the
+ * tools/gen_eth_addr tool and should only be used in a closed laboratory
+ * environment.
+ */
+#define	CONFIG_ETHADDR		4a:56:49:22:3e:43
+#define	CONFIG_ETH1ADDR		02:93:53:d5:06:98
 #else
-#define CONFIG_ENV_IS_IN_NAND	1	/* use NAND for environ vars	*/
-#define CONFIG_ENV_IS_EMBEDDED	1	/* use embedded environment	*/
+#define CONFIG_ENV_IS_IN_FLASH		/* use FLASH for environ vars	*/
 #endif
  
+#if defined(CONFIG_CMD_FLASH)
 /*
  * FLASH related
  */
@@ -148,6 +161,7 @@
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 #endif
+#endif /* CONFIG_CMD_FLASH */
  
 /*
  * IPL (Initial Program Loader, integrated inside CPU)
@@ -211,7 +225,8 @@
  * DDR SDRAM
  */
 #define CONFIG_SYS_MBYTES_SDRAM        (256)	/* 256MB			*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
+    !defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_DDR_DATA_EYE		/* use DDR2 optimization	*/
 #endif
 #define CONFIG_SYS_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes	*/
@@ -306,7 +321,7 @@
  * overwrite part of the U-Boot image which is already loaded from NAND
  * to SDRAM.
  */
-#if defined(CONFIG_NAND_U_BOOT)
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_SYS_POST_MEMORY_ON	0
 #else
 #define CONFIG_SYS_POST_MEMORY_ON	CONFIG_SYS_POST_MEMORY
@@ -354,7 +369,8 @@
 /*
  * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
  */
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
+    !defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_SYS_NAND_CS		3	/* NAND chip connected to CSx	*/
 /* Memory Bank 0 (NOR-FLASH) initialization				*/
 #define CONFIG_SYS_EBC_PB0AP		0x03017200
...	...	@@ -1533,6 +1533,17 @@
1533	1533	@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
1534	1534	@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
1535	1535
	1536	+sequoia_ramboot_config \
	1537	+rainier_ramboot_config: unconfig
	1538	+ @mkdir -p $(obj)include $(obj)board/amcc/sequoia
	1539	+ @echo "#define CONFIG_SYS_RAMBOOT" > $(obj)include/config.h
	1540	+ @echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) \| \
	1541	+ tr '[:lower:]' '[:upper:]')" >> $(obj)include/config.h
	1542	+ @$(MKCONFIG) -n $@ -a sequoia ppc ppc4xx sequoia amcc
	1543	+ @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
	1544	+ @echo "LDSCRIPT = board/amcc/sequoia/u-boot-ram.lds" >> \
	1545	+ $(obj)board/amcc/sequoia/config.tmp
	1546	+
1536	1547	taihu_config: unconfig
1537	1548	@$(MKCONFIG) $(@:_config=) ppc ppc4xx taihu amcc
1538	1549
...	...	@@ -43,12 +43,19 @@
43	43	/* vxWorks needs this as first entry for the Machine Check interrupt */
44	44	tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R\|AC_W\|AC_X\|SA_G\|SA_I )
45	45
	46	+ /*
	47	+ * The RAM-boot version skips the SDRAM TLB (identified by EPN=0). This
	48	+ * entry is already configured for SDRAM via the JTAG debugger and mustn't
	49	+ * be re-initialized by this RAM-booting U-Boot version.
	50	+ */
	51	+#ifndef CONFIG_SYS_RAMBOOT
46	52	/* TLB-entry for DDR SDRAM (Up to 2GB) */
47	53	#ifdef CONFIG_4xx_DCACHE
48	54	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R\|AC_W\|AC_X\|SA_G)
49	55	#else
50	56	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R\|AC_W\|AC_X\|SA_G\|SA_I )
51	57	#endif
	58	+#endif /* CONFIG_SYS_RAMBOOT */
52	59
53	60	/* TLB-entry for EBC */
54	61	tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_R\|AC_W\|AC_X\|SA_G\|SA_I )
...	...	@@ -54,7 +54,8 @@
54	54	************************************************************************/
55	55	phys_size_t initdram (int board_type)
56	56	{
57		-#if !defined(CONFIG_NAND_U_BOOT) \|\| defined(CONFIG_NAND_SPL)
	57	+#if !(defined(CONFIG_NAND_U_BOOT) \|\| defined(CONFIG_SYS_RAMBOOT)) \|\| \
	58	+ defined(CONFIG_NAND_SPL)
58	59	ulong speed = get_bus_freq(0);
59	60
60	61	mtsdram(DDR0_02, 0x00000000);
...	...	@@ -33,7 +33,9 @@
33	33
34	34	DECLARE_GLOBAL_DATA_PTR;
35	35
	36	+#if !defined(CONFIG_SYS_NO_FLASH)
36	37	extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
	38	+#endif
37	39
38	40	extern void __ft_board_setup(void blob, bd_t bd);
39	41	ulong flash_get_size(ulong base, int banknum);
40	42
41	43
42	44
...	...	@@ -122,16 +124,19 @@
122	124
123	125	int misc_init_r(void)
124	126	{
	127	+#if !defined(CONFIG_SYS_NO_FLASH)
125	128	uint pbcr;
126	129	int size_val = 0;
127		- u32 reg;
	130	+#endif
128	131	#ifdef CONFIG_440EPX
129	132	unsigned long usb2d0cr = 0;
130	133	unsigned long usb2phy0cr, usb2h0cr = 0;
131	134	unsigned long sdr0_pfc1;
132	135	char *act = getenv("usbact");
133	136	#endif
	137	+ u32 reg;
134	138
	139	+#if !defined(CONFIG_SYS_NO_FLASH)
135	140	/* Re-do flash sizing to get full correct info */
136	141
137	142	/* adjust flash start and offset */
...	...	@@ -171,6 +176,7 @@
171	176	CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
172	177	&flash_info[0]);
173	178	#endif
	179	+#endif /* CONFIG_SYS_NO_FLASH */
174	180
175	181	/*
176	182	* USB suff...
...	...	@@ -515,7 +521,7 @@
515	521	}
516	522	#endif /* CONFIG_POST */
517	523
518		-#if defined(CONFIG_NAND_U_BOOT)
	524	+#if defined(CONFIG_NAND_U_BOOT) \|\| defined(CONFIG_SYS_RAMBOOT)
519	525	/*
520	526	* On NAND-booting sequoia, we need to patch the chips select numbers
521	527	* in the dtb (CS0 - NAND, CS3 - NOR)
	1	+/*
	2	+ * (C) Copyright 2009
	3	+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+OUTPUT_ARCH(powerpc)
	25	+SECTIONS
	26	+{
	27	+ /* Read-only sections, merged into text segment: */
	28	+ . = + SIZEOF_HEADERS;
	29	+ .interp : { *(.interp) }
	30	+ .hash : { *(.hash) }
	31	+ .dynsym : { *(.dynsym) }
	32	+ .dynstr : { *(.dynstr) }
	33	+ .rel.text : { *(.rel.text) }
	34	+ .rela.text : { *(.rela.text) }
	35	+ .rel.data : { *(.rel.data) }
	36	+ .rela.data : { *(.rela.data) }
	37	+ .rel.rodata : { *(.rel.rodata) }
	38	+ .rela.rodata : { *(.rela.rodata) }
	39	+ .rel.got : { *(.rel.got) }
	40	+ .rela.got : { *(.rela.got) }
	41	+ .rel.ctors : { *(.rel.ctors) }
	42	+ .rela.ctors : { *(.rela.ctors) }
	43	+ .rel.dtors : { *(.rel.dtors) }
	44	+ .rela.dtors : { *(.rela.dtors) }
	45	+ .rel.bss : { *(.rel.bss) }
	46	+ .rela.bss : { *(.rela.bss) }
	47	+ .rel.plt : { *(.rel.plt) }
	48	+ .rela.plt : { *(.rela.plt) }
	49	+ .init : { *(.init) }
	50	+ .plt : { *(.plt) }
	51	+ .text :
	52	+ {
	53	+ cpu/ppc4xx/start.o (.text)
	54	+
	55	+ *(.text)
	56	+ *(.fixup)
	57	+ *(.got1)
	58	+ }
	59	+ _etext = .;
	60	+ PROVIDE (etext = .);
	61	+ .rodata :
	62	+ {
	63	+ (SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata)))
	64	+ }
	65	+ .fini : { *(.fini) } =0
	66	+ .ctors : { *(.ctors) }
	67	+ .dtors : { *(.dtors) }
	68	+
	69	+ /* Read-write section, merged into data segment: */
	70	+ . = (. + 0x00FF) & 0xFFFFFF00;
	71	+ _erotext = .;
	72	+ PROVIDE (erotext = .);
	73	+ .reloc :
	74	+ {
	75	+ *(.got)
	76	+ _GOT2_TABLE_ = .;
	77	+ *(.got2)
	78	+ _FIXUP_TABLE_ = .;
	79	+ *(.fixup)
	80	+ }
	81	+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
	82	+ __fixup_entries = (. - _FIXUP_TABLE_)>>2;
	83	+
	84	+ .data :
	85	+ {
	86	+ *(.data)
	87	+ *(.data1)
	88	+ *(.sdata)
	89	+ *(.sdata2)
	90	+ *(.dynamic)
	91	+ CONSTRUCTORS
	92	+ }
	93	+ _edata = .;
	94	+ PROVIDE (edata = .);
	95	+
	96	+ . = .;
	97	+ __u_boot_cmd_start = .;
	98	+ .u_boot_cmd : { *(.u_boot_cmd) }
	99	+ __u_boot_cmd_end = .;
	100	+
	101	+
	102	+ . = .;
	103	+ __start___ex_table = .;
	104	+ __ex_table : { *(__ex_table) }
	105	+ __stop___ex_table = .;
	106	+
	107	+ . = ALIGN(256);
	108	+ __init_begin = .;
	109	+ .text.init : { *(.text.init) }
	110	+ .data.init : { *(.data.init) }
	111	+ . = ALIGN(256);
	112	+ __init_end = .;
	113	+
	114	+ __bss_start = .;
	115	+ .bss (NOLOAD) :
	116	+ {
	117	+ (.sbss) (.scommon)
	118	+ *(.dynbss)
	119	+ *(.bss)
	120	+ *(COMMON)
	121	+ . = ALIGN(4);
	122	+ }
	123	+
	124	+ _end = . ;
	125	+ PROVIDE (end = .);
	126	+}
...	...	@@ -257,6 +257,14 @@
257	257	bl board_init_f
258	258	#endif
259	259
	260	+#if defined(CONFIG_SYS_RAMBOOT)
	261	+ /*
	262	+ * 4xx RAM-booting U-Boot image is started from offset 0
	263	+ */
	264	+ .text
	265	+ bl _start_440
	266	+#endif
	267	+
260	268	/*
261	269	* 440 Startup -- on reset only the top 4k of the effective
262	270	* address space is mapped in by an entry in the instruction
...	...	@@ -444,10 +452,17 @@
444	452	addis r0,0,0x0000
445	453	li r1,0x003f /* 64 TLB entries */
446	454	mtctr r1
447		-rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
448		- tlbwe r0,r1,0x0001
449		- tlbwe r0,r1,0x0002
450		- subi r1,r1,0x0001
	455	+ li r4,0 /* Start with TLB #0 */
	456	+rsttlb:
	457	+#ifdef CONFIG_SYS_RAMBOOT
	458	+ tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */
	459	+ rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */
	460	+ beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */
	461	+#endif
	462	+ tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/
	463	+ tlbwe r0,r4,1
	464	+ tlbwe r0,r4,2
	465	+tlbnxt: addi r4,r4,1 /* Next TLB */
451	466	bdnz rsttlb
452	467
453	468	/----------------------------------------------------------------/
...	...	@@ -476,7 +491,13 @@
476	491	li r4,0 /* TLB # */
477	492
478	493	addi r5,r5,-4
479		-1: lwzu r0,4(r5)
	494	+1:
	495	+#ifdef CONFIG_SYS_RAMBOOT
	496	+ tlbre r3,r4,0 /* Read contents from TLB word #0 */
	497	+ rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */
	498	+ bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */
	499	+#endif
	500	+ lwzu r0,4(r5)
480	501	cmpwi r0,0
481	502	beq 2f /* 0 marks end */
482	503	lwzu r1,4(r5)
...	...	@@ -484,7 +505,7 @@
484	505	tlbwe r0,r4,0 /* TLB Word 0 */
485	506	tlbwe r1,r4,1 /* TLB Word 1 */
486	507	tlbwe r2,r4,2 /* TLB Word 2 */
487		- addi r4,r4,1 /* Next TLB */
	508	+tlbnx2: addi r4,r4,1 /* Next TLB */
488	509	bdnz 1b
489	510
490	511	/----------------------------------------------------------------/
...	...	@@ -76,6 +76,17 @@
76	76	#define CONFIG_CMD_PING
77	77	#define CONFIG_CMD_REGINFO
78	78
	79	+#if defined(CONFIG_SYS_RAMBOOT)
	80	+/*
	81	+ * Disable NOR FLASH commands on RAM-booting version. One main reason for this
	82	+ * RAM-booting version is boards with NAND and without NOR. This image can
	83	+ * be used for initial NAND programming.
	84	+ */
	85	+#define CONFIG_SYS_NO_FLASH
	86	+#undef CONFIG_CMD_FLASH
	87	+#undef CONFIG_CMD_IMLS
	88	+#endif
	89	+
79	90	/*
80	91	* Miscellaneous configurable options
81	92	*/
...	...	@@ -112,13 +112,26 @@
112	112	/*
113	113	* Environment
114	114	*/
115		-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
116		-#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */
	115	+#if defined(CONFIG_NAND_U_BOOT) \|\| defined(CONFIG_NAND_SPL)
	116	+#define CONFIG_ENV_IS_IN_NAND /* use NAND for environ vars */
	117	+#define CONFIG_ENV_IS_EMBEDDED /* use embedded environment */
	118	+#elif defined(CONFIG_SYS_RAMBOOT)
	119	+#define CONFIG_ENV_IS_NOWHERE /* Store env in memory only */
	120	+#define CONFIG_ENV_SIZE (8 << 10)
	121	+/*
	122	+ * In RAM-booting version, we have no environment storage. So we need to
	123	+ * provide at least preliminary MAC addresses for the 4xx EMAC driver to
	124	+ * register the interfaces. Those two addresses are generated via the
	125	+ * tools/gen_eth_addr tool and should only be used in a closed laboratory
	126	+ * environment.
	127	+ */
	128	+#define CONFIG_ETHADDR 4a:56:49:22:3e:43
	129	+#define CONFIG_ETH1ADDR 02:93:53:d5:06:98
117	130	#else
118		-#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environ vars */
119		-#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
	131	+#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environ vars */
120	132	#endif
121	133
	134	+#if defined(CONFIG_CMD_FLASH)
122	135	/*
123	136	* FLASH related
124	137	*/
...	...	@@ -148,6 +161,7 @@
148	161	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
149	162	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
150	163	#endif
	164	+#endif /* CONFIG_CMD_FLASH */
151	165
152	166	/*
153	167	* IPL (Initial Program Loader, integrated inside CPU)
...	...	@@ -211,7 +225,8 @@
211	225	* DDR SDRAM
212	226	*/
213	227	#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
214		-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
	228	+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
	229	+ !defined(CONFIG_SYS_RAMBOOT)
215	230	#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
216	231	#endif
217	232	#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
...	...	@@ -306,7 +321,7 @@
306	321	* overwrite part of the U-Boot image which is already loaded from NAND
307	322	* to SDRAM.
308	323	*/
309		-#if defined(CONFIG_NAND_U_BOOT)
	324	+#if defined(CONFIG_NAND_U_BOOT) \|\| defined(CONFIG_SYS_RAMBOOT)
310	325	#define CONFIG_SYS_POST_MEMORY_ON 0
311	326	#else
312	327	#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
...	...	@@ -354,7 +369,8 @@
354	369	/*
355	370	* On Sequoia CS0 and CS3 are switched when configuring for NAND booting
356	371	*/
357		-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
	372	+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
	373	+ !defined(CONFIG_SYS_RAMBOOT)
358	374	#define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
359	375	/* Memory Bank 0 (NOR-FLASH) initialization */
360	376	#define CONFIG_SYS_EBC_PB0AP 0x03017200