* Fix ICU862 environment problem

* Fix RAM size detection for RMU board * Implement "reset" for MGT5100/MPC5200 systems

* Fix ICU862 environment problem
* Fix RAM size detection for RMU board * Implement "reset" for MGT5100/MPC5200 systems
wdenk
1 parent e0ac62d798
Showing 11 changed files with 53 additions and 53 deletions Side-by-side Diff
CHANGELOG
board/icecube/icecube.c
board/icu862/u-boot.lds
board/rmu/rmu.c
cpu/mpc5xxx/cpu.c
cpu/mpc8xx/start.S
include/configs/ICU862.h
include/configs/IceCube.h
include/configs/rmu.h
include/mpc5xxx.h
include/version.h
 ======================================================================
-Changes for U-Boot 0.4.5:
+Changes for U-Boot 0.4.7:
 ======================================================================
  
+* Fix ICU862 environment problem
+
+* Fix RAM size detection for RMU board
+
+* Implement "reset" for MGT5100/MPC5200 systems
+
+======================================================================
+Changes for U-Boot 0.4.6:
+======================================================================
+
 * Make Ethernet autonegotiation on INCA-IP work for all clock rates;
   allow selection of clock frequency as "make" target
  
@@ -13,6 +23,10 @@
  
 * Patch by Richard Woodruff, 8 Aug 2003:
   Allow crc32 to be used at address 0x000 (crc32_no_comp, too).
+
+======================================================================
+Changes for U-Boot 0.4.5:
+======================================================================
  
 * Update for TQM board defaults:
   disable clocks_in_mhz, enable boot count limit
@@ -25,6 +25,7 @@
 #include <mpc5xxx.h>
 #include <pci.h>
  
+#ifndef CFG_RAMBOOT
 static long int dram_size(long int *base, long int maxsize)
 {
 	volatile long int *addr;
  
  
@@ -86,11 +87,14 @@
 	/* normal operation */
 	*(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000 | hi_addr_bit;
 }
+#endif
  
 long int initdram (int board_type)
 {
-	ulong test1, test2, dramsize = 0;
+	ulong dramsize = 0;
 #ifndef CFG_RAMBOOT
+	ulong test1, test2;
+
 	/* configure SDRAM start/end */
 #if defined(CONFIG_MPC5200)
 	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
  
@@ -133,8 +137,11 @@
 #else
 #ifdef CONFIG_MGT5100
 	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
+	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
+#else
+	dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
 #endif
-#endif
+#endif /* CFG_RAMBOOT */
 	/* return total ram size */
 	return dramsize;
 }
@@ -136,11 +136,6 @@
    *(.bss)
    *(COMMON)
   }
-  . = ALIGN(256 * 1024);
-  .ppcenv	:
-  {
-    common/environment.o (.ppcenv)
-  }
   _end = . ;
   PROVIDE (end = .);
 }
@@ -96,7 +96,7 @@
 {
     volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
     volatile memctl8xx_t *memctl = &immap->im_memctl;
-    long int size10 ;
+    long int size9 ;
  
     upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
  
@@ -109,7 +109,7 @@
     memctl->memc_or1 = CFG_OR1_PRELIM;
     memctl->memc_br1 = CFG_BR1_PRELIM;
  
-    memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
+    memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
  
     udelay(200);
  
  
  
@@ -122,13 +122,20 @@
  
     udelay (1000);
  
-	/* Check Bank 0 Memory Size
-	 * try 10 column mode
+	/* Check Bank 0 Memory Size,
+	 * 9 column mode
 	 */
  
-	size10 = dram_size (CFG_MAMR_10COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ;
+	size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ;
  
-    return (size10);
+	/*
+	 * Final mapping:
+	 */
+
+	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	udelay (1000);
+
+    return (size9);
 }
  
 /* ------------------------------------------------------------------------- */
@@ -54,31 +54,17 @@
 int
 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-	ulong msr, addr;
-
-	*(vu_long *)MPC5XXX_CDM_SRESET &= ~(1 << 16);	/* Checkstop Reset enable */
-
+	ulong msr;
 	/* Interrupts and MMU off */
 	__asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
  
 	msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
 	__asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
  
-	/*
-	 * Trying to execute the next instruction at a non-existing address
-	 * should cause a machine check, resulting in reset
-	 */
-#ifdef CFG_RESET_ADDRESS
-	addr = CFG_RESET_ADDRESS;
-#else
-	/*
-	 * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
-	 * - sizeof (ulong) is usually a valid address. Better pick an address
-	 * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
-	 */
-	addr = CFG_MONITOR_BASE - sizeof (ulong);
-#endif
-	((void (*)(void)) addr) ();
+	/* Charge the watchdog timer */
+	*(vu_long *)(MPC5XXX_GPT0_COUNTER) = 0xf;
+	*(vu_long *)(MPC5XXX_GPT0_ENABLE) = 0x9004; /* wden|ce|timer_ms */
+
 	return 1;
  
 }
@@ -76,9 +76,6 @@
 	GOT_ENTRY(__init_end)
 	GOT_ENTRY(_end)
 	GOT_ENTRY(__bss_start)
-#if defined(CONFIG_ICU862)
-	GOT_ENTRY(environment)
-#endif
 	END_GOT
  
 /*
  
@@ -617,16 +614,7 @@
 	 * Now clear BSS segment
 	 */
 	lwz	r3,GOT(__bss_start)
-#if defined(CONFIG_ICU862)
-	/*
-	 * For the FADS - the environment is the very last item in flash.
-	 * The real .bss stops just before environment starts, so only
-	 * clear up to that point.
-	 */
-	lwz	r4,GOT(environment)
-#else
 	lwz	r4,GOT(_end)
-#endif
  
 	cmplw	0, r3, r4
 	beq	6f
@@ -196,7 +196,7 @@
 #define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
 #endif
 #else
-#define CFG_MONITOR_LEN (272 << 10) /* Reserve 272 kB for Monitor */
+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
 #endif
 #define CFG_MONITOR_BASE	TEXT_BASE
 #define	CFG_MALLOC_LEN		(256 << 10)	/* Reserve 256 kB for malloc()	*/
@@ -131,9 +131,7 @@
  */
 #define CFG_MBAR		0xf0000000
 #define CFG_SDRAM_BASE		0x00000000
-#ifdef CONFIG_MPC5200
 #define CFG_DEFAULT_MBAR	0x80000000
-#endif
  
 /* Use SRAM until RAM will be available */
 #define CFG_INIT_RAM_ADDR	MPC5XXX_SRAM
@@ -291,12 +291,12 @@
  *
  */
 #define SDRAM_BASE_PRELIM	0x00000000	/* SDRAM base	*/
-#define	SDRAM_MAX_SIZE		0x01000000	/* max 16 MB */
+#define	SDRAM_MAX_SIZE		0x08000000	/* max 128 MB */
  
 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
 #define CFG_OR_TIMING_SDRAM	0x00000E00
  
-#define CFG_OR1_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_OR1_PRELIM	(0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */
 #define CFG_BR1_PRELIM	((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  
 /* RPXLITE mem setting */
@@ -321,8 +321,8 @@
  * MAMR settings for SDRAM
  */
  
-/* 10 column SDRAM */
-#define CFG_MAMR_10COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
  
@@ -78,6 +78,7 @@
 #define MPC5XXX_CDM		(CFG_MBAR + 0x0200)
 #define MPC5XXX_LPB		(CFG_MBAR + 0x0300)
 #define MPC5XXX_ICTL		(CFG_MBAR + 0x0500)
+#define MPC5XXX_GPT		(CFG_MBAR + 0x0600)
 #define MPC5XXX_GPIO		(CFG_MBAR + 0x0b00)
 #define MPC5XXX_PCI		(CFG_MBAR + 0x0d00)
 #define MPC5XXX_SDMA		(CFG_MBAR + 0x1200)
@@ -182,6 +183,10 @@
 #define MPC5XXX_ICTL_MAIN_STS	(MPC5XXX_ICTL + 0x002c)
 #define MPC5XXX_ICTL_PER_STS	(MPC5XXX_ICTL + 0x0030)
 #define MPC5XXX_ICTL_BUS_STS	(MPC5XXX_ICTL + 0x0038)
+
+/* General Purpose Timers registers */
+#define MPC5XXX_GPT0_ENABLE		(MPC5XXX_GPT + 0x0)
+#define MPC5XXX_GPT0_COUNTER		(MPC5XXX_GPT + 0x4)
  
 /* Programmable Serial Controller (PSC) status register bits */
 #define PSC_SR_CDE		0x0080
@@ -24,7 +24,7 @@
 #ifndef	__VERSION_H__
 #define	__VERSION_H__
  
-#define	U_BOOT_VERSION	"U-Boot 0.4.6"
+#define	U_BOOT_VERSION	"U-Boot 0.4.7"
  
 #endif	/* __VERSION_H__ */
1	1	======================================================================
2		-Changes for U-Boot 0.4.5:
	2	+Changes for U-Boot 0.4.7:
3	3	======================================================================
4	4
	5	+* Fix ICU862 environment problem
	6	+
	7	+* Fix RAM size detection for RMU board
	8	+
	9	+* Implement "reset" for MGT5100/MPC5200 systems
	10	+
	11	+======================================================================
	12	+Changes for U-Boot 0.4.6:
	13	+======================================================================
	14	+
5	15	* Make Ethernet autonegotiation on INCA-IP work for all clock rates;
6	16	allow selection of clock frequency as "make" target
7	17
...	...	@@ -13,6 +23,10 @@
13	23
14	24	* Patch by Richard Woodruff, 8 Aug 2003:
15	25	Allow crc32 to be used at address 0x000 (crc32_no_comp, too).
	26	+
	27	+======================================================================
	28	+Changes for U-Boot 0.4.5:
	29	+======================================================================
16	30
17	31	* Update for TQM board defaults:
18	32	disable clocks_in_mhz, enable boot count limit
...	...	@@ -25,6 +25,7 @@
25	25	#include <mpc5xxx.h>
26	26	#include <pci.h>
27	27
	28	+#ifndef CFG_RAMBOOT
28	29	static long int dram_size(long int *base, long int maxsize)
29	30	{
30	31	volatile long int *addr;
31	32
32	33
...	...	@@ -86,11 +87,14 @@
86	87	/* normal operation */
87	88	(vu_long )MPC5XXX_SDRAM_CTRL = 0x504f0000 \| hi_addr_bit;
88	89	}
	90	+#endif
89	91
90	92	long int initdram (int board_type)
91	93	{
92		- ulong test1, test2, dramsize = 0;
	94	+ ulong dramsize = 0;
93	95	#ifndef CFG_RAMBOOT
	96	+ ulong test1, test2;
	97	+
94	98	/* configure SDRAM start/end */
95	99	#if defined(CONFIG_MPC5200)
96	100	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
97	101
...	...	@@ -133,8 +137,11 @@
133	137	#else
134	138	#ifdef CONFIG_MGT5100
135	139	(vu_long )MPC5XXX_ADDECR \|= (1 << 22); /* Enable SDRAM */
	140	+ dramsize = (((vu_long )MPC5XXX_SDRAM_STOP + 1) << 15);
	141	+#else
	142	+ dramsize = ((1 << ((vu_long )MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
136	143	#endif
137		-#endif
	144	+#endif /* CFG_RAMBOOT */
138	145	/* return total ram size */
139	146	return dramsize;
140	147	}
...	...	@@ -136,11 +136,6 @@
136	136	*(.bss)
137	137	*(COMMON)
138	138	}
139		- . = ALIGN(256 * 1024);
140		- .ppcenv :
141		- {
142		- common/environment.o (.ppcenv)
143		- }
144	139	_end = . ;
145	140	PROVIDE (end = .);
146	141	}
...	...	@@ -96,7 +96,7 @@
96	96	{
97	97	volatile immap_t immap = (immap_t )CFG_IMMR;
98	98	volatile memctl8xx_t *memctl = &immap->im_memctl;
99		- long int size10 ;
	99	+ long int size9 ;
100	100
101	101	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
102	102
...	...	@@ -109,7 +109,7 @@
109	109	memctl->memc_or1 = CFG_OR1_PRELIM;
110	110	memctl->memc_br1 = CFG_BR1_PRELIM;
111	111
112		- memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
	112	+ memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
113	113
114	114	udelay(200);
115	115
116	116
117	117
...	...	@@ -122,13 +122,20 @@
122	122
123	123	udelay (1000);
124	124
125		- /* Check Bank 0 Memory Size
126		- * try 10 column mode
	125	+ /* Check Bank 0 Memory Size,
	126	+ * 9 column mode
127	127	*/
128	128
129		- size10 = dram_size (CFG_MAMR_10COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ;
	129	+ size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ;
130	130
131		- return (size10);
	131	+ /*
	132	+ * Final mapping:
	133	+ */
	134	+
	135	+ memctl->memc_or1 = ((-size9) & 0xFFFF0000) \| CFG_OR_TIMING_SDRAM;
	136	+ udelay (1000);
	137	+
	138	+ return (size9);
132	139	}
133	140
134	141	/* ------------------------------------------------------------------------- */
...	...	@@ -54,31 +54,17 @@
54	54	int
55	55	do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
56	56	{
57		- ulong msr, addr;
58		-
59		- (vu_long )MPC5XXX_CDM_SRESET &= ~(1 << 16); /* Checkstop Reset enable */
60		-
	57	+ ulong msr;
61	58	/* Interrupts and MMU off */
62	59	__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
63	60
64	61	msr &= ~(MSR_ME \| MSR_EE \| MSR_IR \| MSR_DR);
65	62	__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
66	63
67		- /*
68		- * Trying to execute the next instruction at a non-existing address
69		- * should cause a machine check, resulting in reset
70		- */
71		-#ifdef CFG_RESET_ADDRESS
72		- addr = CFG_RESET_ADDRESS;
73		-#else
74		- /*
75		- * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
76		- * - sizeof (ulong) is usually a valid address. Better pick an address
77		- * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
78		- */
79		- addr = CFG_MONITOR_BASE - sizeof (ulong);
80		-#endif
81		- ((void (*)(void)) addr) ();
	64	+ /* Charge the watchdog timer */
	65	+ (vu_long )(MPC5XXX_GPT0_COUNTER) = 0xf;
	66	+ (vu_long )(MPC5XXX_GPT0_ENABLE) = 0x9004; /* wden\|ce\|timer_ms */
	67	+
82	68	return 1;
83	69
84	70	}
...	...	@@ -76,9 +76,6 @@
76	76	GOT_ENTRY(__init_end)
77	77	GOT_ENTRY(_end)
78	78	GOT_ENTRY(__bss_start)
79		-#if defined(CONFIG_ICU862)
80		- GOT_ENTRY(environment)
81		-#endif
82	79	END_GOT
83	80
84	81	/*
85	82
...	...	@@ -617,16 +614,7 @@
617	614	* Now clear BSS segment
618	615	*/
619	616	lwz r3,GOT(__bss_start)
620		-#if defined(CONFIG_ICU862)
621		- /*
622		- * For the FADS - the environment is the very last item in flash.
623		- * The real .bss stops just before environment starts, so only
624		- * clear up to that point.
625		- */
626		- lwz r4,GOT(environment)
627		-#else
628	617	lwz r4,GOT(_end)
629		-#endif
630	618
631	619	cmplw 0, r3, r4
632	620	beq 6f
...	...	@@ -196,7 +196,7 @@
196	196	#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
197	197	#endif
198	198	#else
199		-#define CFG_MONITOR_LEN (272 << 10) /* Reserve 272 kB for Monitor */
	199	+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
200	200	#endif
201	201	#define CFG_MONITOR_BASE TEXT_BASE
202	202	#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
...	...	@@ -131,9 +131,7 @@
131	131	*/
132	132	#define CFG_MBAR 0xf0000000
133	133	#define CFG_SDRAM_BASE 0x00000000
134		-#ifdef CONFIG_MPC5200
135	134	#define CFG_DEFAULT_MBAR 0x80000000
136		-#endif
137	135
138	136	/* Use SRAM until RAM will be available */
139	137	#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
...	...	@@ -291,12 +291,12 @@
291	291	*
292	292	*/
293	293	#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
294		-#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
	294	+#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */
295	295
296	296	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
297	297	#define CFG_OR_TIMING_SDRAM 0x00000E00
298	298
299		-#define CFG_OR1_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_SDRAM )
	299	+#define CFG_OR1_PRELIM (0xF0000000 \| CFG_OR_TIMING_SDRAM ) /* map 256 MB */
300	300	#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
301	301
302	302	/* RPXLITE mem setting */
...	...	@@ -321,8 +321,8 @@
321	321	* MAMR settings for SDRAM
322	322	*/
323	323
324		-/* 10 column SDRAM */
325		-#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
	324	+/* 9 column SDRAM */
	325	+#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
326	326	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
327	327	MAMR_RLFA_16X \| MAMR_WLFA_16X \| MAMR_TLFA_16X)
328	328
...	...	@@ -78,6 +78,7 @@
78	78	#define MPC5XXX_CDM (CFG_MBAR + 0x0200)
79	79	#define MPC5XXX_LPB (CFG_MBAR + 0x0300)
80	80	#define MPC5XXX_ICTL (CFG_MBAR + 0x0500)
	81	+#define MPC5XXX_GPT (CFG_MBAR + 0x0600)
81	82	#define MPC5XXX_GPIO (CFG_MBAR + 0x0b00)
82	83	#define MPC5XXX_PCI (CFG_MBAR + 0x0d00)
83	84	#define MPC5XXX_SDMA (CFG_MBAR + 0x1200)
...	...	@@ -182,6 +183,10 @@
182	183	#define MPC5XXX_ICTL_MAIN_STS (MPC5XXX_ICTL + 0x002c)
183	184	#define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030)
184	185	#define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038)
	186	+
	187	+/* General Purpose Timers registers */
	188	+#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0)
	189	+#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4)
185	190
186	191	/* Programmable Serial Controller (PSC) status register bits */
187	192	#define PSC_SR_CDE 0x0080