Commit de621ae63b27ec306d1148a17f82f467711524a7
1 parent
3c86f1ca3a
Exists in
smarc-m6.0.1_2.1.0-ga
Fix Fastboot Download Bugs
Showing 2 changed files with 4 additions and 6 deletions Inline Diff
board/embedian/smarcfimx6/smarcfimx6.c
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. | 2 | * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. |
| 3 | * | 3 | * |
| 4 | * Author: Fabio Estevam <fabio.estevam@freescale.com> | 4 | * Author: Fabio Estevam <fabio.estevam@freescale.com> |
| 5 | * | 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ | 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | #include <asm/arch/clock.h> | 9 | #include <asm/arch/clock.h> |
| 10 | #include <asm/arch/imx-regs.h> | 10 | #include <asm/arch/imx-regs.h> |
| 11 | #include <asm/arch/iomux.h> | 11 | #include <asm/arch/iomux.h> |
| 12 | #include <asm/arch/mx6-pins.h> | 12 | #include <asm/arch/mx6-pins.h> |
| 13 | #include <asm/errno.h> | 13 | #include <asm/errno.h> |
| 14 | #include <asm/gpio.h> | 14 | #include <asm/gpio.h> |
| 15 | #include <asm/imx-common/mxc_i2c.h> | 15 | #include <asm/imx-common/mxc_i2c.h> |
| 16 | #include <asm/imx-common/iomux-v3.h> | 16 | #include <asm/imx-common/iomux-v3.h> |
| 17 | #include <asm/imx-common/boot_mode.h> | 17 | #include <asm/imx-common/boot_mode.h> |
| 18 | #include <asm/imx-common/video.h> | 18 | #include <asm/imx-common/video.h> |
| 19 | #include <mmc.h> | 19 | #include <mmc.h> |
| 20 | #include <fsl_esdhc.h> | 20 | #include <fsl_esdhc.h> |
| 21 | #include <miiphy.h> | 21 | #include <miiphy.h> |
| 22 | #include <netdev.h> | 22 | #include <netdev.h> |
| 23 | 23 | ||
| 24 | #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) | 24 | #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) |
| 25 | #include <lcd.h> | 25 | #include <lcd.h> |
| 26 | #include <mxc_epdc_fb.h> | 26 | #include <mxc_epdc_fb.h> |
| 27 | #endif | 27 | #endif |
| 28 | #include <asm/arch/mxc_hdmi.h> | 28 | #include <asm/arch/mxc_hdmi.h> |
| 29 | #include <asm/arch/crm_regs.h> | 29 | #include <asm/arch/crm_regs.h> |
| 30 | #include <asm/io.h> | 30 | #include <asm/io.h> |
| 31 | #include <asm/arch/sys_proto.h> | 31 | #include <asm/arch/sys_proto.h> |
| 32 | #include <pwm.h> | 32 | #include <pwm.h> |
| 33 | #include <i2c.h> | 33 | #include <i2c.h> |
| 34 | #include <ipu_pixfmt.h> | 34 | #include <ipu_pixfmt.h> |
| 35 | #include <linux/fb.h> | 35 | #include <linux/fb.h> |
| 36 | #include <asm/arch/mx6-ddr.h> | 36 | #include <asm/arch/mx6-ddr.h> |
| 37 | #include <usb.h> | 37 | #include <usb.h> |
| 38 | 38 | ||
| 39 | #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) | 39 | #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) |
| 40 | #include <lcd.h> | 40 | #include <lcd.h> |
| 41 | #include <mxc_epdc_fb.h> | 41 | #include <mxc_epdc_fb.h> |
| 42 | #endif | 42 | #endif |
| 43 | #include "smarcfimx6.h" | 43 | #include "smarcfimx6.h" |
| 44 | #ifdef CONFIG_CMD_SATA | 44 | #ifdef CONFIG_CMD_SATA |
| 45 | #include <asm/imx-common/sata.h> | 45 | #include <asm/imx-common/sata.h> |
| 46 | #endif | 46 | #endif |
| 47 | #ifdef CONFIG_FSL_FASTBOOT | 47 | #ifdef CONFIG_FSL_FASTBOOT |
| 48 | #include <fsl_fastboot.h> | 48 | #include <fsl_fastboot.h> |
| 49 | #ifdef CONFIG_ANDROID_RECOVERY | 49 | #ifdef CONFIG_ANDROID_RECOVERY |
| 50 | #include <recovery.h> | 50 | #include <recovery.h> |
| 51 | #endif | 51 | #endif |
| 52 | #endif /*CONFIG_FSL_FASTBOOT*/ | 52 | #endif /*CONFIG_FSL_FASTBOOT*/ |
| 53 | 53 | ||
| 54 | DECLARE_GLOBAL_DATA_PTR; | 54 | DECLARE_GLOBAL_DATA_PTR; |
| 55 | 55 | ||
| 56 | #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ | 56 | #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
| 57 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ | 57 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ |
| 58 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | 58 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| 59 | 59 | ||
| 60 | #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ | 60 | #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ |
| 61 | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ | 61 | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ |
| 62 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | 62 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| 63 | 63 | ||
| 64 | #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ | 64 | #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
| 65 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) | 65 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
| 66 | 66 | ||
| 67 | #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ | 67 | #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ |
| 68 | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) | 68 | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) |
| 69 | 69 | ||
| 70 | #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_HIGH | \ | 70 | #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_HIGH | \ |
| 71 | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) | 71 | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) |
| 72 | 72 | ||
| 73 | #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ | 73 | #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| 74 | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ | 74 | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
| 75 | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ | 75 | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ |
| 76 | PAD_CTL_ODE | PAD_CTL_SRE_FAST) | 76 | PAD_CTL_ODE | PAD_CTL_SRE_FAST) |
| 77 | 77 | ||
| 78 | #define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ | 78 | #define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ |
| 79 | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) | 79 | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
| 80 | 80 | ||
| 81 | #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ | 81 | #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| 82 | PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ | 82 | PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ |
| 83 | PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | 83 | PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
| 84 | 84 | ||
| 85 | #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ | 85 | #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \ |
| 86 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ | 86 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ |
| 87 | PAD_CTL_SRE_SLOW) | 87 | PAD_CTL_SRE_SLOW) |
| 88 | 88 | ||
| 89 | #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) | 89 | #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) |
| 90 | 90 | ||
| 91 | #define DISP0_PWR_EN IMX_GPIO_NR(1, 02) | 91 | #define DISP0_PWR_EN IMX_GPIO_NR(1, 02) |
| 92 | 92 | ||
| 93 | #define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ | 93 | #define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ |
| 94 | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) | 94 | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
| 95 | 95 | ||
| 96 | #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) | 96 | #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm) |
| 97 | 97 | ||
| 98 | /* | 98 | /* |
| 99 | * Read header information from EEPROM into global structure. | 99 | * Read header information from EEPROM into global structure. |
| 100 | */ | 100 | */ |
| 101 | static int read_eeprom(struct smarcfimx6_id *header) | 101 | static int read_eeprom(struct smarcfimx6_id *header) |
| 102 | { | 102 | { |
| 103 | /* Check if baseboard eeprom is available */ | 103 | /* Check if baseboard eeprom is available */ |
| 104 | if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { | 104 | if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { |
| 105 | puts("Could not probe the EEPROM; something fundamentally " | 105 | puts("Could not probe the EEPROM; something fundamentally " |
| 106 | "wrong on the I2C bus.\n"); | 106 | "wrong on the I2C bus.\n"); |
| 107 | return -ENODEV; | 107 | return -ENODEV; |
| 108 | } | 108 | } |
| 109 | 109 | ||
| 110 | /* read the eeprom using i2c */ | 110 | /* read the eeprom using i2c */ |
| 111 | if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, | 111 | if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, |
| 112 | sizeof(struct smarcfimx6_id))) { | 112 | sizeof(struct smarcfimx6_id))) { |
| 113 | puts("Could not read the EEPROM; something fundamentally" | 113 | puts("Could not read the EEPROM; something fundamentally" |
| 114 | " wrong on the I2C bus.\n"); | 114 | " wrong on the I2C bus.\n"); |
| 115 | return -EIO; | 115 | return -EIO; |
| 116 | } | 116 | } |
| 117 | 117 | ||
| 118 | if (header->magic != 0xEE3355AA) { | 118 | if (header->magic != 0xEE3355AA) { |
| 119 | /* | 119 | /* |
| 120 | * read the eeprom using i2c again, | 120 | * read the eeprom using i2c again, |
| 121 | * but use only a 1 byte address | 121 | * but use only a 1 byte address |
| 122 | */ | 122 | */ |
| 123 | if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, | 123 | if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, |
| 124 | sizeof(struct smarcfimx6_id))) { | 124 | sizeof(struct smarcfimx6_id))) { |
| 125 | puts("Could not read the EEPROM; something " | 125 | puts("Could not read the EEPROM; something " |
| 126 | "fundamentally wrong on the I2C bus.\n"); | 126 | "fundamentally wrong on the I2C bus.\n"); |
| 127 | return -EIO; | 127 | return -EIO; |
| 128 | } | 128 | } |
| 129 | 129 | ||
| 130 | if (header->magic != 0xEE3355AA) { | 130 | if (header->magic != 0xEE3355AA) { |
| 131 | printf("Incorrect magic number (0x%x) in EEPROM\n", | 131 | printf("Incorrect magic number (0x%x) in EEPROM\n", |
| 132 | header->magic); | 132 | header->magic); |
| 133 | return -EINVAL; | 133 | return -EINVAL; |
| 134 | } | 134 | } |
| 135 | } | 135 | } |
| 136 | 136 | ||
| 137 | return 0; | 137 | return 0; |
| 138 | } | 138 | } |
| 139 | 139 | ||
| 140 | /*I2C1 I2C_PM*/ | 140 | /*I2C1 I2C_PM*/ |
| 141 | struct i2c_pads_info i2c_pad_info1 = { | 141 | struct i2c_pads_info i2c_pad_info1 = { |
| 142 | .scl = { | 142 | .scl = { |
| 143 | .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | I2C_PAD, | 143 | .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | I2C_PAD, |
| 144 | .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | I2C_PAD, | 144 | .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | I2C_PAD, |
| 145 | .gp = IMX_GPIO_NR(3, 21) | 145 | .gp = IMX_GPIO_NR(3, 21) |
| 146 | }, | 146 | }, |
| 147 | .sda = { | 147 | .sda = { |
| 148 | .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | I2C_PAD, | 148 | .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | I2C_PAD, |
| 149 | .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | I2C_PAD, | 149 | .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | I2C_PAD, |
| 150 | .gp = IMX_GPIO_NR(3, 28) | 150 | .gp = IMX_GPIO_NR(3, 28) |
| 151 | } | 151 | } |
| 152 | }; | 152 | }; |
| 153 | 153 | ||
| 154 | /* I2C2 HDMI */ | 154 | /* I2C2 HDMI */ |
| 155 | struct i2c_pads_info i2c_pad_info2 = { | 155 | struct i2c_pads_info i2c_pad_info2 = { |
| 156 | .scl = { | 156 | .scl = { |
| 157 | .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, | 157 | .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, |
| 158 | .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, | 158 | .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, |
| 159 | .gp = IMX_GPIO_NR(4, 12) | 159 | .gp = IMX_GPIO_NR(4, 12) |
| 160 | }, | 160 | }, |
| 161 | .sda = { | 161 | .sda = { |
| 162 | .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, | 162 | .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, |
| 163 | .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, | 163 | .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, |
| 164 | .gp = IMX_GPIO_NR(4, 13) | 164 | .gp = IMX_GPIO_NR(4, 13) |
| 165 | } | 165 | } |
| 166 | }; | 166 | }; |
| 167 | 167 | ||
| 168 | /* I2C3 TCA9546APWR */ | 168 | /* I2C3 TCA9546APWR */ |
| 169 | struct i2c_pads_info i2c_pad_info3 = { | 169 | struct i2c_pads_info i2c_pad_info3 = { |
| 170 | .scl = { | 170 | .scl = { |
| 171 | .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | I2C_PAD, | 171 | .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | I2C_PAD, |
| 172 | .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | I2C_PAD, | 172 | .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | I2C_PAD, |
| 173 | .gp = IMX_GPIO_NR(3, 17) | 173 | .gp = IMX_GPIO_NR(3, 17) |
| 174 | }, | 174 | }, |
| 175 | .sda = { | 175 | .sda = { |
| 176 | .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | I2C_PAD, | 176 | .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | I2C_PAD, |
| 177 | .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | I2C_PAD, | 177 | .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | I2C_PAD, |
| 178 | .gp = IMX_GPIO_NR(3, 18) | 178 | .gp = IMX_GPIO_NR(3, 18) |
| 179 | } | 179 | } |
| 180 | }; | 180 | }; |
| 181 | 181 | ||
| 182 | int dram_init(void) | 182 | int dram_init(void) |
| 183 | { | 183 | { |
| 184 | gd->ram_size = imx_ddr_size(); | 184 | gd->ram_size = imx_ddr_size(); |
| 185 | 185 | ||
| 186 | return 0; | 186 | return 0; |
| 187 | } | 187 | } |
| 188 | 188 | ||
| 189 | /* SER0/UART1 */ | 189 | /* SER0/UART1 */ |
| 190 | iomux_v3_cfg_t const uart1_pads[] = { | 190 | iomux_v3_cfg_t const uart1_pads[] = { |
| 191 | MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | 191 | MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 192 | MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | 192 | MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 193 | MX6_PAD_EIM_D20__UART1_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | 193 | MX6_PAD_EIM_D20__UART1_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 194 | MX6_PAD_EIM_D19__UART1_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | 194 | MX6_PAD_EIM_D19__UART1_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 195 | }; | 195 | }; |
| 196 | 196 | ||
| 197 | /* SER1/UART2 */ | 197 | /* SER1/UART2 */ |
| 198 | iomux_v3_cfg_t const uart2_pads[] = { | 198 | iomux_v3_cfg_t const uart2_pads[] = { |
| 199 | MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | 199 | MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 200 | MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | 200 | MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 201 | }; | 201 | }; |
| 202 | 202 | ||
| 203 | /* SER2/UART4 */ | 203 | /* SER2/UART4 */ |
| 204 | iomux_v3_cfg_t const uart4_pads[] = { | 204 | iomux_v3_cfg_t const uart4_pads[] = { |
| 205 | MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | 205 | MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 206 | MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | 206 | MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 207 | MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | 207 | MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 208 | MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | 208 | MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 209 | }; | 209 | }; |
| 210 | 210 | ||
| 211 | /* SER3/UART5 Debug Port */ | 211 | /* SER3/UART5 Debug Port */ |
| 212 | iomux_v3_cfg_t const uart5_pads[] = { | 212 | iomux_v3_cfg_t const uart5_pads[] = { |
| 213 | MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | 213 | MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 214 | MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | 214 | MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 215 | }; | 215 | }; |
| 216 | 216 | ||
| 217 | iomux_v3_cfg_t const wdt_pads[] = { | 217 | iomux_v3_cfg_t const wdt_pads[] = { |
| 218 | MX6_PAD_EIM_D16__GPIO3_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), | 218 | MX6_PAD_EIM_D16__GPIO3_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 219 | }; | 219 | }; |
| 220 | 220 | ||
| 221 | iomux_v3_cfg_t const reset_out_pads[] = { | 221 | iomux_v3_cfg_t const reset_out_pads[] = { |
| 222 | MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), | 222 | MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 223 | }; | 223 | }; |
| 224 | 224 | ||
| 225 | static iomux_v3_cfg_t const enet_pads[] = { | 225 | static iomux_v3_cfg_t const enet_pads[] = { |
| 226 | MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), | 226 | MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 227 | MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), | 227 | MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 228 | MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), | 228 | MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 229 | MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), | 229 | MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 230 | MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), | 230 | MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 231 | MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), | 231 | MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 232 | MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), | 232 | MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 233 | MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), | 233 | MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 234 | MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), | 234 | MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 235 | MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), | 235 | MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 236 | MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), | 236 | MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 237 | MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), | 237 | MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 238 | MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), | 238 | MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 239 | MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), | 239 | MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 240 | MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), | 240 | MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 241 | }; | 241 | }; |
| 242 | 242 | ||
| 243 | static void setup_iomux_enet(void) | 243 | static void setup_iomux_enet(void) |
| 244 | { | 244 | { |
| 245 | imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); | 245 | imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); |
| 246 | gpio_direction_input(IMX_GPIO_NR(4, 11)); | 246 | gpio_direction_input(IMX_GPIO_NR(4, 11)); |
| 247 | } | 247 | } |
| 248 | 248 | ||
| 249 | /* SDIO */ | 249 | /* SDIO */ |
| 250 | iomux_v3_cfg_t const usdhc2_pads[] = { | 250 | iomux_v3_cfg_t const usdhc2_pads[] = { |
| 251 | MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 251 | MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 252 | MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 252 | MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 253 | MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 253 | MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 254 | MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 254 | MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 255 | MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 255 | MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 256 | MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 256 | MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 257 | MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ | 257 | MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ |
| 258 | MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */ | 258 | MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */ |
| 259 | MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), /* SDIO_PWR_EN */ | 259 | MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), /* SDIO_PWR_EN */ |
| 260 | }; | 260 | }; |
| 261 | 261 | ||
| 262 | /* SDMMC */ | 262 | /* SDMMC */ |
| 263 | iomux_v3_cfg_t const usdhc3_pads[] = { | 263 | iomux_v3_cfg_t const usdhc3_pads[] = { |
| 264 | MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 264 | MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 265 | MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 265 | MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 266 | MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 266 | MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 267 | MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 267 | MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 268 | MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 268 | MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 269 | MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 269 | MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 270 | MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 270 | MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 271 | }; | 271 | }; |
| 272 | 272 | ||
| 273 | /* eMMC */ | 273 | /* eMMC */ |
| 274 | iomux_v3_cfg_t const usdhc4_pads[] = { | 274 | iomux_v3_cfg_t const usdhc4_pads[] = { |
| 275 | MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 275 | MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 276 | MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 276 | MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 277 | MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 277 | MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 278 | MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 278 | MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 279 | MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 279 | MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 280 | MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 280 | MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 281 | MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 281 | MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 282 | MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 282 | MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 283 | MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 283 | MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 284 | MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | 284 | MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 285 | }; | 285 | }; |
| 286 | 286 | ||
| 287 | #ifdef CONFIG_MXC_SPI | 287 | #ifdef CONFIG_MXC_SPI |
| 288 | /* SPI0 */ | 288 | /* SPI0 */ |
| 289 | iomux_v3_cfg_t const ecspi2_pads[] = { | 289 | iomux_v3_cfg_t const ecspi2_pads[] = { |
| 290 | MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), | 290 | MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| 291 | MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), | 291 | MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| 292 | MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), | 292 | MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| 293 | MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/ | 293 | MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/ |
| 294 | MX6_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS2#*/ | 294 | MX6_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS2#*/ |
| 295 | MX6_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS3#*/ | 295 | MX6_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS3#*/ |
| 296 | }; | 296 | }; |
| 297 | 297 | ||
| 298 | static void setup_spinor(void) | 298 | static void setup_spinor(void) |
| 299 | { | 299 | { |
| 300 | imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); | 300 | imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); |
| 301 | gpio_direction_output(IMX_GPIO_NR(5, 29), 0); | 301 | gpio_direction_output(IMX_GPIO_NR(5, 29), 0); |
| 302 | } | 302 | } |
| 303 | 303 | ||
| 304 | int board_spi_cs_gpio(unsigned bus, unsigned cs) | 304 | int board_spi_cs_gpio(unsigned bus, unsigned cs) |
| 305 | { | 305 | { |
| 306 | return (bus == 1 && cs == 0) ? (IMX_GPIO_NR(5, 29)) : -1; | 306 | return (bus == 1 && cs == 0) ? (IMX_GPIO_NR(5, 29)) : -1; |
| 307 | } | 307 | } |
| 308 | #endif | 308 | #endif |
| 309 | 309 | ||
| 310 | /* SPI1 */ | 310 | /* SPI1 */ |
| 311 | iomux_v3_cfg_t const ecspi1_pads[] = { | 311 | iomux_v3_cfg_t const ecspi1_pads[] = { |
| 312 | MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), | 312 | MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| 313 | MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), | 313 | MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| 314 | MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), | 314 | MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| 315 | MX6_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/ | 315 | MX6_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/ |
| 316 | MX6_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS1#*/ | 316 | MX6_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS1#*/ |
| 317 | }; | 317 | }; |
| 318 | 318 | ||
| 319 | static iomux_v3_cfg_t const rgb_pads[] = { | 319 | static iomux_v3_cfg_t const rgb_pads[] = { |
| 320 | MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), | 320 | MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 321 | MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 321 | MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 322 | MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 322 | MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 323 | MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 323 | MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 324 | MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(LCD_PAD_CTRL), /* DISP0_DRDY */ | 324 | MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(LCD_PAD_CTRL), /* DISP0_DRDY */ |
| 325 | MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 325 | MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 326 | MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 326 | MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 327 | MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 327 | MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 328 | MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 328 | MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 329 | MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 329 | MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 330 | MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 330 | MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 331 | MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 331 | MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 332 | MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 332 | MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 333 | MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 333 | MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 334 | MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 334 | MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 335 | MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 335 | MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 336 | MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 336 | MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 337 | MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 337 | MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 338 | MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 338 | MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 339 | MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 339 | MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 340 | MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 340 | MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 341 | MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 341 | MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 342 | MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 342 | MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 343 | MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 343 | MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 344 | MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 344 | MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 345 | MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 345 | MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 346 | MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 346 | MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 347 | MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 347 | MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 348 | MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), | 348 | MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), |
| 349 | }; | 349 | }; |
| 350 | 350 | ||
| 351 | static void enable_rgb(struct display_info_t const *dev) | 351 | static void enable_rgb(struct display_info_t const *dev) |
| 352 | { | 352 | { |
| 353 | imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads)); | 353 | imx_iomux_v3_setup_multiple_pads(rgb_pads, ARRAY_SIZE(rgb_pads)); |
| 354 | gpio_direction_output(DISP0_PWR_EN, 1); | 354 | gpio_direction_output(DISP0_PWR_EN, 1); |
| 355 | } | 355 | } |
| 356 | 356 | ||
| 357 | iomux_v3_cfg_t const pcie_pads[] = { | 357 | iomux_v3_cfg_t const pcie_pads[] = { |
| 358 | MX6_PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe Present */ | 358 | MX6_PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe Present */ |
| 359 | MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */ | 359 | MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */ |
| 360 | MX6_PAD_SD1_DAT0__GPIO1_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe Clock Request */ | 360 | MX6_PAD_SD1_DAT0__GPIO1_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe Clock Request */ |
| 361 | }; | 361 | }; |
| 362 | 362 | ||
| 363 | static void setup_pcie(void) | 363 | static void setup_pcie(void) |
| 364 | { | 364 | { |
| 365 | imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); | 365 | imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); |
| 366 | gpio_direction_input(IMX_GPIO_NR(1, 16)); | 366 | gpio_direction_input(IMX_GPIO_NR(1, 16)); |
| 367 | gpio_direction_input(IMX_GPIO_NR(1, 17)); | 367 | gpio_direction_input(IMX_GPIO_NR(1, 17)); |
| 368 | gpio_direction_input(IMX_GPIO_NR(1, 19)); | 368 | gpio_direction_input(IMX_GPIO_NR(1, 19)); |
| 369 | gpio_direction_output(IMX_GPIO_NR(1,20), 0); | 369 | gpio_direction_output(IMX_GPIO_NR(1,20), 0); |
| 370 | } | 370 | } |
| 371 | 371 | ||
| 372 | iomux_v3_cfg_t const di0_pads[] = { | 372 | iomux_v3_cfg_t const di0_pads[] = { |
| 373 | MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */ | 373 | MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */ |
| 374 | MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */ | 374 | MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */ |
| 375 | MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */ | 375 | MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */ |
| 376 | }; | 376 | }; |
| 377 | 377 | ||
| 378 | /* CAN0/FLEXCAN1 */ | 378 | /* CAN0/FLEXCAN1 */ |
| 379 | iomux_v3_cfg_t const flexcan1_pads[] = { | 379 | iomux_v3_cfg_t const flexcan1_pads[] = { |
| 380 | 380 | ||
| 381 | MX6_PAD_GPIO_7__FLEXCAN1_TX | MUX_PAD_CTRL(WEAK_PULLUP), | 381 | MX6_PAD_GPIO_7__FLEXCAN1_TX | MUX_PAD_CTRL(WEAK_PULLUP), |
| 382 | MX6_PAD_GPIO_8__FLEXCAN1_RX | MUX_PAD_CTRL(WEAK_PULLUP), | 382 | MX6_PAD_GPIO_8__FLEXCAN1_RX | MUX_PAD_CTRL(WEAK_PULLUP), |
| 383 | }; | 383 | }; |
| 384 | 384 | ||
| 385 | /* CAN1/FLEXCAN2 */ | 385 | /* CAN1/FLEXCAN2 */ |
| 386 | iomux_v3_cfg_t const flexcan2_pads[] = { | 386 | iomux_v3_cfg_t const flexcan2_pads[] = { |
| 387 | MX6_PAD_KEY_COL4__FLEXCAN2_TX | MUX_PAD_CTRL(WEAK_PULLUP), | 387 | MX6_PAD_KEY_COL4__FLEXCAN2_TX | MUX_PAD_CTRL(WEAK_PULLUP), |
| 388 | MX6_PAD_KEY_ROW4__FLEXCAN2_RX | MUX_PAD_CTRL(WEAK_PULLUP), | 388 | MX6_PAD_KEY_ROW4__FLEXCAN2_RX | MUX_PAD_CTRL(WEAK_PULLUP), |
| 389 | }; | 389 | }; |
| 390 | 390 | ||
| 391 | /* GPIOs */ | 391 | /* GPIOs */ |
| 392 | iomux_v3_cfg_t const gpios_pads[] = { | 392 | iomux_v3_cfg_t const gpios_pads[] = { |
| 393 | MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO0 */ | 393 | MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO0 */ |
| 394 | MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO1 */ | 394 | MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO1 */ |
| 395 | MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO2 */ | 395 | MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO2 */ |
| 396 | MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO3 */ | 396 | MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO3 */ |
| 397 | MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO4 */ | 397 | MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO4 */ |
| 398 | MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO6 */ | 398 | MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO6 */ |
| 399 | MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO7 */ | 399 | MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO7 */ |
| 400 | MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO8 */ | 400 | MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO8 */ |
| 401 | MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO9 */ | 401 | MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO9 */ |
| 402 | MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO10 */ | 402 | MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO10 */ |
| 403 | MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO11 */ | 403 | MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO11 */ |
| 404 | }; | 404 | }; |
| 405 | 405 | ||
| 406 | #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) | 406 | #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) |
| 407 | static iomux_v3_cfg_t const epdc_enable_pads[] = { | 407 | static iomux_v3_cfg_t const epdc_enable_pads[] = { |
| 408 | MX6_PAD_EIM_A16__EPDC_DATA00 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 408 | MX6_PAD_EIM_A16__EPDC_DATA00 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 409 | MX6_PAD_EIM_DA10__EPDC_DATA01 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 409 | MX6_PAD_EIM_DA10__EPDC_DATA01 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 410 | MX6_PAD_EIM_DA12__EPDC_DATA02 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 410 | MX6_PAD_EIM_DA12__EPDC_DATA02 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 411 | MX6_PAD_EIM_DA11__EPDC_DATA03 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 411 | MX6_PAD_EIM_DA11__EPDC_DATA03 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 412 | MX6_PAD_EIM_LBA__EPDC_DATA04 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 412 | MX6_PAD_EIM_LBA__EPDC_DATA04 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 413 | MX6_PAD_EIM_EB2__EPDC_DATA05 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 413 | MX6_PAD_EIM_EB2__EPDC_DATA05 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 414 | MX6_PAD_EIM_CS0__EPDC_DATA06 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 414 | MX6_PAD_EIM_CS0__EPDC_DATA06 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 415 | MX6_PAD_EIM_RW__EPDC_DATA07 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 415 | MX6_PAD_EIM_RW__EPDC_DATA07 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 416 | MX6_PAD_EIM_A21__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 416 | MX6_PAD_EIM_A21__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 417 | MX6_PAD_EIM_A22__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 417 | MX6_PAD_EIM_A22__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 418 | MX6_PAD_EIM_A23__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 418 | MX6_PAD_EIM_A23__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 419 | MX6_PAD_EIM_A24__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 419 | MX6_PAD_EIM_A24__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 420 | MX6_PAD_EIM_D31__EPDC_SDCLK_P | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 420 | MX6_PAD_EIM_D31__EPDC_SDCLK_P | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 421 | MX6_PAD_EIM_D27__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 421 | MX6_PAD_EIM_D27__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 422 | MX6_PAD_EIM_DA1__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 422 | MX6_PAD_EIM_DA1__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 423 | MX6_PAD_EIM_EB1__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 423 | MX6_PAD_EIM_EB1__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 424 | MX6_PAD_EIM_DA2__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 424 | MX6_PAD_EIM_DA2__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 425 | MX6_PAD_EIM_DA4__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 425 | MX6_PAD_EIM_DA4__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 426 | MX6_PAD_EIM_DA5__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 426 | MX6_PAD_EIM_DA5__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 427 | MX6_PAD_EIM_DA6__EPDC_SDCE2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), | 427 | MX6_PAD_EIM_DA6__EPDC_SDCE2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), |
| 428 | }; | 428 | }; |
| 429 | 429 | ||
| 430 | static iomux_v3_cfg_t const epdc_disable_pads[] = { | 430 | static iomux_v3_cfg_t const epdc_disable_pads[] = { |
| 431 | MX6_PAD_EIM_A16__GPIO2_IO22, | 431 | MX6_PAD_EIM_A16__GPIO2_IO22, |
| 432 | MX6_PAD_EIM_DA10__GPIO3_IO10, | 432 | MX6_PAD_EIM_DA10__GPIO3_IO10, |
| 433 | MX6_PAD_EIM_DA12__GPIO3_IO12, | 433 | MX6_PAD_EIM_DA12__GPIO3_IO12, |
| 434 | MX6_PAD_EIM_DA11__GPIO3_IO11, | 434 | MX6_PAD_EIM_DA11__GPIO3_IO11, |
| 435 | MX6_PAD_EIM_LBA__GPIO2_IO27, | 435 | MX6_PAD_EIM_LBA__GPIO2_IO27, |
| 436 | MX6_PAD_EIM_EB2__GPIO2_IO30, | 436 | MX6_PAD_EIM_EB2__GPIO2_IO30, |
| 437 | MX6_PAD_EIM_CS0__GPIO2_IO23, | 437 | MX6_PAD_EIM_CS0__GPIO2_IO23, |
| 438 | MX6_PAD_EIM_RW__GPIO2_IO26, | 438 | MX6_PAD_EIM_RW__GPIO2_IO26, |
| 439 | MX6_PAD_EIM_A21__GPIO2_IO17, | 439 | MX6_PAD_EIM_A21__GPIO2_IO17, |
| 440 | MX6_PAD_EIM_A22__GPIO2_IO16, | 440 | MX6_PAD_EIM_A22__GPIO2_IO16, |
| 441 | MX6_PAD_EIM_A23__GPIO6_IO06, | 441 | MX6_PAD_EIM_A23__GPIO6_IO06, |
| 442 | MX6_PAD_EIM_A24__GPIO5_IO04, | 442 | MX6_PAD_EIM_A24__GPIO5_IO04, |
| 443 | MX6_PAD_EIM_D31__GPIO3_IO31, | 443 | MX6_PAD_EIM_D31__GPIO3_IO31, |
| 444 | MX6_PAD_EIM_D27__GPIO3_IO27, | 444 | MX6_PAD_EIM_D27__GPIO3_IO27, |
| 445 | MX6_PAD_EIM_DA1__GPIO3_IO01, | 445 | MX6_PAD_EIM_DA1__GPIO3_IO01, |
| 446 | MX6_PAD_EIM_EB1__GPIO2_IO29, | 446 | MX6_PAD_EIM_EB1__GPIO2_IO29, |
| 447 | MX6_PAD_EIM_DA2__GPIO3_IO02, | 447 | MX6_PAD_EIM_DA2__GPIO3_IO02, |
| 448 | MX6_PAD_EIM_DA4__GPIO3_IO04, | 448 | MX6_PAD_EIM_DA4__GPIO3_IO04, |
| 449 | MX6_PAD_EIM_DA5__GPIO3_IO05, | 449 | MX6_PAD_EIM_DA5__GPIO3_IO05, |
| 450 | MX6_PAD_EIM_DA6__GPIO3_IO06, | 450 | MX6_PAD_EIM_DA6__GPIO3_IO06, |
| 451 | }; | 451 | }; |
| 452 | #endif | 452 | #endif |
| 453 | 453 | ||
| 454 | static void setup_iomux_uart1(void) | 454 | static void setup_iomux_uart1(void) |
| 455 | { | 455 | { |
| 456 | imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); | 456 | imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
| 457 | } | 457 | } |
| 458 | 458 | ||
| 459 | static void setup_iomux_uart2(void) | 459 | static void setup_iomux_uart2(void) |
| 460 | { | 460 | { |
| 461 | imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); | 461 | imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); |
| 462 | } | 462 | } |
| 463 | 463 | ||
| 464 | static void setup_iomux_uart4(void) | 464 | static void setup_iomux_uart4(void) |
| 465 | { | 465 | { |
| 466 | imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); | 466 | imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); |
| 467 | } | 467 | } |
| 468 | 468 | ||
| 469 | static void setup_iomux_uart5(void) | 469 | static void setup_iomux_uart5(void) |
| 470 | { | 470 | { |
| 471 | imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); | 471 | imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); |
| 472 | } | 472 | } |
| 473 | 473 | ||
| 474 | static void setup_iomux_wdt(void) | 474 | static void setup_iomux_wdt(void) |
| 475 | { | 475 | { |
| 476 | imx_iomux_v3_setup_multiple_pads(wdt_pads, ARRAY_SIZE(wdt_pads)); | 476 | imx_iomux_v3_setup_multiple_pads(wdt_pads, ARRAY_SIZE(wdt_pads)); |
| 477 | 477 | ||
| 478 | /* Set HW_WDT as Output High */ | 478 | /* Set HW_WDT as Output High */ |
| 479 | gpio_direction_output(IMX_GPIO_NR(3, 16) , 1); | 479 | gpio_direction_output(IMX_GPIO_NR(3, 16) , 1); |
| 480 | } | 480 | } |
| 481 | 481 | ||
| 482 | static void setup_iomux_reset_out(void) | 482 | static void setup_iomux_reset_out(void) |
| 483 | { | 483 | { |
| 484 | imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads)); | 484 | imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads)); |
| 485 | 485 | ||
| 486 | /* Set CPU RESET_OUT as Output */ | 486 | /* Set CPU RESET_OUT as Output */ |
| 487 | gpio_direction_output(IMX_GPIO_NR(6, 16) , 0); | 487 | gpio_direction_output(IMX_GPIO_NR(6, 16) , 0); |
| 488 | } | 488 | } |
| 489 | 489 | ||
| 490 | static void setup_spi1(void) | 490 | static void setup_spi1(void) |
| 491 | { | 491 | { |
| 492 | imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); | 492 | imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); |
| 493 | gpio_direction_output(IMX_GPIO_NR(4, 9), 0); | 493 | gpio_direction_output(IMX_GPIO_NR(4, 9), 0); |
| 494 | gpio_direction_output(IMX_GPIO_NR(4, 10), 0); | 494 | gpio_direction_output(IMX_GPIO_NR(4, 10), 0); |
| 495 | } | 495 | } |
| 496 | 496 | ||
| 497 | static void setup_flexcan1(void) | 497 | static void setup_flexcan1(void) |
| 498 | { | 498 | { |
| 499 | imx_iomux_v3_setup_multiple_pads(flexcan1_pads, ARRAY_SIZE(flexcan1_pads)); | 499 | imx_iomux_v3_setup_multiple_pads(flexcan1_pads, ARRAY_SIZE(flexcan1_pads)); |
| 500 | } | 500 | } |
| 501 | 501 | ||
| 502 | static void setup_flexcan2(void) | 502 | static void setup_flexcan2(void) |
| 503 | { | 503 | { |
| 504 | imx_iomux_v3_setup_multiple_pads(flexcan2_pads, ARRAY_SIZE(flexcan2_pads)); | 504 | imx_iomux_v3_setup_multiple_pads(flexcan2_pads, ARRAY_SIZE(flexcan2_pads)); |
| 505 | } | 505 | } |
| 506 | 506 | ||
| 507 | static void setup_gpios(void) | 507 | static void setup_gpios(void) |
| 508 | { | 508 | { |
| 509 | imx_iomux_v3_setup_multiple_pads(gpios_pads, ARRAY_SIZE(gpios_pads)); | 509 | imx_iomux_v3_setup_multiple_pads(gpios_pads, ARRAY_SIZE(gpios_pads)); |
| 510 | gpio_direction_output(IMX_GPIO_NR(6, 11), 0); | 510 | gpio_direction_output(IMX_GPIO_NR(6, 11), 0); |
| 511 | gpio_direction_output(IMX_GPIO_NR(2, 02), 0); | 511 | gpio_direction_output(IMX_GPIO_NR(2, 02), 0); |
| 512 | gpio_direction_output(IMX_GPIO_NR(2, 06), 0); | 512 | gpio_direction_output(IMX_GPIO_NR(2, 06), 0); |
| 513 | gpio_direction_output(IMX_GPIO_NR(2, 03), 0); | 513 | gpio_direction_output(IMX_GPIO_NR(2, 03), 0); |
| 514 | gpio_direction_output(IMX_GPIO_NR(2, 07), 0); | 514 | gpio_direction_output(IMX_GPIO_NR(2, 07), 0); |
| 515 | gpio_direction_input(IMX_GPIO_NR(6, 14)); | 515 | gpio_direction_input(IMX_GPIO_NR(6, 14)); |
| 516 | gpio_direction_input(IMX_GPIO_NR(6, 07)); | 516 | gpio_direction_input(IMX_GPIO_NR(6, 07)); |
| 517 | gpio_direction_input(IMX_GPIO_NR(2, 04)); | 517 | gpio_direction_input(IMX_GPIO_NR(2, 04)); |
| 518 | gpio_direction_input(IMX_GPIO_NR(2, 00)); | 518 | gpio_direction_input(IMX_GPIO_NR(2, 00)); |
| 519 | gpio_direction_input(IMX_GPIO_NR(2, 05)); | 519 | gpio_direction_input(IMX_GPIO_NR(2, 05)); |
| 520 | gpio_direction_input(IMX_GPIO_NR(6, 8)); | 520 | gpio_direction_input(IMX_GPIO_NR(6, 8)); |
| 521 | } | 521 | } |
| 522 | 522 | ||
| 523 | #ifdef CONFIG_FSL_ESDHC | 523 | #ifdef CONFIG_FSL_ESDHC |
| 524 | struct fsl_esdhc_cfg usdhc_cfg[3] = { | 524 | struct fsl_esdhc_cfg usdhc_cfg[3] = { |
| 525 | {USDHC2_BASE_ADDR}, | 525 | {USDHC2_BASE_ADDR}, |
| 526 | {USDHC3_BASE_ADDR}, | 526 | {USDHC3_BASE_ADDR}, |
| 527 | {USDHC4_BASE_ADDR}, | 527 | {USDHC4_BASE_ADDR}, |
| 528 | }; | 528 | }; |
| 529 | 529 | ||
| 530 | int mmc_get_env_devno(void) | 530 | int mmc_get_env_devno(void) |
| 531 | { | 531 | { |
| 532 | u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4); | 532 | u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4); |
| 533 | u32 dev_no; | 533 | u32 dev_no; |
| 534 | u32 bootsel; | 534 | u32 bootsel; |
| 535 | 535 | ||
| 536 | bootsel = (soc_sbmr & 0x000000FF) >> 6 ; | 536 | bootsel = (soc_sbmr & 0x000000FF) >> 6 ; |
| 537 | 537 | ||
| 538 | /* If not boot from sd/mmc, use default value */ | 538 | /* If not boot from sd/mmc, use default value */ |
| 539 | if (bootsel != 1) | 539 | if (bootsel != 1) |
| 540 | return CONFIG_SYS_MMC_ENV_DEV; | 540 | return CONFIG_SYS_MMC_ENV_DEV; |
| 541 | 541 | ||
| 542 | /* BOOT_CFG2[3] and BOOT_CFG2[4] */ | 542 | /* BOOT_CFG2[3] and BOOT_CFG2[4] */ |
| 543 | dev_no = (soc_sbmr & 0x00001800) >> 11; | 543 | dev_no = (soc_sbmr & 0x00001800) >> 11; |
| 544 | 544 | ||
| 545 | /* need ubstract 1 to map to the mmc device id | 545 | /* need ubstract 1 to map to the mmc device id |
| 546 | * see the comments in board_mmc_init function | 546 | * see the comments in board_mmc_init function |
| 547 | */ | 547 | */ |
| 548 | 548 | ||
| 549 | dev_no--; | 549 | dev_no--; |
| 550 | 550 | ||
| 551 | return dev_no; | 551 | return dev_no; |
| 552 | } | 552 | } |
| 553 | 553 | ||
| 554 | int mmc_map_to_kernel_blk(int dev_no) | 554 | int mmc_map_to_kernel_blk(int dev_no) |
| 555 | { | 555 | { |
| 556 | return dev_no + 1; | 556 | return dev_no + 1; |
| 557 | } | 557 | } |
| 558 | 558 | ||
| 559 | #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 28) | 559 | #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 28) |
| 560 | /*#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)*/ | 560 | /*#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)*/ |
| 561 | 561 | ||
| 562 | int board_mmc_getcd(struct mmc *mmc) | 562 | int board_mmc_getcd(struct mmc *mmc) |
| 563 | { | 563 | { |
| 564 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; | 564 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; |
| 565 | int ret = 0; | 565 | int ret = 0; |
| 566 | 566 | ||
| 567 | switch (cfg->esdhc_base) { | 567 | switch (cfg->esdhc_base) { |
| 568 | case USDHC2_BASE_ADDR: | 568 | case USDHC2_BASE_ADDR: |
| 569 | ret = !gpio_get_value(USDHC2_CD_GPIO); | 569 | ret = !gpio_get_value(USDHC2_CD_GPIO); |
| 570 | break; | 570 | break; |
| 571 | case USDHC3_BASE_ADDR: | 571 | case USDHC3_BASE_ADDR: |
| 572 | /*ret = !gpio_get_value(USDHC3_CD_GPIO);*/ | 572 | /*ret = !gpio_get_value(USDHC3_CD_GPIO);*/ |
| 573 | break; | 573 | break; |
| 574 | case USDHC4_BASE_ADDR: | 574 | case USDHC4_BASE_ADDR: |
| 575 | ret = 1; /* eMMC/uSDHC4 is always present */ | 575 | ret = 1; /* eMMC/uSDHC4 is always present */ |
| 576 | break; | 576 | break; |
| 577 | } | 577 | } |
| 578 | 578 | ||
| 579 | return ret; | 579 | return ret; |
| 580 | } | 580 | } |
| 581 | 581 | ||
| 582 | int board_mmc_init(bd_t *bis) | 582 | int board_mmc_init(bd_t *bis) |
| 583 | { | 583 | { |
| 584 | #ifndef CONFIG_SPL_BUILD | 584 | #ifndef CONFIG_SPL_BUILD |
| 585 | int ret; | 585 | int ret; |
| 586 | int i; | 586 | int i; |
| 587 | 587 | ||
| 588 | /* | 588 | /* |
| 589 | * According to the board_mmc_init() the following map is done: | 589 | * According to the board_mmc_init() the following map is done: |
| 590 | * (U-boot device node) (Physical Port) | 590 | * (U-boot device node) (Physical Port) |
| 591 | * mmc0 SDIO | 591 | * mmc0 SDIO |
| 592 | * mmc1 SDMMC | 592 | * mmc1 SDMMC |
| 593 | * mmc2 eMMC | 593 | * mmc2 eMMC |
| 594 | */ | 594 | */ |
| 595 | for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { | 595 | for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { |
| 596 | switch (i) { | 596 | switch (i) { |
| 597 | case 0: | 597 | case 0: |
| 598 | imx_iomux_v3_setup_multiple_pads( | 598 | imx_iomux_v3_setup_multiple_pads( |
| 599 | usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); | 599 | usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); |
| 600 | gpio_direction_input(USDHC2_CD_GPIO); | 600 | gpio_direction_input(USDHC2_CD_GPIO); |
| 601 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); | 601 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
| 602 | break; | 602 | break; |
| 603 | case 1: | 603 | case 1: |
| 604 | imx_iomux_v3_setup_multiple_pads( | 604 | imx_iomux_v3_setup_multiple_pads( |
| 605 | usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); | 605 | usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
| 606 | /*gpio_direction_input(USDHC3_CD_GPIO);*/ | 606 | /*gpio_direction_input(USDHC3_CD_GPIO);*/ |
| 607 | usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); | 607 | usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
| 608 | break; | 608 | break; |
| 609 | case 2: | 609 | case 2: |
| 610 | imx_iomux_v3_setup_multiple_pads( | 610 | imx_iomux_v3_setup_multiple_pads( |
| 611 | usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); | 611 | usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); |
| 612 | usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); | 612 | usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
| 613 | break; | 613 | break; |
| 614 | default: | 614 | default: |
| 615 | printf("Warning: you configured more USDHC controllers" | 615 | printf("Warning: you configured more USDHC controllers" |
| 616 | "(%d) then supported by the board (%d)\n", | 616 | "(%d) then supported by the board (%d)\n", |
| 617 | i + 1, CONFIG_SYS_FSL_USDHC_NUM); | 617 | i + 1, CONFIG_SYS_FSL_USDHC_NUM); |
| 618 | return -EINVAL; | 618 | return -EINVAL; |
| 619 | } | 619 | } |
| 620 | 620 | ||
| 621 | ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); | 621 | ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); |
| 622 | if (ret) | 622 | if (ret) |
| 623 | return ret; | 623 | return ret; |
| 624 | } | 624 | } |
| 625 | 625 | ||
| 626 | return 0; | 626 | return 0; |
| 627 | #else | 627 | #else |
| 628 | struct src *psrc = (struct src *)SRC_BASE_ADDR; | 628 | struct src *psrc = (struct src *)SRC_BASE_ADDR; |
| 629 | unsigned reg = readl(&psrc->sbmr1) >> 11; | 629 | unsigned reg = readl(&psrc->sbmr1) >> 11; |
| 630 | /* | 630 | /* |
| 631 | * Upon reading BOOT_CFG register the following map is done: | 631 | * Upon reading BOOT_CFG register the following map is done: |
| 632 | * Bit 11 and 12 of BOOT_CFG register can determine the current | 632 | * Bit 11 and 12 of BOOT_CFG register can determine the current |
| 633 | * mmc port | 633 | * mmc port |
| 634 | * 0x1 SDIO | 634 | * 0x1 SDIO |
| 635 | * 0x2 SDMMC | 635 | * 0x2 SDMMC |
| 636 | * 0x3 eMMC | 636 | * 0x3 eMMC |
| 637 | */ | 637 | */ |
| 638 | 638 | ||
| 639 | switch (reg & 0x3) { | 639 | switch (reg & 0x3) { |
| 640 | case 0x1: | 640 | case 0x1: |
| 641 | imx_iomux_v3_setup_multiple_pads( | 641 | imx_iomux_v3_setup_multiple_pads( |
| 642 | usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); | 642 | usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); |
| 643 | usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; | 643 | usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; |
| 644 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); | 644 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
| 645 | gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; | 645 | gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; |
| 646 | break; | 646 | break; |
| 647 | case 0x2: | 647 | case 0x2: |
| 648 | imx_iomux_v3_setup_multiple_pads( | 648 | imx_iomux_v3_setup_multiple_pads( |
| 649 | usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); | 649 | usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); |
| 650 | usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; | 650 | usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; |
| 651 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); | 651 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); |
| 652 | gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; | 652 | gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; |
| 653 | break; | 653 | break; |
| 654 | case 0x3: | 654 | case 0x3: |
| 655 | imx_iomux_v3_setup_multiple_pads( | 655 | imx_iomux_v3_setup_multiple_pads( |
| 656 | usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); | 656 | usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); |
| 657 | usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; | 657 | usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; |
| 658 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); | 658 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); |
| 659 | gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; | 659 | gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; |
| 660 | break; | 660 | break; |
| 661 | } | 661 | } |
| 662 | 662 | ||
| 663 | return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); | 663 | return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); |
| 664 | #endif | 664 | #endif |
| 665 | } | 665 | } |
| 666 | #endif | 666 | #endif |
| 667 | 667 | ||
| 668 | int check_mmc_autodetect(void) | 668 | int check_mmc_autodetect(void) |
| 669 | { | 669 | { |
| 670 | char *autodetect_str = getenv("mmcautodetect"); | 670 | char *autodetect_str = getenv("mmcautodetect"); |
| 671 | 671 | ||
| 672 | if ((autodetect_str != NULL) && | 672 | if ((autodetect_str != NULL) && |
| 673 | (strcmp(autodetect_str, "yes") == 0)) { | 673 | (strcmp(autodetect_str, "yes") == 0)) { |
| 674 | return 1; | 674 | return 1; |
| 675 | } | 675 | } |
| 676 | 676 | ||
| 677 | return 0; | 677 | return 0; |
| 678 | } | 678 | } |
| 679 | 679 | ||
| 680 | void board_late_mmc_env_init(void) | 680 | void board_late_mmc_env_init(void) |
| 681 | { | 681 | { |
| 682 | char cmd[32]; | 682 | char cmd[32]; |
| 683 | char mmcblk[32]; | 683 | char mmcblk[32]; |
| 684 | u32 dev_no = mmc_get_env_devno(); | 684 | u32 dev_no = mmc_get_env_devno(); |
| 685 | 685 | ||
| 686 | if (!check_mmc_autodetect()) | 686 | if (!check_mmc_autodetect()) |
| 687 | return; | 687 | return; |
| 688 | 688 | ||
| 689 | setenv_ulong("mmcdev", dev_no); | 689 | setenv_ulong("mmcdev", dev_no); |
| 690 | 690 | ||
| 691 | /* Set mmcblk env */ | 691 | /* Set mmcblk env */ |
| 692 | sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", | 692 | sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", |
| 693 | mmc_map_to_kernel_blk(dev_no)); | 693 | mmc_map_to_kernel_blk(dev_no)); |
| 694 | setenv("mmcroot", mmcblk); | 694 | setenv("mmcroot", mmcblk); |
| 695 | 695 | ||
| 696 | sprintf(cmd, "mmc dev %d", dev_no); | 696 | sprintf(cmd, "mmc dev %d", dev_no); |
| 697 | run_command(cmd, 0); | 697 | run_command(cmd, 0); |
| 698 | } | 698 | } |
| 699 | 699 | ||
| 700 | #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) | 700 | #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) |
| 701 | vidinfo_t panel_info = { | 701 | vidinfo_t panel_info = { |
| 702 | .vl_refresh = 85, | 702 | .vl_refresh = 85, |
| 703 | .vl_col = 800, | 703 | .vl_col = 800, |
| 704 | .vl_row = 600, | 704 | .vl_row = 600, |
| 705 | .vl_pixclock = 26666667, | 705 | .vl_pixclock = 26666667, |
| 706 | .vl_left_margin = 8, | 706 | .vl_left_margin = 8, |
| 707 | .vl_right_margin = 100, | 707 | .vl_right_margin = 100, |
| 708 | .vl_upper_margin = 4, | 708 | .vl_upper_margin = 4, |
| 709 | .vl_lower_margin = 8, | 709 | .vl_lower_margin = 8, |
| 710 | .vl_hsync = 4, | 710 | .vl_hsync = 4, |
| 711 | .vl_vsync = 1, | 711 | .vl_vsync = 1, |
| 712 | .vl_sync = 0, | 712 | .vl_sync = 0, |
| 713 | .vl_mode = 0, | 713 | .vl_mode = 0, |
| 714 | .vl_flag = 0, | 714 | .vl_flag = 0, |
| 715 | .vl_bpix = 3, | 715 | .vl_bpix = 3, |
| 716 | .cmap = 0, | 716 | .cmap = 0, |
| 717 | }; | 717 | }; |
| 718 | 718 | ||
| 719 | struct epdc_timing_params panel_timings = { | 719 | struct epdc_timing_params panel_timings = { |
| 720 | .vscan_holdoff = 4, | 720 | .vscan_holdoff = 4, |
| 721 | .sdoed_width = 10, | 721 | .sdoed_width = 10, |
| 722 | .sdoed_delay = 20, | 722 | .sdoed_delay = 20, |
| 723 | .sdoez_width = 10, | 723 | .sdoez_width = 10, |
| 724 | .sdoez_delay = 20, | 724 | .sdoez_delay = 20, |
| 725 | .gdclk_hp_offs = 419, | 725 | .gdclk_hp_offs = 419, |
| 726 | .gdsp_offs = 20, | 726 | .gdsp_offs = 20, |
| 727 | .gdoe_offs = 0, | 727 | .gdoe_offs = 0, |
| 728 | .gdclk_offs = 5, | 728 | .gdclk_offs = 5, |
| 729 | .num_ce = 1, | 729 | .num_ce = 1, |
| 730 | }; | 730 | }; |
| 731 | 731 | ||
| 732 | static void setup_epdc_power(void) | 732 | static void setup_epdc_power(void) |
| 733 | { | 733 | { |
| 734 | /* Setup epdc voltage */ | 734 | /* Setup epdc voltage */ |
| 735 | 735 | ||
| 736 | /* EIM_A17 - GPIO2[21] for PWR_GOOD status */ | 736 | /* EIM_A17 - GPIO2[21] for PWR_GOOD status */ |
| 737 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 | | 737 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 | |
| 738 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); | 738 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); |
| 739 | /* Set as input */ | 739 | /* Set as input */ |
| 740 | gpio_direction_input(IMX_GPIO_NR(2, 21)); | 740 | gpio_direction_input(IMX_GPIO_NR(2, 21)); |
| 741 | 741 | ||
| 742 | /* EIM_D17 - GPIO3[17] for VCOM control */ | 742 | /* EIM_D17 - GPIO3[17] for VCOM control */ |
| 743 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 | | 743 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 | |
| 744 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); | 744 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); |
| 745 | 745 | ||
| 746 | /* Set as output */ | 746 | /* Set as output */ |
| 747 | gpio_direction_output(IMX_GPIO_NR(3, 17), 1); | 747 | gpio_direction_output(IMX_GPIO_NR(3, 17), 1); |
| 748 | 748 | ||
| 749 | /* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */ | 749 | /* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */ |
| 750 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 | | 750 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 | |
| 751 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); | 751 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); |
| 752 | /* Set as output */ | 752 | /* Set as output */ |
| 753 | gpio_direction_output(IMX_GPIO_NR(3, 20), 1); | 753 | gpio_direction_output(IMX_GPIO_NR(3, 20), 1); |
| 754 | 754 | ||
| 755 | /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */ | 755 | /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */ |
| 756 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 | | 756 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 | |
| 757 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); | 757 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); |
| 758 | /* Set as output */ | 758 | /* Set as output */ |
| 759 | gpio_direction_output(IMX_GPIO_NR(2, 20), 1); | 759 | gpio_direction_output(IMX_GPIO_NR(2, 20), 1); |
| 760 | } | 760 | } |
| 761 | 761 | ||
| 762 | static void epdc_enable_pins(void) | 762 | static void epdc_enable_pins(void) |
| 763 | { | 763 | { |
| 764 | /* epdc iomux settings */ | 764 | /* epdc iomux settings */ |
| 765 | imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, | 765 | imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, |
| 766 | ARRAY_SIZE(epdc_enable_pads)); | 766 | ARRAY_SIZE(epdc_enable_pads)); |
| 767 | } | 767 | } |
| 768 | 768 | ||
| 769 | static void epdc_disable_pins(void) | 769 | static void epdc_disable_pins(void) |
| 770 | { | 770 | { |
| 771 | /* Configure MUX settings for EPDC pins to GPIO */ | 771 | /* Configure MUX settings for EPDC pins to GPIO */ |
| 772 | imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, | 772 | imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, |
| 773 | ARRAY_SIZE(epdc_disable_pads)); | 773 | ARRAY_SIZE(epdc_disable_pads)); |
| 774 | } | 774 | } |
| 775 | 775 | ||
| 776 | static void setup_epdc(void) | 776 | static void setup_epdc(void) |
| 777 | { | 777 | { |
| 778 | unsigned int reg; | 778 | unsigned int reg; |
| 779 | struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | 779 | struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 780 | 780 | ||
| 781 | /*** epdc Maxim PMIC settings ***/ | 781 | /*** epdc Maxim PMIC settings ***/ |
| 782 | 782 | ||
| 783 | /* EPDC PWRSTAT - GPIO2[21] for PWR_GOOD status */ | 783 | /* EPDC PWRSTAT - GPIO2[21] for PWR_GOOD status */ |
| 784 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 | | 784 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 | |
| 785 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); | 785 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); |
| 786 | 786 | ||
| 787 | /* EPDC VCOM0 - GPIO3[17] for VCOM control */ | 787 | /* EPDC VCOM0 - GPIO3[17] for VCOM control */ |
| 788 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 | | 788 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 | |
| 789 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); | 789 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); |
| 790 | 790 | ||
| 791 | /* UART4 TXD - GPIO3[20] for EPD PMIC WAKEUP */ | 791 | /* UART4 TXD - GPIO3[20] for EPD PMIC WAKEUP */ |
| 792 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 | | 792 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 | |
| 793 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); | 793 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); |
| 794 | 794 | ||
| 795 | /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */ | 795 | /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */ |
| 796 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 | | 796 | imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 | |
| 797 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); | 797 | MUX_PAD_CTRL(EPDC_PAD_CTRL)); |
| 798 | 798 | ||
| 799 | /*** Set pixel clock rates for EPDC ***/ | 799 | /*** Set pixel clock rates for EPDC ***/ |
| 800 | 800 | ||
| 801 | /* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */ | 801 | /* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */ |
| 802 | reg = readl(&ccm_regs->cscdr3); | 802 | reg = readl(&ccm_regs->cscdr3); |
| 803 | reg &= ~0x7C000; | 803 | reg &= ~0x7C000; |
| 804 | reg |= (1 << 16) | (1 << 14); | 804 | reg |= (1 << 16) | (1 << 14); |
| 805 | writel(reg, &ccm_regs->cscdr3); | 805 | writel(reg, &ccm_regs->cscdr3); |
| 806 | 806 | ||
| 807 | /* EPDC AXI clk enable */ | 807 | /* EPDC AXI clk enable */ |
| 808 | reg = readl(&ccm_regs->CCGR3); | 808 | reg = readl(&ccm_regs->CCGR3); |
| 809 | reg |= 0x00C0; | 809 | reg |= 0x00C0; |
| 810 | writel(reg, &ccm_regs->CCGR3); | 810 | writel(reg, &ccm_regs->CCGR3); |
| 811 | 811 | ||
| 812 | /* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */ | 812 | /* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */ |
| 813 | reg = readl(&ccm_regs->cscdr2); | 813 | reg = readl(&ccm_regs->cscdr2); |
| 814 | reg &= ~0x3FE00; | 814 | reg &= ~0x3FE00; |
| 815 | reg |= (2 << 15) | (5 << 12); | 815 | reg |= (2 << 15) | (5 << 12); |
| 816 | writel(reg, &ccm_regs->cscdr2); | 816 | writel(reg, &ccm_regs->cscdr2); |
| 817 | 817 | ||
| 818 | /* PLL5 enable (defaults to 650) */ | 818 | /* PLL5 enable (defaults to 650) */ |
| 819 | reg = readl(&ccm_regs->analog_pll_video); | 819 | reg = readl(&ccm_regs->analog_pll_video); |
| 820 | reg &= ~((1 << 16) | (1 << 12)); | 820 | reg &= ~((1 << 16) | (1 << 12)); |
| 821 | reg |= (1 << 13); | 821 | reg |= (1 << 13); |
| 822 | writel(reg, &ccm_regs->analog_pll_video); | 822 | writel(reg, &ccm_regs->analog_pll_video); |
| 823 | 823 | ||
| 824 | /* EPDC PIX clk enable */ | 824 | /* EPDC PIX clk enable */ |
| 825 | reg = readl(&ccm_regs->CCGR3); | 825 | reg = readl(&ccm_regs->CCGR3); |
| 826 | reg |= 0x0C00; | 826 | reg |= 0x0C00; |
| 827 | writel(reg, &ccm_regs->CCGR3); | 827 | writel(reg, &ccm_regs->CCGR3); |
| 828 | 828 | ||
| 829 | panel_info.epdc_data.wv_modes.mode_init = 0; | 829 | panel_info.epdc_data.wv_modes.mode_init = 0; |
| 830 | panel_info.epdc_data.wv_modes.mode_du = 1; | 830 | panel_info.epdc_data.wv_modes.mode_du = 1; |
| 831 | panel_info.epdc_data.wv_modes.mode_gc4 = 3; | 831 | panel_info.epdc_data.wv_modes.mode_gc4 = 3; |
| 832 | panel_info.epdc_data.wv_modes.mode_gc8 = 2; | 832 | panel_info.epdc_data.wv_modes.mode_gc8 = 2; |
| 833 | panel_info.epdc_data.wv_modes.mode_gc16 = 2; | 833 | panel_info.epdc_data.wv_modes.mode_gc16 = 2; |
| 834 | panel_info.epdc_data.wv_modes.mode_gc32 = 2; | 834 | panel_info.epdc_data.wv_modes.mode_gc32 = 2; |
| 835 | 835 | ||
| 836 | panel_info.epdc_data.epdc_timings = panel_timings; | 836 | panel_info.epdc_data.epdc_timings = panel_timings; |
| 837 | 837 | ||
| 838 | setup_epdc_power(); | 838 | setup_epdc_power(); |
| 839 | } | 839 | } |
| 840 | 840 | ||
| 841 | void epdc_power_on(void) | 841 | void epdc_power_on(void) |
| 842 | { | 842 | { |
| 843 | unsigned int reg; | 843 | unsigned int reg; |
| 844 | struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; | 844 | struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; |
| 845 | 845 | ||
| 846 | /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ | 846 | /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ |
| 847 | gpio_set_value(IMX_GPIO_NR(2, 20), 1); | 847 | gpio_set_value(IMX_GPIO_NR(2, 20), 1); |
| 848 | udelay(1000); | 848 | udelay(1000); |
| 849 | 849 | ||
| 850 | /* Enable epdc signal pin */ | 850 | /* Enable epdc signal pin */ |
| 851 | epdc_enable_pins(); | 851 | epdc_enable_pins(); |
| 852 | 852 | ||
| 853 | /* Set PMIC Wakeup to high - enable Display power */ | 853 | /* Set PMIC Wakeup to high - enable Display power */ |
| 854 | gpio_set_value(IMX_GPIO_NR(3, 20), 1); | 854 | gpio_set_value(IMX_GPIO_NR(3, 20), 1); |
| 855 | 855 | ||
| 856 | /* Wait for PWRGOOD == 1 */ | 856 | /* Wait for PWRGOOD == 1 */ |
| 857 | while (1) { | 857 | while (1) { |
| 858 | reg = readl(&gpio_regs->gpio_psr); | 858 | reg = readl(&gpio_regs->gpio_psr); |
| 859 | if (!(reg & (1 << 21))) | 859 | if (!(reg & (1 << 21))) |
| 860 | break; | 860 | break; |
| 861 | 861 | ||
| 862 | udelay(100); | 862 | udelay(100); |
| 863 | } | 863 | } |
| 864 | 864 | ||
| 865 | /* Enable VCOM */ | 865 | /* Enable VCOM */ |
| 866 | gpio_set_value(IMX_GPIO_NR(3, 17), 1); | 866 | gpio_set_value(IMX_GPIO_NR(3, 17), 1); |
| 867 | 867 | ||
| 868 | udelay(500); | 868 | udelay(500); |
| 869 | } | 869 | } |
| 870 | 870 | ||
| 871 | void epdc_power_off(void) | 871 | void epdc_power_off(void) |
| 872 | { | 872 | { |
| 873 | /* Set PMIC Wakeup to low - disable Display power */ | 873 | /* Set PMIC Wakeup to low - disable Display power */ |
| 874 | gpio_set_value(IMX_GPIO_NR(3, 20), 0); | 874 | gpio_set_value(IMX_GPIO_NR(3, 20), 0); |
| 875 | 875 | ||
| 876 | /* Disable VCOM */ | 876 | /* Disable VCOM */ |
| 877 | gpio_set_value(IMX_GPIO_NR(3, 17), 0); | 877 | gpio_set_value(IMX_GPIO_NR(3, 17), 0); |
| 878 | 878 | ||
| 879 | epdc_disable_pins(); | 879 | epdc_disable_pins(); |
| 880 | 880 | ||
| 881 | /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ | 881 | /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ |
| 882 | gpio_set_value(IMX_GPIO_NR(2, 20), 0); | 882 | gpio_set_value(IMX_GPIO_NR(2, 20), 0); |
| 883 | } | 883 | } |
| 884 | #endif | 884 | #endif |
| 885 | 885 | ||
| 886 | #if defined(CONFIG_VIDEO_IPUV3) | 886 | #if defined(CONFIG_VIDEO_IPUV3) |
| 887 | static iomux_v3_cfg_t const backlight_pads[] = { | 887 | static iomux_v3_cfg_t const backlight_pads[] = { |
| 888 | /* Backlight Enable for RGB: S127 */ | 888 | /* Backlight Enable for RGB: S127 */ |
| 889 | MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), | 889 | MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 890 | #define BACKLIGHT_EN IMX_GPIO_NR(1, 00) | 890 | #define BACKLIGHT_EN IMX_GPIO_NR(1, 00) |
| 891 | /* PWM Backlight Control: S141 */ | 891 | /* PWM Backlight Control: S141 */ |
| 892 | 892 | ||
| 893 | /* Backlight Enable for LVDS: S127 */ | 893 | /* Backlight Enable for LVDS: S127 */ |
| 894 | MX6_PAD_GPIO_1__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), | 894 | MX6_PAD_GPIO_1__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 895 | /* LCD VDD Enable(for parallel LCD): S133 */ | 895 | /* LCD VDD Enable(for parallel LCD): S133 */ |
| 896 | MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), | 896 | MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 897 | }; | 897 | }; |
| 898 | 898 | ||
| 899 | static void disable_lvds(struct display_info_t const *dev) | 899 | static void disable_lvds(struct display_info_t const *dev) |
| 900 | { | 900 | { |
| 901 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; | 901 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
| 902 | 902 | ||
| 903 | int reg = readl(&iomux->gpr[2]); | 903 | int reg = readl(&iomux->gpr[2]); |
| 904 | 904 | ||
| 905 | reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK | | 905 | reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK | |
| 906 | IOMUXC_GPR2_LVDS_CH1_MODE_MASK); | 906 | IOMUXC_GPR2_LVDS_CH1_MODE_MASK); |
| 907 | 907 | ||
| 908 | writel(reg, &iomux->gpr[2]); | 908 | writel(reg, &iomux->gpr[2]); |
| 909 | } | 909 | } |
| 910 | 910 | ||
| 911 | static void do_enable_hdmi(struct display_info_t const *dev) | 911 | static void do_enable_hdmi(struct display_info_t const *dev) |
| 912 | { | 912 | { |
| 913 | disable_lvds(dev); | 913 | disable_lvds(dev); |
| 914 | imx_enable_hdmi_phy(); | 914 | imx_enable_hdmi_phy(); |
| 915 | } | 915 | } |
| 916 | 916 | ||
| 917 | static void enable_lvds(struct display_info_t const *dev) | 917 | static void enable_lvds(struct display_info_t const *dev) |
| 918 | { | 918 | { |
| 919 | struct iomuxc *iomux = (struct iomuxc *) | 919 | struct iomuxc *iomux = (struct iomuxc *) |
| 920 | IOMUXC_BASE_ADDR; | 920 | IOMUXC_BASE_ADDR; |
| 921 | u32 reg = readl(&iomux->gpr[2]); | 921 | u32 reg = readl(&iomux->gpr[2]); |
| 922 | reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | | 922 | reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | |
| 923 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT; | 923 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT; |
| 924 | writel(reg, &iomux->gpr[2]); | 924 | writel(reg, &iomux->gpr[2]); |
| 925 | } | 925 | } |
| 926 | 926 | ||
| 927 | struct display_info_t const displays[] = {{ | 927 | struct display_info_t const displays[] = {{ |
| 928 | .bus = -1, | 928 | .bus = -1, |
| 929 | .addr = 0, | 929 | .addr = 0, |
| 930 | .pixfmt = IPU_PIX_FMT_LVDS666, | 930 | .pixfmt = IPU_PIX_FMT_LVDS666, |
| 931 | .detect = NULL, | 931 | .detect = NULL, |
| 932 | .enable = enable_lvds, | 932 | .enable = enable_lvds, |
| 933 | .mode = { | 933 | .mode = { |
| 934 | .name = "Hannstar-XGA", | 934 | .name = "Hannstar-XGA", |
| 935 | .refresh = 60, | 935 | .refresh = 60, |
| 936 | .xres = 1024, | 936 | .xres = 1024, |
| 937 | .yres = 768, | 937 | .yres = 768, |
| 938 | .pixclock = 15385, | 938 | .pixclock = 15385, |
| 939 | .left_margin = 220, | 939 | .left_margin = 220, |
| 940 | .right_margin = 40, | 940 | .right_margin = 40, |
| 941 | .upper_margin = 21, | 941 | .upper_margin = 21, |
| 942 | .lower_margin = 7, | 942 | .lower_margin = 7, |
| 943 | .hsync_len = 60, | 943 | .hsync_len = 60, |
| 944 | .vsync_len = 10, | 944 | .vsync_len = 10, |
| 945 | .sync = FB_SYNC_EXT, | 945 | .sync = FB_SYNC_EXT, |
| 946 | .vmode = FB_VMODE_NONINTERLACED | 946 | .vmode = FB_VMODE_NONINTERLACED |
| 947 | } }, { | 947 | } }, { |
| 948 | .bus = -1, | 948 | .bus = -1, |
| 949 | .addr = 0, | 949 | .addr = 0, |
| 950 | .pixfmt = IPU_PIX_FMT_RGB24, | 950 | .pixfmt = IPU_PIX_FMT_RGB24, |
| 951 | .detect = NULL, | 951 | .detect = NULL, |
| 952 | .enable = do_enable_hdmi, | 952 | .enable = do_enable_hdmi, |
| 953 | .mode = { | 953 | .mode = { |
| 954 | .name = "HDMI", | 954 | .name = "HDMI", |
| 955 | .refresh = 60, | 955 | .refresh = 60, |
| 956 | .xres = 640, | 956 | .xres = 640, |
| 957 | .yres = 480, | 957 | .yres = 480, |
| 958 | .pixclock = 39721, | 958 | .pixclock = 39721, |
| 959 | .left_margin = 48, | 959 | .left_margin = 48, |
| 960 | .right_margin = 16, | 960 | .right_margin = 16, |
| 961 | .upper_margin = 33, | 961 | .upper_margin = 33, |
| 962 | .lower_margin = 10, | 962 | .lower_margin = 10, |
| 963 | .hsync_len = 96, | 963 | .hsync_len = 96, |
| 964 | .vsync_len = 2, | 964 | .vsync_len = 2, |
| 965 | .sync = 0, | 965 | .sync = 0, |
| 966 | .vmode = FB_VMODE_NONINTERLACED | 966 | .vmode = FB_VMODE_NONINTERLACED |
| 967 | } }, { | 967 | } }, { |
| 968 | .bus = -1, | 968 | .bus = -1, |
| 969 | .addr = 0, | 969 | .addr = 0, |
| 970 | .pixfmt = IPU_PIX_FMT_RGB24, | 970 | .pixfmt = IPU_PIX_FMT_RGB24, |
| 971 | .detect = NULL, | 971 | .detect = NULL, |
| 972 | .enable = enable_rgb, | 972 | .enable = enable_rgb, |
| 973 | .mode = { | 973 | .mode = { |
| 974 | .name = "SEIKO-WVGA", | 974 | .name = "SEIKO-WVGA", |
| 975 | .refresh = 57, | 975 | .refresh = 57, |
| 976 | .xres = 800, | 976 | .xres = 800, |
| 977 | .yres = 480, | 977 | .yres = 480, |
| 978 | .pixclock = 37037, | 978 | .pixclock = 37037, |
| 979 | .left_margin = 40, | 979 | .left_margin = 40, |
| 980 | .right_margin = 60, | 980 | .right_margin = 60, |
| 981 | .upper_margin = 10, | 981 | .upper_margin = 10, |
| 982 | .lower_margin = 10, | 982 | .lower_margin = 10, |
| 983 | .hsync_len = 20, | 983 | .hsync_len = 20, |
| 984 | .vsync_len = 10, | 984 | .vsync_len = 10, |
| 985 | .sync = 0, | 985 | .sync = 0, |
| 986 | .vmode = FB_VMODE_NONINTERLACED | 986 | .vmode = FB_VMODE_NONINTERLACED |
| 987 | } } }; | 987 | } } }; |
| 988 | size_t display_count = ARRAY_SIZE(displays); | 988 | size_t display_count = ARRAY_SIZE(displays); |
| 989 | 989 | ||
| 990 | static void setup_display(void) | 990 | static void setup_display(void) |
| 991 | { | 991 | { |
| 992 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | 992 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 993 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; | 993 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
| 994 | int reg; | 994 | int reg; |
| 995 | 995 | ||
| 996 | /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */ | 996 | /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */ |
| 997 | imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads)); | 997 | imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads)); |
| 998 | 998 | ||
| 999 | enable_ipu_clock(); | 999 | enable_ipu_clock(); |
| 1000 | imx_setup_hdmi(); | 1000 | imx_setup_hdmi(); |
| 1001 | 1001 | ||
| 1002 | /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ | 1002 | /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ |
| 1003 | reg = readl(&mxc_ccm->CCGR3); | 1003 | reg = readl(&mxc_ccm->CCGR3); |
| 1004 | reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; | 1004 | reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK; |
| 1005 | writel(reg, &mxc_ccm->CCGR3); | 1005 | writel(reg, &mxc_ccm->CCGR3); |
| 1006 | 1006 | ||
| 1007 | /* set LDB0, LDB1 clk select to 011/011 */ | 1007 | /* set LDB0, LDB1 clk select to 011/011 */ |
| 1008 | reg = readl(&mxc_ccm->cs2cdr); | 1008 | reg = readl(&mxc_ccm->cs2cdr); |
| 1009 | reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | 1009 | reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
| 1010 | | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); | 1010 | | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); |
| 1011 | reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | 1011 | reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
| 1012 | | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); | 1012 | | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); |
| 1013 | writel(reg, &mxc_ccm->cs2cdr); | 1013 | writel(reg, &mxc_ccm->cs2cdr); |
| 1014 | 1014 | ||
| 1015 | reg = readl(&mxc_ccm->cscmr2); | 1015 | reg = readl(&mxc_ccm->cscmr2); |
| 1016 | reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; | 1016 | reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; |
| 1017 | writel(reg, &mxc_ccm->cscmr2); | 1017 | writel(reg, &mxc_ccm->cscmr2); |
| 1018 | 1018 | ||
| 1019 | reg = readl(&mxc_ccm->chsccdr); | 1019 | reg = readl(&mxc_ccm->chsccdr); |
| 1020 | reg |= (CHSCCDR_CLK_SEL_LDB_DI0 | 1020 | reg |= (CHSCCDR_CLK_SEL_LDB_DI0 |
| 1021 | << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); | 1021 | << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); |
| 1022 | reg |= (CHSCCDR_CLK_SEL_LDB_DI0 | 1022 | reg |= (CHSCCDR_CLK_SEL_LDB_DI0 |
| 1023 | << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); | 1023 | << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); |
| 1024 | writel(reg, &mxc_ccm->chsccdr); | 1024 | writel(reg, &mxc_ccm->chsccdr); |
| 1025 | 1025 | ||
| 1026 | reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES | 1026 | reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
| 1027 | | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW | 1027 | | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
| 1028 | | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW | 1028 | | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
| 1029 | | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG | 1029 | | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
| 1030 | | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT | 1030 | | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
| 1031 | | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG | 1031 | | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
| 1032 | | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT | 1032 | | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
| 1033 | | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED | 1033 | | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED |
| 1034 | | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0; | 1034 | | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0; |
| 1035 | writel(reg, &iomux->gpr[2]); | 1035 | writel(reg, &iomux->gpr[2]); |
| 1036 | 1036 | ||
| 1037 | reg = readl(&iomux->gpr[3]); | 1037 | reg = readl(&iomux->gpr[3]); |
| 1038 | reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK | 1038 | reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
| 1039 | | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) | 1039 | | IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) |
| 1040 | | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 | 1040 | | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 |
| 1041 | << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); | 1041 | << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); |
| 1042 | writel(reg, &iomux->gpr[3]); | 1042 | writel(reg, &iomux->gpr[3]); |
| 1043 | 1043 | ||
| 1044 | /*turn on backlight*/ | 1044 | /*turn on backlight*/ |
| 1045 | 1045 | ||
| 1046 | imx_iomux_v3_setup_multiple_pads(backlight_pads, | 1046 | imx_iomux_v3_setup_multiple_pads(backlight_pads, |
| 1047 | ARRAY_SIZE(backlight_pads)); | 1047 | ARRAY_SIZE(backlight_pads)); |
| 1048 | gpio_direction_output(BACKLIGHT_EN, 1); | 1048 | gpio_direction_output(BACKLIGHT_EN, 1); |
| 1049 | gpio_direction_output(DISP0_PWR_EN, 1); | 1049 | gpio_direction_output(DISP0_PWR_EN, 1); |
| 1050 | /* enable backlight PWM 2 */ | 1050 | /* enable backlight PWM 2 */ |
| 1051 | if (pwm_init(1, 0, 0)) | 1051 | if (pwm_init(1, 0, 0)) |
| 1052 | goto error; | 1052 | goto error; |
| 1053 | /* duty cycle 500ns, period: 3000ns */ | 1053 | /* duty cycle 500ns, period: 3000ns */ |
| 1054 | if (pwm_config(1, 1000, 3000)) | 1054 | if (pwm_config(1, 1000, 3000)) |
| 1055 | goto error; | 1055 | goto error; |
| 1056 | if (pwm_enable(1)) | 1056 | if (pwm_enable(1)) |
| 1057 | goto error; | 1057 | goto error; |
| 1058 | return; | 1058 | return; |
| 1059 | 1059 | ||
| 1060 | error: | 1060 | error: |
| 1061 | puts("error init pwm for backlight\n"); | 1061 | puts("error init pwm for backlight\n"); |
| 1062 | return; | 1062 | return; |
| 1063 | } | 1063 | } |
| 1064 | #endif /* CONFIG_VIDEO_IPUV3 */ | 1064 | #endif /* CONFIG_VIDEO_IPUV3 */ |
| 1065 | 1065 | ||
| 1066 | /* | 1066 | /* |
| 1067 | * Do not overwrite the console | 1067 | * Do not overwrite the console |
| 1068 | * Use always serial for U-Boot console | 1068 | * Use always serial for U-Boot console |
| 1069 | */ | 1069 | */ |
| 1070 | int overwrite_console(void) | 1070 | int overwrite_console(void) |
| 1071 | { | 1071 | { |
| 1072 | return 1; | 1072 | return 1; |
| 1073 | } | 1073 | } |
| 1074 | 1074 | ||
| 1075 | int board_eth_init(bd_t *bis) | 1075 | int board_eth_init(bd_t *bis) |
| 1076 | { | 1076 | { |
| 1077 | #if defined(CONFIG_MAC_ADDR_IN_EEPROM) | 1077 | #if defined(CONFIG_MAC_ADDR_IN_EEPROM) |
| 1078 | 1078 | ||
| 1079 | uchar env_enetaddr[6]; | 1079 | uchar env_enetaddr[6]; |
| 1080 | int enetaddr_found; | 1080 | int enetaddr_found; |
| 1081 | 1081 | ||
| 1082 | enetaddr_found = eth_getenv_enetaddr("ethaddr", env_enetaddr); | 1082 | enetaddr_found = eth_getenv_enetaddr("ethaddr", env_enetaddr); |
| 1083 | 1083 | ||
| 1084 | uint8_t enetaddr[8]; | 1084 | uint8_t enetaddr[8]; |
| 1085 | int eeprom_mac_read; | 1085 | int eeprom_mac_read; |
| 1086 | 1086 | ||
| 1087 | /* Read Ethernet MAC address from EEPROM */ | 1087 | /* Read Ethernet MAC address from EEPROM */ |
| 1088 | eeprom_mac_read = smarcfimx6_read_mac_address(enetaddr); | 1088 | eeprom_mac_read = smarcfimx6_read_mac_address(enetaddr); |
| 1089 | 1089 | ||
| 1090 | /* | 1090 | /* |
| 1091 | * MAC address not present in the environment | 1091 | * MAC address not present in the environment |
| 1092 | * try and read the MAC address from EEPROM flash | 1092 | * try and read the MAC address from EEPROM flash |
| 1093 | * and set it. | 1093 | * and set it. |
| 1094 | */ | 1094 | */ |
| 1095 | if (!enetaddr_found) { | 1095 | if (!enetaddr_found) { |
| 1096 | if (eeprom_mac_read) | 1096 | if (eeprom_mac_read) |
| 1097 | /* Set Ethernet MAC address from EEPROM */ | 1097 | /* Set Ethernet MAC address from EEPROM */ |
| 1098 | smarcfimx6_sync_env_enetaddr(enetaddr); | 1098 | smarcfimx6_sync_env_enetaddr(enetaddr); |
| 1099 | } else { | 1099 | } else { |
| 1100 | /* | 1100 | /* |
| 1101 | * MAC address present in environment compare it with | 1101 | * MAC address present in environment compare it with |
| 1102 | * the MAC address in EEPROM and warn on mismatch | 1102 | * the MAC address in EEPROM and warn on mismatch |
| 1103 | */ | 1103 | */ |
| 1104 | if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6)) | 1104 | if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6)) |
| 1105 | printf("Warning: MAC address in EEPROM don't match " | 1105 | printf("Warning: MAC address in EEPROM don't match " |
| 1106 | "with the MAC address in the environment\n"); | 1106 | "with the MAC address in the environment\n"); |
| 1107 | printf("Default using MAC address from environment\n"); | 1107 | printf("Default using MAC address from environment\n"); |
| 1108 | } | 1108 | } |
| 1109 | 1109 | ||
| 1110 | #endif | 1110 | #endif |
| 1111 | setup_iomux_enet(); | 1111 | setup_iomux_enet(); |
| 1112 | setup_pcie(); | 1112 | setup_pcie(); |
| 1113 | 1113 | ||
| 1114 | return cpu_eth_init(bis); | 1114 | return cpu_eth_init(bis); |
| 1115 | } | 1115 | } |
| 1116 | 1116 | ||
| 1117 | #ifdef CONFIG_USB_EHCI_MX6 | 1117 | #ifdef CONFIG_USB_EHCI_MX6 |
| 1118 | #define USB_OTHERREGS_OFFSET 0x800 | 1118 | #define USB_OTHERREGS_OFFSET 0x800 |
| 1119 | #define UCTRL_PWR_POL (1 << 9) | 1119 | #define UCTRL_PWR_POL (1 << 9) |
| 1120 | 1120 | ||
| 1121 | static iomux_v3_cfg_t const usb_otg_pads[] = { | 1121 | static iomux_v3_cfg_t const usb_otg_pads[] = { |
| 1122 | MX6_PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(WEAK_PULLUP), | 1122 | MX6_PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(WEAK_PULLUP), |
| 1123 | MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP), | 1123 | MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), |
| 1124 | /* OTG Power enable */ | 1124 | /* OTG Power enable */ |
| 1125 | MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(OUTPUT_40OHM), | 1125 | MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(OUTPUT_40OHM), |
| 1126 | }; | 1126 | }; |
| 1127 | 1127 | ||
| 1128 | static iomux_v3_cfg_t const usb_hc1_pads[] = { | 1128 | static iomux_v3_cfg_t const usb_hc1_pads[] = { |
| 1129 | MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(WEAK_PULLUP), | 1129 | MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(WEAK_PULLUP), |
| 1130 | /* USB1 Power enable */ | 1130 | /* USB1 Power enable */ |
| 1131 | MX6_PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(OUTPUT_40OHM), | 1131 | MX6_PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(OUTPUT_40OHM), |
| 1132 | }; | 1132 | }; |
| 1133 | 1133 | ||
| 1134 | static void setup_usb(void) | 1134 | static void setup_usb(void) |
| 1135 | { | 1135 | { |
| 1136 | imx_iomux_v3_setup_multiple_pads(usb_otg_pads, | 1136 | imx_iomux_v3_setup_multiple_pads(usb_otg_pads, |
| 1137 | ARRAY_SIZE(usb_otg_pads)); | 1137 | ARRAY_SIZE(usb_otg_pads)); |
| 1138 | 1138 | ||
| 1139 | /* | 1139 | /* |
| 1140 | * set daisy chain for otg_pin_id on 6q. | 1140 | * set daisy chain for otg_pin_id on 6q. |
| 1141 | * for 6dl, this bit is reserved | 1141 | * for 6dl, this bit is reserved |
| 1142 | */ | 1142 | */ |
| 1143 | imx_iomux_set_gpr_register(1, 13, 1, 0); | 1143 | imx_iomux_set_gpr_register(1, 13, 1, 0); |
| 1144 | 1144 | ||
| 1145 | imx_iomux_v3_setup_multiple_pads(usb_hc1_pads, | 1145 | imx_iomux_v3_setup_multiple_pads(usb_hc1_pads, |
| 1146 | ARRAY_SIZE(usb_hc1_pads)); | 1146 | ARRAY_SIZE(usb_hc1_pads)); |
| 1147 | } | 1147 | } |
| 1148 | 1148 | ||
| 1149 | int board_ehci_hcd_init(int port) | 1149 | int board_ehci_hcd_init(int port) |
| 1150 | { | 1150 | { |
| 1151 | u32 *usbnc_usb_ctrl; | 1151 | u32 *usbnc_usb_ctrl; |
| 1152 | 1152 | ||
| 1153 | if (port > 1) | 1153 | if (port > 1) |
| 1154 | return -EINVAL; | 1154 | return -EINVAL; |
| 1155 | 1155 | ||
| 1156 | usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + | 1156 | usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + |
| 1157 | port * 4); | 1157 | port * 4); |
| 1158 | 1158 | ||
| 1159 | setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); | 1159 | setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); |
| 1160 | 1160 | ||
| 1161 | return 0; | 1161 | return 0; |
| 1162 | } | 1162 | } |
| 1163 | 1163 | ||
| 1164 | int board_ehci_power(int port, int on) | 1164 | int board_ehci_power(int port, int on) |
| 1165 | { | 1165 | { |
| 1166 | switch (port) { | 1166 | switch (port) { |
| 1167 | case 0: | 1167 | case 0: |
| 1168 | /* Set USB OTG Over Current */ | 1168 | /* Set USB OTG Over Current */ |
| 1169 | gpio_direction_input(IMX_GPIO_NR(1, 30)); | 1169 | gpio_direction_input(IMX_GPIO_NR(1, 30)); |
| 1170 | /* Trun On USB OTG Power */ | 1170 | /* Trun On USB OTG Power */ |
| 1171 | gpio_direction_output(IMX_GPIO_NR(1, 29),1); | 1171 | gpio_direction_output(IMX_GPIO_NR(1, 29),1); |
| 1172 | break; | 1172 | break; |
| 1173 | case 1: | 1173 | case 1: |
| 1174 | if (on){ | 1174 | if (on){ |
| 1175 | /* Set USB1 Over Current */ | 1175 | /* Set USB1 Over Current */ |
| 1176 | gpio_direction_input(IMX_GPIO_NR(1, 27)); | 1176 | gpio_direction_input(IMX_GPIO_NR(1, 27)); |
| 1177 | /* Trun On USB1 Power */ | 1177 | /* Trun On USB1 Power */ |
| 1178 | gpio_direction_output(IMX_GPIO_NR(1, 26),1); | 1178 | gpio_direction_output(IMX_GPIO_NR(1, 26),1); |
| 1179 | } | 1179 | } |
| 1180 | else | 1180 | else |
| 1181 | gpio_direction_output(IMX_GPIO_NR(1, 26), 0); | 1181 | gpio_direction_output(IMX_GPIO_NR(1, 26), 0); |
| 1182 | break; | 1182 | break; |
| 1183 | default: | 1183 | default: |
| 1184 | printf("MXC USB port %d not yet supported\n", port); | 1184 | printf("MXC USB port %d not yet supported\n", port); |
| 1185 | return -EINVAL; | 1185 | return -EINVAL; |
| 1186 | } | 1186 | } |
| 1187 | 1187 | ||
| 1188 | return 0; | 1188 | return 0; |
| 1189 | } | 1189 | } |
| 1190 | #endif | 1190 | #endif |
| 1191 | 1191 | ||
| 1192 | int board_early_init_f(void) | 1192 | int board_early_init_f(void) |
| 1193 | { | 1193 | { |
| 1194 | setup_iomux_wdt(); | 1194 | setup_iomux_wdt(); |
| 1195 | setup_iomux_reset_out(); | 1195 | setup_iomux_reset_out(); |
| 1196 | setup_iomux_uart1(); | 1196 | setup_iomux_uart1(); |
| 1197 | setup_iomux_uart2(); | 1197 | setup_iomux_uart2(); |
| 1198 | setup_iomux_uart4(); | 1198 | setup_iomux_uart4(); |
| 1199 | setup_iomux_uart5(); | 1199 | setup_iomux_uart5(); |
| 1200 | #if defined(CONFIG_VIDEO_IPUV3) | 1200 | #if defined(CONFIG_VIDEO_IPUV3) |
| 1201 | setup_display(); | 1201 | setup_display(); |
| 1202 | #endif | 1202 | #endif |
| 1203 | 1203 | ||
| 1204 | #ifdef CONFIG_MXC_SPI | 1204 | #ifdef CONFIG_MXC_SPI |
| 1205 | /*Unlock SPI Flash*/ | 1205 | /*Unlock SPI Flash*/ |
| 1206 | gpio_direction_output(IMX_GPIO_NR(4,20), 1); | 1206 | gpio_direction_output(IMX_GPIO_NR(4,20), 1); |
| 1207 | setup_spinor(); | 1207 | setup_spinor(); |
| 1208 | /*Lock SPI Flash and Free SPI0*/ | 1208 | /*Lock SPI Flash and Free SPI0*/ |
| 1209 | gpio_direction_output(IMX_GPIO_NR(4,20), 0); | 1209 | gpio_direction_output(IMX_GPIO_NR(4,20), 0); |
| 1210 | #endif | 1210 | #endif |
| 1211 | setup_spi1(); | 1211 | setup_spi1(); |
| 1212 | setup_flexcan1(); | 1212 | setup_flexcan1(); |
| 1213 | setup_flexcan2(); | 1213 | setup_flexcan2(); |
| 1214 | setup_gpios(); | 1214 | setup_gpios(); |
| 1215 | 1215 | ||
| 1216 | return 0; | 1216 | return 0; |
| 1217 | } | 1217 | } |
| 1218 | 1218 | ||
| 1219 | int board_init(void) | 1219 | int board_init(void) |
| 1220 | { | 1220 | { |
| 1221 | /* address of boot parameters */ | 1221 | /* address of boot parameters */ |
| 1222 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; | 1222 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| 1223 | 1223 | ||
| 1224 | setup_i2c(2, CONFIG_SYS_I2C_SPEED, | 1224 | setup_i2c(2, CONFIG_SYS_I2C_SPEED, |
| 1225 | 0x70, &i2c_pad_info3); | 1225 | 0x70, &i2c_pad_info3); |
| 1226 | 1226 | ||
| 1227 | /* Configure I2C switch (PCA9546) to enable channel 0. */ | 1227 | /* Configure I2C switch (PCA9546) to enable channel 0. */ |
| 1228 | i2c_set_bus_num(2); | 1228 | i2c_set_bus_num(2); |
| 1229 | uint8_t i2cbuf; | 1229 | uint8_t i2cbuf; |
| 1230 | i2cbuf = CONFIG_SYS_I2C_PCA9546_ENABLE; | 1230 | i2cbuf = CONFIG_SYS_I2C_PCA9546_ENABLE; |
| 1231 | if (i2c_write(CONFIG_SYS_I2C_PCA9546_ADDR, 0, | 1231 | if (i2c_write(CONFIG_SYS_I2C_PCA9546_ADDR, 0, |
| 1232 | CONFIG_SYS_I2C_PCA9546_ADDR_LEN, &i2cbuf, 1)) { | 1232 | CONFIG_SYS_I2C_PCA9546_ADDR_LEN, &i2cbuf, 1)) { |
| 1233 | printf("Write to MUX @ 0x%02x failed\n", CONFIG_SYS_I2C_PCA9546_ADDR); | 1233 | printf("Write to MUX @ 0x%02x failed\n", CONFIG_SYS_I2C_PCA9546_ADDR); |
| 1234 | return 1; | 1234 | return 1; |
| 1235 | } | 1235 | } |
| 1236 | 1236 | ||
| 1237 | #ifdef CONFIG_USB_EHCI_MX6 | 1237 | #ifdef CONFIG_USB_EHCI_MX6 |
| 1238 | setup_usb(); | 1238 | setup_usb(); |
| 1239 | #endif | 1239 | #endif |
| 1240 | 1240 | ||
| 1241 | #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) | 1241 | #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) |
| 1242 | setup_epdc(); | 1242 | setup_epdc(); |
| 1243 | #endif | 1243 | #endif |
| 1244 | 1244 | ||
| 1245 | #ifdef CONFIG_CMD_SATA | 1245 | #ifdef CONFIG_CMD_SATA |
| 1246 | setup_sata(); | 1246 | setup_sata(); |
| 1247 | #endif | 1247 | #endif |
| 1248 | 1248 | ||
| 1249 | return 0; | 1249 | return 0; |
| 1250 | } | 1250 | } |
| 1251 | 1251 | ||
| 1252 | #ifdef CONFIG_CMD_BMODE | 1252 | #ifdef CONFIG_CMD_BMODE |
| 1253 | static const struct boot_mode board_boot_modes[] = { | 1253 | static const struct boot_mode board_boot_modes[] = { |
| 1254 | /* 4 bit bus width */ | 1254 | /* 4 bit bus width */ |
| 1255 | {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, | 1255 | {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, |
| 1256 | {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, | 1256 | {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, |
| 1257 | /* 8 bit bus width */ | 1257 | /* 8 bit bus width */ |
| 1258 | {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, | 1258 | {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)}, |
| 1259 | {NULL, 0}, | 1259 | {NULL, 0}, |
| 1260 | }; | 1260 | }; |
| 1261 | #endif | 1261 | #endif |
| 1262 | 1262 | ||
| 1263 | int board_late_init(void) | 1263 | int board_late_init(void) |
| 1264 | { | 1264 | { |
| 1265 | // Make sure we enable ECSPI2 clock | 1265 | // Make sure we enable ECSPI2 clock |
| 1266 | int reg; | 1266 | int reg; |
| 1267 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | 1267 | struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 1268 | reg = readl(&mxc_ccm->CCGR1); | 1268 | reg = readl(&mxc_ccm->CCGR1); |
| 1269 | reg |= MXC_CCM_CCGR1_ECSPI2S_MASK; | 1269 | reg |= MXC_CCM_CCGR1_ECSPI2S_MASK; |
| 1270 | writel(reg, &mxc_ccm->CCGR1); | 1270 | writel(reg, &mxc_ccm->CCGR1); |
| 1271 | #ifdef CONFIG_CMD_BMODE | 1271 | #ifdef CONFIG_CMD_BMODE |
| 1272 | add_board_boot_modes(board_boot_modes); | 1272 | add_board_boot_modes(board_boot_modes); |
| 1273 | #endif | 1273 | #endif |
| 1274 | 1274 | ||
| 1275 | #ifdef CONFIG_ENV_IS_IN_MMC | 1275 | #ifdef CONFIG_ENV_IS_IN_MMC |
| 1276 | board_late_mmc_env_init(); | 1276 | board_late_mmc_env_init(); |
| 1277 | #endif | 1277 | #endif |
| 1278 | 1278 | ||
| 1279 | /* Check Board Information */ | 1279 | /* Check Board Information */ |
| 1280 | setup_i2c(0, CONFIG_SYS_I2C_SPEED, | 1280 | setup_i2c(0, CONFIG_SYS_I2C_SPEED, |
| 1281 | 0x50, &i2c_pad_info1); | 1281 | 0x50, &i2c_pad_info1); |
| 1282 | 1282 | ||
| 1283 | struct smarcfimx6_id header; | 1283 | struct smarcfimx6_id header; |
| 1284 | 1284 | ||
| 1285 | if (read_eeprom(&header) < 0) | 1285 | if (read_eeprom(&header) < 0) |
| 1286 | puts("Could not get board ID.\n"); | 1286 | puts("Could not get board ID.\n"); |
| 1287 | 1287 | ||
| 1288 | puts("-----------------------------------------\n"); | 1288 | puts("-----------------------------------------\n"); |
| 1289 | printf("Board ID: %.*s\n", | 1289 | printf("Board ID: %.*s\n", |
| 1290 | sizeof(header.name), header.name); | 1290 | sizeof(header.name), header.name); |
| 1291 | printf("Board Revision: %.*s\n", | 1291 | printf("Board Revision: %.*s\n", |
| 1292 | sizeof(header.version), header.version); | 1292 | sizeof(header.version), header.version); |
| 1293 | printf("Board Serial#: %.*s\n", | 1293 | printf("Board Serial#: %.*s\n", |
| 1294 | sizeof(header.serial), header.serial); | 1294 | sizeof(header.serial), header.serial); |
| 1295 | puts("-----------------------------------------\n"); | 1295 | puts("-----------------------------------------\n"); |
| 1296 | 1296 | ||
| 1297 | /* SMARC BOOT_SEL*/ | 1297 | /* SMARC BOOT_SEL*/ |
| 1298 | if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { | 1298 | if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { |
| 1299 | puts("BOOT_SEL Detected: OFF OFF OFF, Load zImage from Carrier SATA...\n"); | 1299 | puts("BOOT_SEL Detected: OFF OFF OFF, Load zImage from Carrier SATA...\n"); |
| 1300 | if (!getenv("bootcmd")) | 1300 | if (!getenv("bootcmd")) |
| 1301 | setenv("bootcmd", "boota sata"); | 1301 | setenv("bootcmd", "boota sata"); |
| 1302 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { | 1302 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { |
| 1303 | puts("BOOT_SEL Detected: OFF OFF ON, USB Boot Up Not Defined...Carrier SPI Boot Not Supported...\n"); | 1303 | puts("BOOT_SEL Detected: OFF OFF ON, USB Boot Up Not Defined...Carrier SPI Boot Not Supported...\n"); |
| 1304 | hang(); | 1304 | hang(); |
| 1305 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { | 1305 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { |
| 1306 | puts("BOOT_SEL Detected: OFF ON OFF, Load zImage from Carrier SDMMC...\n"); | 1306 | puts("BOOT_SEL Detected: OFF ON OFF, Load zImage from Carrier SDMMC...\n"); |
| 1307 | setenv_ulong("mmcdev", 1); | 1307 | setenv_ulong("mmcdev", 1); |
| 1308 | if (!getenv("fastboot_dev")) | 1308 | if (!getenv("fastboot_dev")) |
| 1309 | setenv("fastboot_dev", "mmc1"); | 1309 | setenv("fastboot_dev", "mmc1"); |
| 1310 | if (!getenv("bootcmd")) | 1310 | if (!getenv("bootcmd")) |
| 1311 | setenv("bootcmd", "boota mmc1"); | 1311 | setenv("bootcmd", "boota mmc1"); |
| 1312 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { | 1312 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { |
| 1313 | puts("BOOT_SEL Detected: ON OFF OFF, Load zImage from Carrier SD Card...\n"); | 1313 | puts("BOOT_SEL Detected: ON OFF OFF, Load zImage from Carrier SD Card...\n"); |
| 1314 | setenv_ulong("mmcdev", 0); | 1314 | setenv_ulong("mmcdev", 0); |
| 1315 | if (!getenv("fastboot_dev")) | 1315 | if (!getenv("fastboot_dev")) |
| 1316 | setenv("fastboot_dev", "mmc0"); | 1316 | setenv("fastboot_dev", "mmc0"); |
| 1317 | if (!getenv("bootcmd")) | 1317 | if (!getenv("bootcmd")) |
| 1318 | setenv("bootcmd", "boota mmc0"); | 1318 | setenv("bootcmd", "boota mmc0"); |
| 1319 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { | 1319 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { |
| 1320 | puts("BOOT_SEL Detected: OFF ON ON, Load zImage from Module eMMC Flash...\n"); | 1320 | puts("BOOT_SEL Detected: OFF ON ON, Load zImage from Module eMMC Flash...\n"); |
| 1321 | setenv_ulong("mmcdev", 2); | 1321 | setenv_ulong("mmcdev", 2); |
| 1322 | if (!getenv("fastboot_dev")) | 1322 | if (!getenv("fastboot_dev")) |
| 1323 | setenv("fastboot_dev", "mmc2"); | 1323 | setenv("fastboot_dev", "mmc2"); |
| 1324 | if (!getenv("bootcmd")) | 1324 | if (!getenv("bootcmd")) |
| 1325 | setenv("bootcmd", "boota mmc2"); | 1325 | setenv("bootcmd", "boota mmc2"); |
| 1326 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { | 1326 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { |
| 1327 | puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n"); | 1327 | puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n"); |
| 1328 | setenv("bootcmd", "run netboot;"); | 1328 | setenv("bootcmd", "run netboot;"); |
| 1329 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { | 1329 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { |
| 1330 | puts("Carrier SPI Boot 110\n"); | 1330 | puts("Carrier SPI Boot 110\n"); |
| 1331 | hang(); | 1331 | hang(); |
| 1332 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { | 1332 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { |
| 1333 | puts("BOOT_SEL Detected: ON ON ON, MOdule SPI Boot up is Default, Load zImage from Module eMMC...\n"); | 1333 | puts("BOOT_SEL Detected: ON ON ON, MOdule SPI Boot up is Default, Load zImage from Module eMMC...\n"); |
| 1334 | setenv_ulong("mmcdev", 2); | 1334 | setenv_ulong("mmcdev", 2); |
| 1335 | if (!getenv("fastboot_dev")) | 1335 | if (!getenv("fastboot_dev")) |
| 1336 | setenv("fastboot_dev", "mmc2"); | 1336 | setenv("fastboot_dev", "mmc2"); |
| 1337 | if (!getenv("bootcmd")) | 1337 | if (!getenv("bootcmd")) |
| 1338 | setenv("bootcmd", "boota mmc2"); | 1338 | setenv("bootcmd", "boota mmc2"); |
| 1339 | } else { | 1339 | } else { |
| 1340 | puts("unsupported boot devices\n"); | 1340 | puts("unsupported boot devices\n"); |
| 1341 | hang(); | 1341 | hang(); |
| 1342 | } | 1342 | } |
| 1343 | 1343 | ||
| 1344 | return 0; | 1344 | return 0; |
| 1345 | } | 1345 | } |
| 1346 | 1346 | ||
| 1347 | #ifdef CONFIG_FSL_FASTBOOT | 1347 | #ifdef CONFIG_FSL_FASTBOOT |
| 1348 | 1348 | ||
| 1349 | void board_fastboot_setup(void) | 1349 | void board_fastboot_setup(void) |
| 1350 | { | 1350 | { |
| 1351 | #if defined(CONFIG_FASTBOOT_STORAGE_SATA) | 1351 | #if defined(CONFIG_FASTBOOT_STORAGE_SATA) |
| 1352 | if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) | 1352 | if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) |
| 1353 | if (!getenv("fastboot_dev")) | 1353 | if (!getenv("fastboot_dev")) |
| 1354 | setenv("fastboot_dev", "sata"); | 1354 | setenv("fastboot_dev", "sata"); |
| 1355 | if (!getenv("bootcmd")) | 1355 | if (!getenv("bootcmd")) |
| 1356 | setenv("bootcmd", "boota sata"); | 1356 | setenv("bootcmd", "boota sata"); |
| 1357 | #endif /*CONFIG_FASTBOOT_STORAGE_SATA*/ | 1357 | #endif /*CONFIG_FASTBOOT_STORAGE_SATA*/ |
| 1358 | #if defined(CONFIG_FASTBOOT_STORAGE_MMC) | 1358 | #if defined(CONFIG_FASTBOOT_STORAGE_MMC) |
| 1359 | if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { | 1359 | if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { |
| 1360 | setenv_ulong("mmcdev", 0); | 1360 | setenv_ulong("mmcdev", 0); |
| 1361 | if (!getenv("fastboot_dev")) | 1361 | if (!getenv("fastboot_dev")) |
| 1362 | setenv("fastboot_dev", "mmc0"); | 1362 | setenv("fastboot_dev", "mmc0"); |
| 1363 | if (!getenv("bootcmd")) | 1363 | if (!getenv("bootcmd")) |
| 1364 | setenv("bootcmd", "boota mmc0"); | 1364 | setenv("bootcmd", "boota mmc0"); |
| 1365 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { | 1365 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { |
| 1366 | setenv_ulong("mmcdev", 1); | 1366 | setenv_ulong("mmcdev", 1); |
| 1367 | if (!getenv("fastboot_dev")) | 1367 | if (!getenv("fastboot_dev")) |
| 1368 | setenv("fastboot_dev", "mmc1"); | 1368 | setenv("fastboot_dev", "mmc1"); |
| 1369 | if (!getenv("bootcmd")) | 1369 | if (!getenv("bootcmd")) |
| 1370 | setenv("bootcmd", "boota mmc1"); | 1370 | setenv("bootcmd", "boota mmc1"); |
| 1371 | } else if((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { | 1371 | } else if((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { |
| 1372 | setenv_ulong("mmcdev", 2); | 1372 | setenv_ulong("mmcdev", 2); |
| 1373 | if (!getenv("fastboot_dev")) | 1373 | if (!getenv("fastboot_dev")) |
| 1374 | setenv("fastboot_dev", "mmc2"); | 1374 | setenv("fastboot_dev", "mmc2"); |
| 1375 | if (!getenv("bootcmd")) | 1375 | if (!getenv("bootcmd")) |
| 1376 | setenv("bootcmd", "boota mmc2"); | 1376 | setenv("bootcmd", "boota mmc2"); |
| 1377 | #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ | 1377 | #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ |
| 1378 | } else { | 1378 | } else { |
| 1379 | printf("unsupported boot devices\n"); | 1379 | printf("unsupported boot devices\n"); |
| 1380 | return; | 1380 | return; |
| 1381 | } | 1381 | } |
| 1382 | 1382 | ||
| 1383 | } | 1383 | } |
| 1384 | 1384 | ||
| 1385 | #ifdef CONFIG_ANDROID_RECOVERY | 1385 | #ifdef CONFIG_ANDROID_RECOVERY |
| 1386 | 1386 | ||
| 1387 | /* Use LID# as Recovery Key */ | 1387 | /* Use LID# as Recovery Key */ |
| 1388 | #define GPIO_VOL_DN_KEY IMX_GPIO_NR(2, 25) | 1388 | #define GPIO_VOL_DN_KEY IMX_GPIO_NR(2, 25) |
| 1389 | iomux_v3_cfg_t const recovery_key_pads[] = { | 1389 | iomux_v3_cfg_t const recovery_key_pads[] = { |
| 1390 | (MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), | 1390 | (MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)), |
| 1391 | }; | 1391 | }; |
| 1392 | 1392 | ||
| 1393 | int check_recovery_cmd_file(void) | 1393 | int check_recovery_cmd_file(void) |
| 1394 | { | 1394 | { |
| 1395 | int button_pressed = 0; | 1395 | int button_pressed = 0; |
| 1396 | int recovery_mode = 0; | 1396 | int recovery_mode = 0; |
| 1397 | 1397 | ||
| 1398 | recovery_mode = recovery_check_and_clean_flag(); | 1398 | recovery_mode = recovery_check_and_clean_flag(); |
| 1399 | 1399 | ||
| 1400 | /* Check Recovery Combo Button press or not. */ | 1400 | /* Check Recovery Combo Button press or not. */ |
| 1401 | imx_iomux_v3_setup_multiple_pads(recovery_key_pads, | 1401 | imx_iomux_v3_setup_multiple_pads(recovery_key_pads, |
| 1402 | ARRAY_SIZE(recovery_key_pads)); | 1402 | ARRAY_SIZE(recovery_key_pads)); |
| 1403 | 1403 | ||
| 1404 | gpio_direction_input(GPIO_VOL_DN_KEY); | 1404 | gpio_direction_input(GPIO_VOL_DN_KEY); |
| 1405 | 1405 | ||
| 1406 | if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */ | 1406 | if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */ |
| 1407 | button_pressed = 1; | 1407 | button_pressed = 1; |
| 1408 | printf("Recovery key pressed\n"); | 1408 | printf("Recovery key pressed\n"); |
| 1409 | } | 1409 | } |
| 1410 | 1410 | ||
| 1411 | return recovery_mode || button_pressed; | 1411 | return recovery_mode || button_pressed; |
| 1412 | } | 1412 | } |
| 1413 | 1413 | ||
| 1414 | void board_recovery_setup(void) | 1414 | void board_recovery_setup(void) |
| 1415 | { | 1415 | { |
| 1416 | #if defined(CONFIG_FASTBOOT_STORAGE_SATA) | 1416 | #if defined(CONFIG_FASTBOOT_STORAGE_SATA) |
| 1417 | if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) | 1417 | if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) |
| 1418 | puts("Entering Recovery Mode into SATA...\n"); | 1418 | puts("Entering Recovery Mode into SATA...\n"); |
| 1419 | if (!getenv("bootcmd_android_recovery")) | 1419 | if (!getenv("bootcmd_android_recovery")) |
| 1420 | setenv("bootcmd_android_recovery", | 1420 | setenv("bootcmd_android_recovery", |
| 1421 | "boota sata recovery"); | 1421 | "boota sata recovery"); |
| 1422 | #endif /*CONFIG_FASTBOOT_STORAGE_SATA*/ | 1422 | #endif /*CONFIG_FASTBOOT_STORAGE_SATA*/ |
| 1423 | #if defined(CONFIG_FASTBOOT_STORAGE_MMC) | 1423 | #if defined(CONFIG_FASTBOOT_STORAGE_MMC) |
| 1424 | if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { | 1424 | if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { |
| 1425 | puts("Entering Recovery Mode into Carrier SD Card...\n"); | 1425 | puts("Entering Recovery Mode into Carrier SD Card...\n"); |
| 1426 | setenv_ulong("mmcdev", 0); | 1426 | setenv_ulong("mmcdev", 0); |
| 1427 | if (!getenv("bootcmd_android_recovery")) | 1427 | if (!getenv("bootcmd_android_recovery")) |
| 1428 | setenv("bootcmd_android_recovery", | 1428 | setenv("bootcmd_android_recovery", |
| 1429 | "boota mmc0 recovery"); | 1429 | "boota mmc0 recovery"); |
| 1430 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { | 1430 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { |
| 1431 | puts("Entering Recovery Mode into Carrier SDMMC...\n"); | 1431 | puts("Entering Recovery Mode into Carrier SDMMC...\n"); |
| 1432 | setenv_ulong("mmcdev", 1); | 1432 | setenv_ulong("mmcdev", 1); |
| 1433 | if (!getenv("bootcmd_android_recovery")) | 1433 | if (!getenv("bootcmd_android_recovery")) |
| 1434 | setenv("bootcmd_android_recovery", | 1434 | setenv("bootcmd_android_recovery", |
| 1435 | "boota mmc1 recovery"); | 1435 | "boota mmc1 recovery"); |
| 1436 | } else if((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { | 1436 | } else if((gpio_get_value(IMX_GPIO_NR(1, 4)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { |
| 1437 | puts("Entering Recovery Mode into on Module eMMC Flash...\n"); | 1437 | puts("Entering Recovery Mode into on Module eMMC Flash...\n"); |
| 1438 | setenv_ulong("mmcdev", 2); | 1438 | setenv_ulong("mmcdev", 2); |
| 1439 | if (!getenv("bootcmd_android_recovery")) | 1439 | if (!getenv("bootcmd_android_recovery")) |
| 1440 | setenv("bootcmd_android_recovery", | 1440 | setenv("bootcmd_android_recovery", |
| 1441 | "boota mmc2 recovery"); | 1441 | "boota mmc2 recovery"); |
| 1442 | #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ | 1442 | #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/ |
| 1443 | } else { | 1443 | } else { |
| 1444 | puts("Unsupported bootup device for recovery\n"); | 1444 | puts("Unsupported bootup device for recovery\n"); |
| 1445 | return; | 1445 | return; |
| 1446 | } | 1446 | } |
| 1447 | 1447 | ||
| 1448 | printf("setup env for recovery..\n"); | 1448 | printf("setup env for recovery..\n"); |
| 1449 | setenv("bootcmd", "run bootcmd_android_recovery"); | 1449 | setenv("bootcmd", "run bootcmd_android_recovery"); |
| 1450 | } | 1450 | } |
| 1451 | 1451 | ||
| 1452 | #endif /*CONFIG_ANDROID_RECOVERY*/ | 1452 | #endif /*CONFIG_ANDROID_RECOVERY*/ |
| 1453 | 1453 | ||
| 1454 | #endif /*CONFIG_FSL_FASTBOOT*/ | 1454 | #endif /*CONFIG_FSL_FASTBOOT*/ |
| 1455 | 1455 | ||
| 1456 | #ifdef CONFIG_SPL_BUILD | 1456 | #ifdef CONFIG_SPL_BUILD |
| 1457 | #include <spl.h> | 1457 | #include <spl.h> |
| 1458 | #include <libfdt.h> | 1458 | #include <libfdt.h> |
| 1459 | 1459 | ||
| 1460 | const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { | 1460 | const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { |
| 1461 | .dram_sdclk_0 = 0x00020030, | 1461 | .dram_sdclk_0 = 0x00020030, |
| 1462 | .dram_sdclk_1 = 0x00020030, | 1462 | .dram_sdclk_1 = 0x00020030, |
| 1463 | .dram_cas = 0x00020030, | 1463 | .dram_cas = 0x00020030, |
| 1464 | .dram_ras = 0x00020030, | 1464 | .dram_ras = 0x00020030, |
| 1465 | .dram_reset = 0x00020030, | 1465 | .dram_reset = 0x00020030, |
| 1466 | .dram_sdcke0 = 0x00003000, | 1466 | .dram_sdcke0 = 0x00003000, |
| 1467 | .dram_sdcke1 = 0x00003000, | 1467 | .dram_sdcke1 = 0x00003000, |
| 1468 | .dram_sdba2 = 0x00000000, | 1468 | .dram_sdba2 = 0x00000000, |
| 1469 | .dram_sdodt0 = 0x00003030, | 1469 | .dram_sdodt0 = 0x00003030, |
| 1470 | .dram_sdodt1 = 0x00003030, | 1470 | .dram_sdodt1 = 0x00003030, |
| 1471 | .dram_sdqs0 = 0x00000030, | 1471 | .dram_sdqs0 = 0x00000030, |
| 1472 | .dram_sdqs1 = 0x00000030, | 1472 | .dram_sdqs1 = 0x00000030, |
| 1473 | .dram_sdqs2 = 0x00000030, | 1473 | .dram_sdqs2 = 0x00000030, |
| 1474 | .dram_sdqs3 = 0x00000030, | 1474 | .dram_sdqs3 = 0x00000030, |
| 1475 | .dram_sdqs4 = 0x00000030, | 1475 | .dram_sdqs4 = 0x00000030, |
| 1476 | .dram_sdqs5 = 0x00000030, | 1476 | .dram_sdqs5 = 0x00000030, |
| 1477 | .dram_sdqs6 = 0x00000030, | 1477 | .dram_sdqs6 = 0x00000030, |
| 1478 | .dram_sdqs7 = 0x00000030, | 1478 | .dram_sdqs7 = 0x00000030, |
| 1479 | .dram_dqm0 = 0x00020030, | 1479 | .dram_dqm0 = 0x00020030, |
| 1480 | .dram_dqm1 = 0x00020030, | 1480 | .dram_dqm1 = 0x00020030, |
| 1481 | .dram_dqm2 = 0x00020030, | 1481 | .dram_dqm2 = 0x00020030, |
| 1482 | .dram_dqm3 = 0x00020030, | 1482 | .dram_dqm3 = 0x00020030, |
| 1483 | .dram_dqm4 = 0x00020030, | 1483 | .dram_dqm4 = 0x00020030, |
| 1484 | .dram_dqm5 = 0x00020030, | 1484 | .dram_dqm5 = 0x00020030, |
| 1485 | .dram_dqm6 = 0x00020030, | 1485 | .dram_dqm6 = 0x00020030, |
| 1486 | .dram_dqm7 = 0x00020030, | 1486 | .dram_dqm7 = 0x00020030, |
| 1487 | }; | 1487 | }; |
| 1488 | 1488 | ||
| 1489 | const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { | 1489 | const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { |
| 1490 | .grp_ddr_type = 0x000C0000, | 1490 | .grp_ddr_type = 0x000C0000, |
| 1491 | .grp_ddrmode_ctl = 0x00020000, | 1491 | .grp_ddrmode_ctl = 0x00020000, |
| 1492 | .grp_ddrpke = 0x00000000, | 1492 | .grp_ddrpke = 0x00000000, |
| 1493 | .grp_addds = 0x00000030, | 1493 | .grp_addds = 0x00000030, |
| 1494 | .grp_ctlds = 0x00000030, | 1494 | .grp_ctlds = 0x00000030, |
| 1495 | .grp_ddrmode = 0x00020000, | 1495 | .grp_ddrmode = 0x00020000, |
| 1496 | .grp_b0ds = 0x00000030, | 1496 | .grp_b0ds = 0x00000030, |
| 1497 | .grp_b1ds = 0x00000030, | 1497 | .grp_b1ds = 0x00000030, |
| 1498 | .grp_b2ds = 0x00000030, | 1498 | .grp_b2ds = 0x00000030, |
| 1499 | .grp_b3ds = 0x00000030, | 1499 | .grp_b3ds = 0x00000030, |
| 1500 | .grp_b4ds = 0x00000030, | 1500 | .grp_b4ds = 0x00000030, |
| 1501 | .grp_b5ds = 0x00000030, | 1501 | .grp_b5ds = 0x00000030, |
| 1502 | .grp_b6ds = 0x00000030, | 1502 | .grp_b6ds = 0x00000030, |
| 1503 | .grp_b7ds = 0x00000030, | 1503 | .grp_b7ds = 0x00000030, |
| 1504 | }; | 1504 | }; |
| 1505 | 1505 | ||
| 1506 | const struct mx6_mmdc_calibration mx6_mmcd_calib = { | 1506 | const struct mx6_mmdc_calibration mx6_mmcd_calib = { |
| 1507 | .p0_mpwldectrl0 = 0x001F001F, | 1507 | .p0_mpwldectrl0 = 0x001F001F, |
| 1508 | .p0_mpwldectrl1 = 0x001F001F, | 1508 | .p0_mpwldectrl1 = 0x001F001F, |
| 1509 | .p1_mpwldectrl0 = 0x00440044, | 1509 | .p1_mpwldectrl0 = 0x00440044, |
| 1510 | .p1_mpwldectrl1 = 0x00440044, | 1510 | .p1_mpwldectrl1 = 0x00440044, |
| 1511 | .p0_mpdgctrl0 = 0x434B0350, | 1511 | .p0_mpdgctrl0 = 0x434B0350, |
| 1512 | .p0_mpdgctrl1 = 0x034C0359, | 1512 | .p0_mpdgctrl1 = 0x034C0359, |
| 1513 | .p1_mpdgctrl0 = 0x434B0350, | 1513 | .p1_mpdgctrl0 = 0x434B0350, |
| 1514 | .p1_mpdgctrl1 = 0x03650348, | 1514 | .p1_mpdgctrl1 = 0x03650348, |
| 1515 | .p0_mprddlctl = 0x4436383B, | 1515 | .p0_mprddlctl = 0x4436383B, |
| 1516 | .p1_mprddlctl = 0x39393341, | 1516 | .p1_mprddlctl = 0x39393341, |
| 1517 | .p0_mpwrdlctl = 0x35373933, | 1517 | .p0_mpwrdlctl = 0x35373933, |
| 1518 | .p1_mpwrdlctl = 0x48254A36, | 1518 | .p1_mpwrdlctl = 0x48254A36, |
| 1519 | }; | 1519 | }; |
| 1520 | 1520 | ||
| 1521 | static struct mx6_ddr3_cfg mem_ddr = { | 1521 | static struct mx6_ddr3_cfg mem_ddr = { |
| 1522 | .mem_speed = 1600, | 1522 | .mem_speed = 1600, |
| 1523 | .density = 4, | 1523 | .density = 4, |
| 1524 | .width = 64, | 1524 | .width = 64, |
| 1525 | .banks = 8, | 1525 | .banks = 8, |
| 1526 | .rowaddr = 14, | 1526 | .rowaddr = 14, |
| 1527 | .coladdr = 10, | 1527 | .coladdr = 10, |
| 1528 | .pagesz = 2, | 1528 | .pagesz = 2, |
| 1529 | .trcd = 1375, | 1529 | .trcd = 1375, |
| 1530 | .trcmin = 4875, | 1530 | .trcmin = 4875, |
| 1531 | .trasmin = 3500, | 1531 | .trasmin = 3500, |
| 1532 | }; | 1532 | }; |
| 1533 | 1533 | ||
| 1534 | static void ccgr_init(void) | 1534 | static void ccgr_init(void) |
| 1535 | { | 1535 | { |
| 1536 | struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | 1536 | struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; |
| 1537 | 1537 | ||
| 1538 | writel(0x00C03F3F, &ccm->CCGR0); | 1538 | writel(0x00C03F3F, &ccm->CCGR0); |
| 1539 | writel(0x0030FC03, &ccm->CCGR1); | 1539 | writel(0x0030FC03, &ccm->CCGR1); |
| 1540 | writel(0x0FFFC000, &ccm->CCGR2); | 1540 | writel(0x0FFFC000, &ccm->CCGR2); |
| 1541 | writel(0x3FF00000, &ccm->CCGR3); | 1541 | writel(0x3FF00000, &ccm->CCGR3); |
| 1542 | writel(0x00FFF300, &ccm->CCGR4); | 1542 | writel(0x00FFF300, &ccm->CCGR4); |
| 1543 | writel(0x0F0000C3, &ccm->CCGR5); | 1543 | writel(0x0F0000C3, &ccm->CCGR5); |
| 1544 | writel(0x000003FF, &ccm->CCGR6); | 1544 | writel(0x000003FF, &ccm->CCGR6); |
| 1545 | } | 1545 | } |
| 1546 | 1546 | ||
| 1547 | static void gpr_init(void) | 1547 | static void gpr_init(void) |
| 1548 | { | 1548 | { |
| 1549 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; | 1549 | struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; |
| 1550 | 1550 | ||
| 1551 | /* enable AXI cache for VDOA/VPU/IPU */ | 1551 | /* enable AXI cache for VDOA/VPU/IPU */ |
| 1552 | writel(0xF00000CF, &iomux->gpr[4]); | 1552 | writel(0xF00000CF, &iomux->gpr[4]); |
| 1553 | /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ | 1553 | /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ |
| 1554 | writel(0x007F007F, &iomux->gpr[6]); | 1554 | writel(0x007F007F, &iomux->gpr[6]); |
| 1555 | writel(0x007F007F, &iomux->gpr[7]); | 1555 | writel(0x007F007F, &iomux->gpr[7]); |
| 1556 | } | 1556 | } |
| 1557 | 1557 | ||
| 1558 | /* | 1558 | /* |
| 1559 | * This section requires the differentiation between iMX6 Sabre boards, but | 1559 | * This section requires the differentiation between iMX6 Sabre boards, but |
| 1560 | * for now, it will configure only for the mx6q variant. | 1560 | * for now, it will configure only for the mx6q variant. |
| 1561 | */ | 1561 | */ |
| 1562 | static void spl_dram_init(void) | 1562 | static void spl_dram_init(void) |
| 1563 | { | 1563 | { |
| 1564 | struct mx6_ddr_sysinfo sysinfo = { | 1564 | struct mx6_ddr_sysinfo sysinfo = { |
| 1565 | /* width of data bus:0=16,1=32,2=64 */ | 1565 | /* width of data bus:0=16,1=32,2=64 */ |
| 1566 | .dsize = mem_ddr.width/32, | 1566 | .dsize = mem_ddr.width/32, |
| 1567 | /* config for full 4GB range so that get_mem_size() works */ | 1567 | /* config for full 4GB range so that get_mem_size() works */ |
| 1568 | .cs_density = 32, /* 32Gb per CS */ | 1568 | .cs_density = 32, /* 32Gb per CS */ |
| 1569 | /* single chip select */ | 1569 | /* single chip select */ |
| 1570 | .ncs = 1, | 1570 | .ncs = 1, |
| 1571 | .cs1_mirror = 0, | 1571 | .cs1_mirror = 0, |
| 1572 | .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ | 1572 | .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ |
| 1573 | #ifdef RTT_NOM_120OHM | 1573 | #ifdef RTT_NOM_120OHM |
| 1574 | .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ | 1574 | .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ |
| 1575 | #else | 1575 | #else |
| 1576 | .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ | 1576 | .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ |
| 1577 | #endif | 1577 | #endif |
| 1578 | .walat = 1, /* Write additional latency */ | 1578 | .walat = 1, /* Write additional latency */ |
| 1579 | .ralat = 5, /* Read additional latency */ | 1579 | .ralat = 5, /* Read additional latency */ |
| 1580 | .mif3_mode = 3, /* Command prediction working mode */ | 1580 | .mif3_mode = 3, /* Command prediction working mode */ |
| 1581 | .bi_on = 1, /* Bank interleaving enabled */ | 1581 | .bi_on = 1, /* Bank interleaving enabled */ |
| 1582 | .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ | 1582 | .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ |
| 1583 | .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ | 1583 | .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ |
| 1584 | }; | 1584 | }; |
| 1585 | 1585 | ||
| 1586 | mx6dq_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); | 1586 | mx6dq_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); |
| 1587 | mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); | 1587 | mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); |
| 1588 | } | 1588 | } |
| 1589 | 1589 | ||
| 1590 | void board_init_f(ulong dummy) | 1590 | void board_init_f(ulong dummy) |
| 1591 | { | 1591 | { |
| 1592 | /* setup AIPS and disable watchdog */ | 1592 | /* setup AIPS and disable watchdog */ |
| 1593 | arch_cpu_init(); | 1593 | arch_cpu_init(); |
| 1594 | 1594 | ||
| 1595 | ccgr_init(); | 1595 | ccgr_init(); |
| 1596 | gpr_init(); | 1596 | gpr_init(); |
| 1597 | 1597 | ||
| 1598 | /* iomux and setup of i2c */ | 1598 | /* iomux and setup of i2c */ |
| 1599 | board_early_init_f(); | 1599 | board_early_init_f(); |
| 1600 | 1600 | ||
| 1601 | /* setup GP timer */ | 1601 | /* setup GP timer */ |
| 1602 | timer_init(); | 1602 | timer_init(); |
| 1603 | 1603 | ||
| 1604 | /* UART clocks enabled and gd valid - init serial console */ | 1604 | /* UART clocks enabled and gd valid - init serial console */ |
| 1605 | preloader_console_init(); | 1605 | preloader_console_init(); |
| 1606 | 1606 | ||
| 1607 | /* DDR initialization */ | 1607 | /* DDR initialization */ |
| 1608 | spl_dram_init(); | 1608 | spl_dram_init(); |
| 1609 | 1609 | ||
| 1610 | /* Clear the BSS. */ | 1610 | /* Clear the BSS. */ |
| 1611 | memset(__bss_start, 0, __bss_end - __bss_start); | 1611 | memset(__bss_start, 0, __bss_end - __bss_start); |
| 1612 | 1612 | ||
| 1613 | /* load/boot image from boot device */ | 1613 | /* load/boot image from boot device */ |
| 1614 | board_init_r(NULL, 0); | 1614 | board_init_r(NULL, 0); |
| 1615 | } | 1615 | } |
| 1616 | 1616 | ||
| 1617 | void reset_cpu(ulong addr) | 1617 | void reset_cpu(ulong addr) |
| 1618 | { | 1618 | { |
| 1619 | } | 1619 | } |
| 1620 | #endif | 1620 | #endif |
| 1621 | 1621 |
include/configs/smarcfimx6.h
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. | 2 | * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. |
| 3 | * | 3 | * |
| 4 | * Configuration settings for the Freescale i.MX6Q SabreSD board. | 4 | * Configuration settings for the Freescale i.MX6Q SabreSD board. |
| 5 | * | 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ | 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | #ifndef __SMARCFIMX6_CONFIG_H | 9 | #ifndef __SMARCFIMX6_CONFIG_H |
| 10 | #define __SMARCFIMX6_CONFIG_H | 10 | #define __SMARCFIMX6_CONFIG_H |
| 11 | 11 | ||
| 12 | #include <asm/arch/imx-regs.h> | 12 | #include <asm/arch/imx-regs.h> |
| 13 | #include <asm/imx-common/gpio.h> | 13 | #include <asm/imx-common/gpio.h> |
| 14 | 14 | ||
| 15 | #ifdef CONFIG_SPL | 15 | #ifdef CONFIG_SPL |
| 16 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | 16 | #define CONFIG_SPL_LIBCOMMON_SUPPORT |
| 17 | #define CONFIG_SPL_MMC_SUPPORT | 17 | #define CONFIG_SPL_MMC_SUPPORT |
| 18 | #include "imx6_spl.h" | 18 | #include "imx6_spl.h" |
| 19 | #endif | 19 | #endif |
| 20 | 20 | ||
| 21 | #define CONFIG_MACH_TYPE_SMARCFIMX6 3990 | 21 | #define CONFIG_MACH_TYPE_SMARCFIMX6 3990 |
| 22 | #define CONFIG_MACH_TYPE MACH_TYPE_SMARCFIMX6 | 22 | #define CONFIG_MACH_TYPE MACH_TYPE_SMARCFIMX6 |
| 23 | #if defined(CONFIG_SER0) | 23 | #if defined(CONFIG_SER0) |
| 24 | #define CONFIG_MXC_UART_BASE UART1_BASE | 24 | #define CONFIG_MXC_UART_BASE UART1_BASE |
| 25 | #define CONFIG_CONSOLE_DEV "ttymxc0" | 25 | #define CONFIG_CONSOLE_DEV "ttymxc0" |
| 26 | #endif | 26 | #endif |
| 27 | #if defined(CONFIG_SER1) | 27 | #if defined(CONFIG_SER1) |
| 28 | #define CONFIG_MXC_UART_BASE UART2_BASE | 28 | #define CONFIG_MXC_UART_BASE UART2_BASE |
| 29 | #define CONFIG_CONSOLE_DEV "ttymxc1" | 29 | #define CONFIG_CONSOLE_DEV "ttymxc1" |
| 30 | #endif | 30 | #endif |
| 31 | #if defined(CONFIG_SER2) | 31 | #if defined(CONFIG_SER2) |
| 32 | #define CONFIG_MXC_UART_BASE UART4_BASE | 32 | #define CONFIG_MXC_UART_BASE UART4_BASE |
| 33 | #define CONFIG_CONSOLE_DEV "ttymxc3" | 33 | #define CONFIG_CONSOLE_DEV "ttymxc3" |
| 34 | #endif | 34 | #endif |
| 35 | #if defined(CONFIG_SER3) | 35 | #if defined(CONFIG_SER3) |
| 36 | #define CONFIG_MXC_UART_BASE UART5_BASE | 36 | #define CONFIG_MXC_UART_BASE UART5_BASE |
| 37 | #define CONFIG_CONSOLE_DEV "ttymxc4" | 37 | #define CONFIG_CONSOLE_DEV "ttymxc4" |
| 38 | #endif | 38 | #endif |
| 39 | #define CONFIG_MMCROOT "/dev/mmcblk2p2" /* SDHC3 */ | 39 | #define CONFIG_MMCROOT "/dev/mmcblk2p2" /* SDHC3 */ |
| 40 | #if defined(CONFIG_MX6QP) | 40 | #if defined(CONFIG_MX6QP) |
| 41 | #define CONFIG_DEFAULT_FDT_FILE "imx6qp-smarcfimx6.dtb" | 41 | #define CONFIG_DEFAULT_FDT_FILE "imx6qp-smarcfimx6.dtb" |
| 42 | #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) | 42 | #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) |
| 43 | #elif defined(CONFIG_MX6Q) | 43 | #elif defined(CONFIG_MX6Q) |
| 44 | #define CONFIG_DEFAULT_FDT_FILE "imx6q-smarcfimx6.dtb" | 44 | #define CONFIG_DEFAULT_FDT_FILE "imx6q-smarcfimx6.dtb" |
| 45 | #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) | 45 | #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) |
| 46 | #elif defined(CONFIG_MX6DL) | 46 | #elif defined(CONFIG_MX6DL) |
| 47 | #define CONFIG_DEFAULT_FDT_FILE "imx6dl-smarcfimx6.dtb" | 47 | #define CONFIG_DEFAULT_FDT_FILE "imx6dl-smarcfimx6.dtb" |
| 48 | #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) | 48 | #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) |
| 49 | #elif defined(CONFIG_MX6SOLO) | 49 | #elif defined(CONFIG_MX6SOLO) |
| 50 | #define CONFIG_DEFAULT_FDT_FILE "imx6dl-smarcfimx6.dtb" | 50 | #define CONFIG_DEFAULT_FDT_FILE "imx6dl-smarcfimx6.dtb" |
| 51 | #define PHYS_SDRAM_SIZE (512u * 1024 * 1024) | 51 | #define PHYS_SDRAM_SIZE (512u * 1024 * 1024) |
| 52 | #endif | 52 | #endif |
| 53 | 53 | ||
| 54 | #include "smarcfimx6_common.h" | 54 | #include "smarcfimx6_common.h" |
| 55 | 55 | ||
| 56 | #define CONFIG_SYS_FSL_USDHC_NUM 3 | 56 | #define CONFIG_SYS_FSL_USDHC_NUM 3 |
| 57 | #define CONFIG_SYS_MMC_ENV_DEV 2 /* SDHC3 */ | 57 | #define CONFIG_SYS_MMC_ENV_DEV 2 /* SDHC3 */ |
| 58 | #define CONFIG_SYS_MMC_ENV_PART 0 /* user partition */ | 58 | #define CONFIG_SYS_MMC_ENV_PART 0 /* user partition */ |
| 59 | 59 | ||
| 60 | #ifdef CONFIG_SYS_USE_SPINOR | 60 | #ifdef CONFIG_SYS_USE_SPINOR |
| 61 | #define CONFIG_SF_DEFAULT_CS 0 | 61 | #define CONFIG_SF_DEFAULT_CS 0 |
| 62 | #endif | 62 | #endif |
| 63 | 63 | ||
| 64 | /* | 64 | /* |
| 65 | * imx6 q/dl/solo pcie would be failed to work properly in kernel, if | 65 | * imx6 q/dl/solo pcie would be failed to work properly in kernel, if |
| 66 | * the pcie module is iniialized/enumerated both in uboot and linux | 66 | * the pcie module is iniialized/enumerated both in uboot and linux |
| 67 | * kernel. | 67 | * kernel. |
| 68 | * rootcause:imx6 q/dl/solo pcie don't have the reset mechanism. | 68 | * rootcause:imx6 q/dl/solo pcie don't have the reset mechanism. |
| 69 | * it is only be RESET by the POR. So, the pcie module only be | 69 | * it is only be RESET by the POR. So, the pcie module only be |
| 70 | * initialized/enumerated once in one POR. | 70 | * initialized/enumerated once in one POR. |
| 71 | * Set to use pcie in kernel defaultly, mask the pcie config here. | 71 | * Set to use pcie in kernel defaultly, mask the pcie config here. |
| 72 | * Remove the mask freely, if the uboot pcie functions, rather than | 72 | * Remove the mask freely, if the uboot pcie functions, rather than |
| 73 | * the kernel's, are required. | 73 | * the kernel's, are required. |
| 74 | */ | 74 | */ |
| 75 | /* #define CONFIG_CMD_PCI */ | 75 | /* #define CONFIG_CMD_PCI */ |
| 76 | #ifdef CONFIG_CMD_PCI | 76 | #ifdef CONFIG_CMD_PCI |
| 77 | #define CONFIG_PCI | 77 | #define CONFIG_PCI |
| 78 | #define CONFIG_PCI_PNP | 78 | #define CONFIG_PCI_PNP |
| 79 | #define CONFIG_PCI_SCAN_SHOW | 79 | #define CONFIG_PCI_SCAN_SHOW |
| 80 | #define CONFIG_PCIE_IMX | 80 | #define CONFIG_PCIE_IMX |
| 81 | #endif | 81 | #endif |
| 82 | 82 | ||
| 83 | /* PWM Configs */ | 83 | /* PWM Configs */ |
| 84 | #define CONFIG_PWM_IMX | 84 | #define CONFIG_PWM_IMX |
| 85 | #define CONFIG_IMX6_PWM_PER_CLK 66000000 | 85 | #define CONFIG_IMX6_PWM_PER_CLK 66000000 |
| 86 | 86 | ||
| 87 | /* USB Configs */ | 87 | /* USB Configs */ |
| 88 | #define CONFIG_CMD_USB | 88 | #define CONFIG_CMD_USB |
| 89 | #ifdef CONFIG_CMD_USB | 89 | #ifdef CONFIG_CMD_USB |
| 90 | #define CONFIG_USB_EHCI | 90 | #define CONFIG_USB_EHCI |
| 91 | #define CONFIG_USB_EHCI_MX6 | 91 | #define CONFIG_USB_EHCI_MX6 |
| 92 | #define CONFIG_USB_STORAGE | 92 | #define CONFIG_USB_STORAGE |
| 93 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | 93 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| 94 | #define CONFIG_USB_HOST_ETHER | 94 | #define CONFIG_USB_HOST_ETHER |
| 95 | #define CONFIG_USB_ETHER_ASIX | 95 | #define CONFIG_USB_ETHER_ASIX |
| 96 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) | 96 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
| 97 | #define CONFIG_MXC_USB_FLAGS 0 | 97 | #define CONFIG_MXC_USB_FLAGS 0 |
| 98 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ | 98 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ |
| 99 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ | 99 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ |
| 100 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) | 100 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
| 101 | #define CONFIG_USB_KEYBOARD | 101 | #define CONFIG_USB_KEYBOARD |
| 102 | #ifdef CONFIG_USB_KEYBOARD | 102 | #ifdef CONFIG_USB_KEYBOARD |
| 103 | #define CONFIG_SYS_USB_EVENT_POLL | 103 | #define CONFIG_SYS_USB_EVENT_POLL |
| 104 | #endif /* CONFIG_USB_KEYBOARD */ | 104 | #endif /* CONFIG_USB_KEYBOARD */ |
| 105 | /* Client */ | 105 | /* Client */ |
| 106 | #define CONFIG_USB_GADGET | 106 | #define CONFIG_USB_GADGET |
| 107 | #define CONFIG_USB_GADGET_VBUS_DRAW 2 | 107 | #define CONFIG_USB_GADGET_VBUS_DRAW 2 |
| 108 | #define CONFIG_CI_UDC | 108 | #define CONFIG_CI_UDC |
| 109 | #define CONFIG_USBD_HS | 109 | #define CONFIG_USBD_HS |
| 110 | #define CONFIG_USB_GADGET_DUALSPEED | 110 | #define CONFIG_USB_GADGET_DUALSPEED |
| 111 | 111 | ||
| 112 | #define CONFIG_CMD_USB_MASS_STORAGE | 112 | #define CONFIG_CMD_USB_MASS_STORAGE |
| 113 | #define CONFIG_USB_GADGET_MASS_STORAGE | 113 | #define CONFIG_USB_GADGET_MASS_STORAGE |
| 114 | #define CONFIG_USBDOWNLOAD_GADGET | 114 | #define CONFIG_USBDOWNLOAD_GADGET |
| 115 | #define CONFIG_EMB_VID 0x1B67 | 115 | #define CONFIG_G_DNL_VENDOR_NUM 0x18d1 |
| 116 | #define CONFIG_EMB_PID_SMARCFIMX6 0x0027 | 116 | #define CONFIG_G_DNL_PRODUCT_NUM 0x0d02 |
| 117 | #define CONFIG_G_DNL_MANUFACTURER "Embedian" | 117 | #define CONFIG_G_DNL_MANUFACTURER "FSL" |
| 118 | #define CONFIG_G_DNL_VENDOR_NUM CONFIG_EMB_VID | ||
| 119 | #define CONFIG_G_DNL_PRODUCT_NUM CONFIG_EMB_PID_SMARCFIMX6 | ||
| 120 | /* USB DFU */ | 118 | /* USB DFU */ |
| 121 | #define CONFIG_CMD_DFU | 119 | #define CONFIG_CMD_DFU |
| 122 | #define CONFIG_DFU_FUNCTION | 120 | #define CONFIG_DFU_FUNCTION |
| 123 | #define CONFIG_DFU_MMC | 121 | #define CONFIG_DFU_MMC |
| 124 | #endif | 122 | #endif |
| 125 | 123 | ||
| 126 | /*#define CONFIG_SPLASH_SCREEN*/ | 124 | /*#define CONFIG_SPLASH_SCREEN*/ |
| 127 | /*#define CONFIG_MXC_EPDC*/ | 125 | /*#define CONFIG_MXC_EPDC*/ |
| 128 | 126 | ||
| 129 | /* | 127 | /* |
| 130 | * SPLASH SCREEN Configs | 128 | * SPLASH SCREEN Configs |
| 131 | */ | 129 | */ |
| 132 | #if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MXC_EPDC) | 130 | #if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MXC_EPDC) |
| 133 | /* | 131 | /* |
| 134 | * Framebuffer and LCD | 132 | * Framebuffer and LCD |
| 135 | */ | 133 | */ |
| 136 | #define CONFIG_CMD_BMP | 134 | #define CONFIG_CMD_BMP |
| 137 | #define CONFIG_LCD | 135 | #define CONFIG_LCD |
| 138 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | 136 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
| 139 | #undef LCD_TEST_PATTERN | 137 | #undef LCD_TEST_PATTERN |
| 140 | /* #define CONFIG_SPLASH_IS_IN_MMC 1 */ | 138 | /* #define CONFIG_SPLASH_IS_IN_MMC 1 */ |
| 141 | #define LCD_BPP LCD_MONOCHROME | 139 | #define LCD_BPP LCD_MONOCHROME |
| 142 | /* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ | 140 | /* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ |
| 143 | 141 | ||
| 144 | #define CONFIG_WAVEFORM_BUF_SIZE 0x200000 | 142 | #define CONFIG_WAVEFORM_BUF_SIZE 0x200000 |
| 145 | #endif /* CONFIG_SPLASH_SCREEN && CONFIG_MXC_EPDC */ | 143 | #endif /* CONFIG_SPLASH_SCREEN && CONFIG_MXC_EPDC */ |
| 146 | 144 | ||
| 147 | #endif /* __SMARCFIMX6_CONFIG_H */ | 145 | #endif /* __SMARCFIMX6_CONFIG_H */ |
| 148 | 146 |