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Commit e570aca9474bb707cd2cab0c5c9b8aba957ae51e

Authored by Albert ARIBAUD
1 parent af5b9b1f78
Exists in master and in 50 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

mx1ads: remove board support 

Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Acked-by: Stefano Babic <sbabic@denx.de>

Showing 7 changed files with 1 additions and 733 deletions Side-by-side Diff

board/mx1ads/Makefile
View file @ e570aca
1   -#
2   -# board/mx1ads/Makefile
3   -#
4   -# (C) Copyright 2006
5   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6   -#
7   -# (c) Copyright 2004
8   -# Techware Information Technology, Inc.
9   -# http://www.techware.com.tw/
10   -#
11   -# Ming-Len Wu <minglen_wu@techware.com.tw>
12   -#
13   -# SPDX-License-Identifier: GPL-2.0+
14   -
15   -obj-y := mx1ads.o syncflash.o
16   -obj-y += lowlevel_init.o
board/mx1ads/lowlevel_init.S
View file @ e570aca
1   -/*
2   - * board/mx1ads/lowlevel_init.S
3   - *
4   - * (c) Copyright 2004
5   - * Techware Information Technology, Inc.
6   - * http://www.techware.com.tw/
7   - *
8   - * Ming-Len Wu <minglen_wu@techware.com.tw>
9   - *
10   - * SPDX-License-Identifier: GPL-2.0+
11   - */
12   -
13   -#include <config.h>
14   -#include <version.h>
15   -
16   -#define SDCTL0 0x221000
17   -#define SDCTL1 0x221004
18   -
19   -
20   -_TEXT_BASE:
21   - .word CONFIG_SYS_TEXT_BASE
22   -
23   -.globl lowlevel_init
24   -lowlevel_init:
25   -/* memory controller init */
26   -
27   - ldr r1, =SDCTL0
28   -
29   -/* Set Precharge Command */
30   -
31   - ldr r3, =0x92120200
32   -/* ldr r3, =0x92120251
33   -*/
34   - str r3, [r1]
35   -
36   -/* Issue Precharge All Commad */
37   - ldr r3, =0x8200000
38   - ldr r2, [r3]
39   -
40   -/* Set AutoRefresh Command */
41   - ldr r3, =0xA2120200
42   - str r3, [r1]
43   -
44   -/* Issue AutoRefresh Command */
45   - ldr r3, =0x8000000
46   - ldr r2, [r3]
47   - ldr r2, [r3]
48   - ldr r2, [r3]
49   - ldr r2, [r3]
50   - ldr r2, [r3]
51   - ldr r2, [r3]
52   - ldr r2, [r3]
53   - ldr r2, [r3]
54   -
55   -/* Set Mode Register */
56   - ldr r3, =0xB2120200
57   - str r3, [r1]
58   -
59   -/* Issue Mode Register Command */
60   - ldr r3, =0x08111800 /* Mode Register Value */
61   - ldr r2, [r3]
62   -
63   -/* Set Normal Mode */
64   - ldr r3, =0x82124200
65   - str r3, [r1]
66   -
67   -/* everything is fine now */
68   - mov pc, lr
board/mx1ads/mx1ads.c
View file @ e570aca
1   -/*
2   - * board/mx1ads/mx1ads.c
3   - *
4   - * (c) Copyright 2004
5   - * Techware Information Technology, Inc.
6   - * http://www.techware.com.tw/
7   - *
8   - * Ming-Len Wu <minglen_wu@techware.com.tw>
9   - *
10   - * SPDX-License-Identifier: GPL-2.0+
11   - */
12   -
13   -#include <common.h>
14   -#include <netdev.h>
15   -/*#include <mc9328.h>*/
16   -#include <asm/arch/imx-regs.h>
17   -#include <asm/io.h>
18   -
19   -DECLARE_GLOBAL_DATA_PTR;
20   -
21   -#define FCLK_SPEED 1
22   -
23   -#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
24   -#define M_MDIV 0xC3
25   -#define M_PDIV 0x4
26   -#define M_SDIV 0x1
27   -#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
28   -#define M_MDIV 0xA1
29   -#define M_PDIV 0x3
30   -#define M_SDIV 0x1
31   -#endif
32   -
33   -#define USB_CLOCK 1
34   -
35   -#if USB_CLOCK==0
36   -#define U_M_MDIV 0xA1
37   -#define U_M_PDIV 0x3
38   -#define U_M_SDIV 0x1
39   -#elif USB_CLOCK==1
40   -#define U_M_MDIV 0x48
41   -#define U_M_PDIV 0x3
42   -#define U_M_SDIV 0x2
43   -#endif
44   -
45   -#if 0
46   -
47   -static inline void delay (unsigned long loops)
48   -{
49   - __asm__ volatile ("1:\n"
50   - "subs %0, %1, #1\n"
51   - "bne 1b":"=r" (loops):"0" (loops));
52   -}
53   -
54   -#endif
55   -
56   -/*
57   - * Miscellaneous platform dependent initialisations
58   - */
59   -
60   -void SetAsynchMode (void)
61   -{
62   - __asm__ ("mrc p15,0,r0,c1,c0,0 \n"
63   - "mov r2, #0xC0000000 \n"
64   - "orr r0,r2,r0 \n" "mcr p15,0,r0,c1,c0,0 \n");
65   -}
66   -
67   -static u32 mc9328sid;
68   -
69   -int board_early_init_f(void)
70   -{
71   - mc9328sid = SIDR;
72   -
73   - GPCR = 0x000003AB; /* I/O pad driving strength */
74   -
75   - /* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */
76   -/* MX1_CS1L = 0x11110601; */
77   -
78   - MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
79   -
80   -/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
81   - * BCLK divider to 2 (i.e. BCLK to 48 MHz)
82   - */
83   - CSCR = 0xAF000403;
84   -
85   - CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */
86   - CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
87   -
88   -/* setup cs4 for cs8900 ethernet */
89   -
90   - CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */
91   - CS4L = 0x00001501;
92   -
93   - GIUS (0) &= 0xFF3FFFFF;
94   - GPR (0) &= 0xFF3FFFFF;
95   -
96   - readl(0x1500000C);
97   - readl(0x1500000C);
98   -
99   - SetAsynchMode ();
100   -
101   - icache_enable ();
102   - dcache_enable ();
103   -
104   -/* set PERCLKs */
105   - PCDR = 0x00000055; /* set PERCLKS */
106   -
107   -/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
108   - * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
109   - * all sources selected as normal interrupt
110   - */
111   -
112   -/* MX1_INTTYPEH = 0;
113   - MX1_INTTYPEL = 0;
114   -*/
115   - return 0;
116   -}
117   -
118   -int board_init(void)
119   -{
120   - gd->bd->bi_arch_number = MACH_TYPE_MX1ADS;
121   -
122   - gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */
123   -
124   - return 0;
125   -}
126   -
127   -int board_late_init (void)
128   -{
129   -
130   - setenv ("stdout", "serial");
131   - setenv ("stderr", "serial");
132   -
133   - switch (mc9328sid) {
134   - case 0x0005901d:
135   - printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",
136   - mc9328sid);
137   - break;
138   - case 0x04d4c01d:
139   - printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",
140   - mc9328sid);
141   - break;
142   - case 0x00d4c01d:
143   - printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",
144   - mc9328sid);
145   - break;
146   -
147   - default:
148   - printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",
149   - mc9328sid);
150   - break;
151   - }
152   - return 0;
153   -}
154   -
155   -int dram_init(void)
156   -{
157   - /* dram_init must store complete ramsize in gd->ram_size */
158   - gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
159   - PHYS_SDRAM_1_SIZE);
160   - return 0;
161   -}
162   -
163   -void dram_init_banksize(void)
164   -{
165   - gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
166   - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
167   -}
168   -
169   -#ifdef CONFIG_CMD_NET
170   -int board_eth_init(bd_t *bis)
171   -{
172   - int rc = 0;
173   -#ifdef CONFIG_CS8900
174   - rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
175   -#endif
176   - return rc;
177   -}
178   -#endif
board/mx1ads/syncflash.c
View file @ e570aca
1   -/*
2   - * board/mx1ads/syncflash.c
3   - *
4   - * (c) Copyright 2004
5   - * Techware Information Technology, Inc.
6   - * http://www.techware.com.tw/
7   - *
8   - * Ming-Len Wu <minglen_wu@techware.com.tw>
9   - *
10   - * SPDX-License-Identifier: GPL-2.0+
11   - */
12   -
13   -#include <common.h>
14   -/*#include <mc9328.h>*/
15   -#include <asm/arch/imx-regs.h>
16   -
17   -typedef unsigned long * p_u32;
18   -
19   -/* 4Mx16x2 IAM=0 CSD1 */
20   -
21   -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
22   -
23   -/* Following Setting is for CSD1 */
24   -#define SFCTL 0x00221004
25   -#define reg_SFCTL __REG(SFCTL)
26   -
27   -#define SYNCFLASH_A10 (0x00100000)
28   -
29   -#define CMD_NORMAL (0x81020300) /* Normal Mode */
30   -#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */
31   -#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */
32   -#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */
33   -#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */
34   -#define CMD_PROGRAM (CMD_NORMAL + 0x70000000)
35   -
36   -#define MODE_REG_VAL (CONFIG_SYS_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */
37   -
38   -/* LCR Command */
39   -#define LCR_READSTATUS (0x0001C000) /* 0x70 */
40   -#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */
41   -#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */
42   -#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */
43   -#define LCR_SR_CLEAR (0x00014000) /* 0x50 */
44   -
45   -/* Get Status register */
46   -u32 SF_SR(void) {
47   - u32 tmp;
48   -
49   - reg_SFCTL = CMD_PROGRAM;
50   - tmp = __REG(CONFIG_SYS_FLASH_BASE);
51   -
52   - reg_SFCTL = CMD_NORMAL;
53   -
54   - reg_SFCTL = CMD_LCR; /* Activate LCR Mode */
55   - __REG(CONFIG_SYS_FLASH_BASE + LCR_SR_CLEAR);
56   -
57   - return tmp;
58   -}
59   -
60   -/* check if SyncFlash is ready */
61   -u8 SF_Ready(void) {
62   - u32 tmp;
63   -
64   - tmp = SF_SR();
65   -
66   - if ((tmp & 0x00800000) && (tmp & 0x001C0000)) {
67   - printf ("SyncFlash Error code %08x\n",tmp);
68   - };
69   -
70   - if ((tmp & 0x00000080) && (tmp & 0x0000001C)) {
71   - printf ("SyncFlash Error code %08x\n",tmp);
72   - };
73   -
74   - if (tmp == 0x00800080) /* Test Bit 7 of SR */
75   - return 1;
76   - else
77   - return 0;
78   -}
79   -
80   -/* Issue the precharge all command */
81   -void SF_PrechargeAll(void) {
82   -
83   - /* Set Precharge Command */
84   - reg_SFCTL = CMD_PREC;
85   - /* Issue Precharge All Command */
86   - __REG(CONFIG_SYS_FLASH_BASE + SYNCFLASH_A10);
87   -}
88   -
89   -/* set SyncFlash to normal mode */
90   -void SF_Normal(void) {
91   -
92   - SF_PrechargeAll();
93   -
94   - reg_SFCTL = CMD_NORMAL;
95   -}
96   -
97   -/* Erase SyncFlash */
98   -void SF_Erase(u32 RowAddress) {
99   -
100   - reg_SFCTL = CMD_NORMAL;
101   - __REG(RowAddress);
102   -
103   - reg_SFCTL = CMD_PREC;
104   - __REG(RowAddress);
105   -
106   - reg_SFCTL = CMD_LCR; /* Set LCR mode */
107   - __REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */
108   -
109   - reg_SFCTL = CMD_NORMAL; /* return to Normal mode */
110   - __REG(RowAddress) = 0xD0D0D0D0; /* Confirm */
111   -
112   - while(!SF_Ready());
113   -}
114   -
115   -void SF_NvmodeErase(void) {
116   - SF_PrechargeAll();
117   -
118   - reg_SFCTL = CMD_LCR; /* Set to LCR mode */
119   - __REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */
120   -
121   - reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
122   - __REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */
123   -
124   - while(!SF_Ready());
125   -}
126   -
127   -void SF_NvmodeWrite(void) {
128   - SF_PrechargeAll();
129   -
130   - reg_SFCTL = CMD_LCR; /* Set to LCR mode */
131   - __REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */
132   -
133   - reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
134   - __REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */
135   -}
136   -
137   -/****************************************************************************************/
138   -
139   -ulong flash_init(void) {
140   - int i, j;
141   -
142   -/* Turn on CSD1 for negating RESETSF of SyncFLash */
143   -
144   - reg_SFCTL |= 0x80000000; /* enable CSD1 for SyncFlash */
145   - udelay(200);
146   -
147   - reg_SFCTL = CMD_LMR; /* Set Load Mode Register Command */
148   - __REG(MODE_REG_VAL); /* Issue Load Mode Register Command */
149   -
150   - SF_Normal();
151   -
152   - i = 0;
153   -
154   - flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC;
155   -
156   - flash_info[i].size = FLASH_BANK_SIZE;
157   - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
158   -
159   - memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
160   -
161   - for (j = 0; j < flash_info[i].sector_count; j++) {
162   - flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + j * 0x00100000;
163   - }
164   -
165   - flash_protect(FLAG_PROTECT_SET,
166   - CONFIG_SYS_FLASH_BASE,
167   - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
168   - &flash_info[0]);
169   -
170   - flash_protect(FLAG_PROTECT_SET,
171   - CONFIG_ENV_ADDR,
172   - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
173   - &flash_info[0]);
174   -
175   - return FLASH_BANK_SIZE;
176   -}
177   -
178   -void flash_print_info (flash_info_t *info) {
179   -
180   - int i;
181   -
182   - switch (info->flash_id & FLASH_VENDMASK) {
183   - case (FLASH_MAN_MT & FLASH_VENDMASK):
184   - printf("Micron: ");
185   - break;
186   - default:
187   - printf("Unknown Vendor ");
188   - break;
189   - }
190   -
191   - switch (info->flash_id & FLASH_TYPEMASK) {
192   - case (FLASH_MT28S4M16LC & FLASH_TYPEMASK):
193   - printf("2x FLASH_MT28S4M16LC (16MB Total)\n");
194   - break;
195   - default:
196   - printf("Unknown Chip Type\n");
197   - return;
198   - break;
199   - }
200   -
201   - printf(" Size: %ld MB in %d Sectors\n",
202   - info->size >> 20, info->sector_count);
203   -
204   - printf(" Sector Start Addresses: ");
205   -
206   - for (i = 0; i < info->sector_count; i++) {
207   - if ((i % 5) == 0)
208   - printf ("\n ");
209   -
210   - printf (" %08lX%s", info->start[i],
211   - info->protect[i] ? " (RO)" : " ");
212   - }
213   -
214   - printf ("\n");
215   -}
216   -
217   -/*-----------------------------------------------------------------------*/
218   -
219   -int flash_erase (flash_info_t *info, int s_first, int s_last) {
220   - int iflag, cflag, prot, sect;
221   - int rc = ERR_OK;
222   -
223   -/* first look for protection bits */
224   -
225   - if (info->flash_id == FLASH_UNKNOWN)
226   - return ERR_UNKNOWN_FLASH_TYPE;
227   -
228   - if ((s_first < 0) || (s_first > s_last))
229   - return ERR_INVAL;
230   -
231   - if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK))
232   - return ERR_UNKNOWN_FLASH_VENDOR;
233   -
234   - prot = 0;
235   -
236   - for (sect = s_first; sect <= s_last; ++sect) {
237   - if (info->protect[sect])
238   - prot++;
239   - }
240   -
241   - if (prot) {
242   - printf("protected!\n");
243   - return ERR_PROTECTED;
244   - }
245   -/*
246   - * Disable interrupts which might cause a timeout
247   - * here. Remember that our exception vectors are
248   - * at address 0 in the flash, and we don't want a
249   - * (ticker) exception to happen while the flash
250   - * chip is in programming mode.
251   - */
252   -
253   - cflag = icache_status();
254   - icache_disable();
255   - iflag = disable_interrupts();
256   -
257   -/* Start erase on unprotected sectors */
258   - for (sect = s_first; sect <= s_last && !ctrlc(); sect++) {
259   -
260   - printf("Erasing sector %2d ... ", sect);
261   -
262   -/* arm simple, non interrupt dependent timer */
263   -
264   - get_timer(0);
265   -
266   - SF_NvmodeErase();
267   - SF_NvmodeWrite();
268   -
269   - SF_Erase(CONFIG_SYS_FLASH_BASE + (0x0100000 * sect));
270   - SF_Normal();
271   -
272   - printf("ok.\n");
273   - }
274   -
275   - if (ctrlc())
276   - printf("User Interrupt!\n");
277   -
278   - if (iflag)
279   - enable_interrupts();
280   -
281   - if (cflag)
282   - icache_enable();
283   -
284   - return rc;
285   -}
286   -
287   -/*-----------------------------------------------------------------------
288   - * Copy memory to flash.
289   - */
290   -
291   -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
292   - int i;
293   -
294   - for(i = 0; i < cnt; i += 4) {
295   -
296   - SF_PrechargeAll();
297   -
298   - reg_SFCTL = CMD_PROGRAM; /* Enter SyncFlash Program mode */
299   - __REG(addr + i) = __REG((u32)src + i);
300   -
301   - while(!SF_Ready());
302   - }
303   -
304   - SF_Normal();
305   -
306   - return ERR_OK;
307   -}
... ... @@ -65,7 +65,6 @@
65 65 Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2_ram eb_cpux9k2:RAMBOOT Jens Scharsig <esw@bus-elektronik.de>
66 66 Active arm arm920t at91 eukrea cpuat91 cpuat91 cpuat91 Eric Benard <eric@eukrea.com>
67 67 Active arm arm920t at91 eukrea cpuat91 cpuat91_ram cpuat91:RAMBOOT Eric Benard <eric@eukrea.com>
68   -Active arm arm920t imx - - mx1ads - -
69 68 Active arm arm920t imx - - scb9328 - Torsten Koschorrek <koschorrek@synertronixx.de>
70 69 Active arm arm920t ks8695 - - cm4008 - Greg Ungerer <greg.ungerer@opengear.com>
71 70 Active arm arm920t ks8695 - - cm41xx - -
doc/README.scrapyard
Diff comments   View file @ e570aca
... ... @@ -11,6 +11,7 @@
11 11  
12 12 Board Arch CPU Commit Removed Last known maintainer/contact
13 13 =================================================================================================
  14 +mx1ads arm arm920t - 2014-01-13
14 15 mini2440 arm arm920t - 2014-01-13 Gabriel Huau <contact@huau-gabriel.fr>
15 16 omap730p2 arm arm926ejs 79c5c08d 2013-11-11
16 17 pn62 powerpc mpc824x 649acfe1 2013-11-11 Wolfgang Grandegger <wg@grandegger.com>
include/configs/mx1ads.h
View file @ e570aca
1   -/*
2   - * include/configs/mx1ads.h
3   - *
4   - * (c) Copyright 2004
5   - * Techware Information Technology, Inc.
6   - * http://www.techware.com.tw/
7   - *
8   - * Ming-Len Wu <minglen_wu@techware.com.tw>
9   - *
10   - * This is the Configuration setting for Motorola MX1ADS board
11   - *
12   - * SPDX-License-Identifier: GPL-2.0+
13   - */
14   -
15   -#ifndef __CONFIG_H
16   -#define __CONFIG_H
17   -
18   -/*
19   - * High Level Configuration Options
20   - * (easy to change)
21   - */
22   -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
23   -#define CONFIG_IMX 1 /* It's a Motorola MC9328 SoC */
24   -#define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */
25   -
26   -/*
27   - * Select serial console configuration
28   - */
29   -#define CONFIG_IMX_SERIAL
30   -#define CONFIG_IMX_SERIAL1 /* internal uart 1 */
31   -/* #define _CONFIG_UART2 */ /* internal uart 2 */
32   -/* #define CONFIG_SILENT_CONSOLE */ /* use this to disable output */
33   -
34   -#define CONFIG_BOARD_LATE_INIT
35   -#define USE_920T_MMU 1
36   -
37   -#if 0
38   -#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
39   -#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
40   -#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
41   -#endif
42   -
43   -/*
44   - * Size of malloc() pool
45   - */
46   -
47   -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
48   -
49   -/*
50   - * CS8900 Ethernet drivers
51   - */
52   -#define CONFIG_CS8900 /* we have a CS8900 on-board */
53   -#define CONFIG_CS8900_BASE 0x15000300
54   -#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */
55   -
56   -/*
57   - * select serial console configuration
58   - */
59   -
60   -/* #define CONFIG_UART1 */
61   -/* #define CONFIG_UART2 1 */
62   -
63   -#define CONFIG_BAUDRATE 115200
64   -
65   -/*
66   - * BOOTP options
67   - */
68   -#define CONFIG_BOOTP_BOOTFILESIZE
69   -#define CONFIG_BOOTP_BOOTPATH
70   -#define CONFIG_BOOTP_GATEWAY
71   -#define CONFIG_BOOTP_HOSTNAME
72   -
73   -/*
74   - * Command line configuration.
75   - */
76   -#include <config_cmd_default.h>
77   -
78   -#define CONFIG_CMD_CACHE
79   -#define CONFIG_CMD_REGINFO
80   -#define CONFIG_CMD_ELF
81   -
82   -#define CONFIG_BOOTDELAY 3
83   -#define CONFIG_BOOTARGS "root=/dev/msdk mem=48M"
84   -#define CONFIG_BOOTFILE "mx1ads"
85   -#define CONFIG_BOOTCOMMAND "tftp; bootm"
86   -
87   -#if defined(CONFIG_CMD_KGDB)
88   -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
89   -#endif
90   -
91   -/*
92   - * Miscellaneous configurable options
93   - */
94   -
95   -#define CONFIG_SYS_HUSH_PARSER 1
96   -
97   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
98   -
99   -#ifdef CONFIG_SYS_HUSH_PARSER
100   -#define CONFIG_SYS_PROMPT "MX1ADS$ " /* Monitor Command Prompt */
101   -#else
102   -#define CONFIG_SYS_PROMPT "MX1ADS=> " /* Monitor Command Prompt */
103   -#endif
104   -
105   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
106   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
107   - /* Print Buffer Size */
108   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
109   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
110   -
111   -#define CONFIG_SYS_MEMTEST_START 0x09000000 /* memtest works on */
112   -#define CONFIG_SYS_MEMTEST_END 0x0AF00000 /* 63 MB in DRAM */
113   -
114   -#define CONFIG_SYS_LOAD_ADDR 0x08800000 /* default load address */
115   -#define CONFIG_SYS_HZ 3686400
116   -#define CONFIG_SYS_CPUSPEED 0x141
117   -
118   -/*-----------------------------------------------------------------------
119   - * Physical Memory Map
120   - */
121   -
122   -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
123   -#define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */
124   -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
125   -
126   -#define CONFIG_SYS_TEXT_BASE 0x10000000
127   -
128   -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
129   -#define CONFIG_SYS_INIT_RAM_ADDR 0x00300000
130   -#define CONFIG_SYS_INIT_RAM_SIZE 0x000FFFFF
131   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
132   - GENERATED_GBL_DATA_SIZE)
133   -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
134   - CONFIG_SYS_GBL_DATA_OFFSET)
135   -
136   -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */
137   -#define CONFIG_SYS_FLASH_BASE 0x0C000000 /* SyncFlash on CSD1 */
138   -#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
139   -
140   -/*-----------------------------------------------------------------------
141   - * FLASH and environment organization
142   - */
143   -
144   -#define CONFIG_SYNCFLASH 1
145   -#define PHYS_FLASH_SIZE 0x01000000
146   -#define CONFIG_SYS_MAX_FLASH_SECT (16)
147   -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x00ff8000)
148   -
149   -#define CONFIG_ENV_IS_IN_FLASH 1
150   -#define CONFIG_ENV_SIZE 0x04000 /* Total Size of Environment Sector */
151   -#define CONFIG_ENV_SECT_SIZE 0x100000
152   -
153   -/*-----------------------------------------------------------------------
154   - * Enable passing ATAGS
155   - */
156   -
157   -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
158   -#define CONFIG_SETUP_MEMORY_TAGS 1
159   -
160   -#define CONFIG_SYS_CLK_FREQ 16780000
161   -#define CONFIG_SYSPLL_CLK_FREQ 16000000
162   -
163   -#endif /* __CONFIG_H */