Eric Lee / smarc-uboot

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Commit e7eb8f938734febbbdfce19820df0b469fbef773

Authored by Keerthy
Committed by Lokesh Vutla
1 parent 5f25a3908c
Exists in v2016.05-smarct4x and in 3 other branches v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc

arm: omap: Introduce vcores_update function 

This is needed in case of am57xx where in board detection is done
pretty late in the init sequence. The pmic registers for variants
of am57xx are different hence we need to assign them carefully based
on the board type. Add a function to assign omap_vcores after the
board detection is done.

Fixes: 888ea8611c1 ("ARM: dts: AM572x-IDK Initial Support")
Fixes: 1084ffa86a5 ("ARM: dts: AM571x-IDK Initial Support")
Reported-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>

Showing 3 changed files with 92 additions and 0 deletions Side-by-side Diff

arch/arm/cpu/armv7/omap-common/hwinit-common.c
Diff comments   View file @ e7eb8f9
... ... @@ -112,6 +112,16 @@
112 112 {
113 113 }
114 114  
  115 +/**
  116 + * vcores_update() - Assign omap_vcores based on board
  117 + *
  118 + * Function to pick the vcores based on board. This is expected to be
  119 + * overridden in the SoC family board file where desired.
  120 + */
  121 +void __weak vcores_update(void)
  122 +{
  123 +}
  124 +
115 125 void s_init(void)
116 126 {
117 127 }
... ... @@ -149,6 +159,7 @@
149 159 #endif
150 160 setup_early_clocks();
151 161 do_board_detect();
  162 + vcores_update();
152 163 prcm_init();
153 164 }
154 165  
arch/arm/include/asm/arch-omap5/sys_proto.h
Diff comments   View file @ e7eb8f9
... ... @@ -51,6 +51,7 @@
51 51 void setup_early_clocks(void);
52 52 void prcm_init(void);
53 53 void do_board_detect(void);
  54 +void vcores_update(void);
54 55 void bypass_dpll(u32 const base);
55 56 void freq_update_core(void);
56 57 u32 get_sys_clk_freq(void);
board/ti/am57xx/board.c
Diff comments   View file @ e7eb8f9
... ... @@ -265,6 +265,78 @@
265 265 .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
266 266 };
267 267  
  268 +struct vcores_data am571x_idk_volts = {
  269 + .mpu.value = VDD_MPU_DRA7,
  270 + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
  271 + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  272 + .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  273 + .mpu.pmic = &tps659038,
  274 + .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  275 +
  276 + .eve.value = VDD_EVE_DRA7,
  277 + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
  278 + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  279 + .eve.addr = TPS659038_REG_ADDR_SMPS45,
  280 + .eve.pmic = &tps659038,
  281 + .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  282 +
  283 + .gpu.value = VDD_GPU_DRA7,
  284 + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
  285 + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  286 + .gpu.addr = TPS659038_REG_ADDR_SMPS6,
  287 + .gpu.pmic = &tps659038,
  288 + .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  289 +
  290 + .core.value = VDD_CORE_DRA7,
  291 + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
  292 + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  293 + .core.addr = TPS659038_REG_ADDR_SMPS7,
  294 + .core.pmic = &tps659038,
  295 +
  296 + .iva.value = VDD_IVA_DRA7,
  297 + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
  298 + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  299 + .iva.addr = TPS659038_REG_ADDR_SMPS45,
  300 + .iva.pmic = &tps659038,
  301 + .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  302 +};
  303 +
  304 +struct vcores_data am572x_idk_volts = {
  305 + .mpu.value = VDD_MPU_DRA7,
  306 + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
  307 + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  308 + .mpu.addr = TPS659038_REG_ADDR_SMPS12,
  309 + .mpu.pmic = &tps659038,
  310 + .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
  311 +
  312 + .eve.value = VDD_EVE_DRA7,
  313 + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
  314 + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  315 + .eve.addr = TPS659038_REG_ADDR_SMPS45,
  316 + .eve.pmic = &tps659038,
  317 + .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
  318 +
  319 + .gpu.value = VDD_GPU_DRA7,
  320 + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
  321 + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  322 + .gpu.addr = TPS659038_REG_ADDR_SMPS6,
  323 + .gpu.pmic = &tps659038,
  324 + .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
  325 +
  326 + .core.value = VDD_CORE_DRA7,
  327 + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
  328 + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  329 + .core.addr = TPS659038_REG_ADDR_SMPS7,
  330 + .core.pmic = &tps659038,
  331 +
  332 + .iva.value = VDD_IVA_DRA7,
  333 + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
  334 + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
  335 + .iva.addr = TPS659038_REG_ADDR_SMPS8,
  336 + .iva.pmic = &tps659038,
  337 + .iva.abb_tx_done_mask = OMAP_ABB_IVA_TXDONE_MASK,
  338 +};
  339 +
268 340 #ifdef CONFIG_SPL_BUILD
269 341 /* No env to setup for SPL */
270 342 static inline void setup_board_eeprom_env(void) { }
... ... @@ -341,6 +413,14 @@
341 413 }
342 414  
343 415 #endif /* CONFIG_SPL_BUILD */
  416 +
  417 +void vcores_update(void)
  418 +{
  419 + if (board_is_am572x_idk())
  420 + *omap_vcores = &am572x_idk_volts;
  421 + else if (board_is_am571x_idk())
  422 + *omap_vcores = &am571x_idk_volts;
  423 +}
344 424  
345 425 void hw_data_init(void)
346 426 {