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Commit ea3857230c2d7428e8c22a9d063b4a5b86b34a0c

Authored by Masahiro Yamada
Committed by Tom Rini
1 parent 3d357619a5
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ARM: kirkwood: move SoC headers to mach-kirkwood/include/mach 

Move arch/arm/include/asm/arch-kirkwood/*
  -> arch/arm/mach-kirkwood/include/mach/*

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>

Showing 16 changed files with 762 additions and 763 deletions Side-by-side Diff

... ... @@ -99,7 +99,6 @@
99 99 S: Maintained
100 100 T: git git://git.denx.de/u-boot-marvell.git
101 101 F: arch/arm/mach-kirkwood/
102   -F: arch/arm/include/asm/arch-kirkwood/
103 102  
104 103 ARM MARVELL PXA
105 104 M: Marek Vasut <marex@denx.de>
arch/arm/include/asm/arch-kirkwood/config.h
View file @ ea38572
1   -/*
2   - * (C) Copyright 2011
3   - * Marvell Semiconductor <www.marvell.com>
4   - * Written-by: Lei Wen <leiwen@marvell.com>
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -/*
10   - * This file should be included in board config header file.
11   - *
12   - * It supports common definitions for Kirkwood platform
13   - */
14   -
15   -#ifndef _KW_CONFIG_H
16   -#define _KW_CONFIG_H
17   -
18   -#if defined (CONFIG_KW88F6281)
19   -#include <asm/arch/kw88f6281.h>
20   -#elif defined (CONFIG_KW88F6192)
21   -#include <asm/arch/kw88f6192.h>
22   -#else
23   -#error "SOC Name not defined"
24   -#endif /* CONFIG_KW88F6281 */
25   -
26   -#include <asm/arch/soc.h>
27   -#define CONFIG_SYS_CACHELINE_SIZE 32
28   - /* default Dcache Line length for kirkwood */
29   -#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
30   -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
31   -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
32   -#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
33   -
34   -/*
35   - * By default kwbimage.cfg from board specific folder is used
36   - * If for some board, different configuration file need to be used,
37   - * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
38   - */
39   -#ifndef CONFIG_SYS_KWD_CONFIG
40   -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
41   -#endif /* CONFIG_SYS_KWD_CONFIG */
42   -
43   -/* Kirkwood has 2k of Security SRAM, use it for SP */
44   -#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
45   -#define CONFIG_NR_DRAM_BANKS_MAX 2
46   -
47   -#define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE
48   -#define MV_UART_CONSOLE_BASE KW_UART0_BASE
49   -#define MV_SATA_BASE KW_SATA_BASE
50   -#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
51   -#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET
52   -
53   -/*
54   - * NAND configuration
55   - */
56   -#ifdef CONFIG_CMD_NAND
57   -#define CONFIG_NAND_KIRKWOOD
58   -#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
59   -#define NAND_ALLOW_ERASE_ALL 1
60   -#endif
61   -
62   -/*
63   - * SPI Flash configuration
64   - */
65   -#ifdef CONFIG_CMD_SF
66   -#define CONFIG_HARD_SPI 1
67   -#define CONFIG_KIRKWOOD_SPI 1
68   -#ifndef CONFIG_ENV_SPI_BUS
69   -# define CONFIG_ENV_SPI_BUS 0
70   -#endif
71   -#ifndef CONFIG_ENV_SPI_CS
72   -# define CONFIG_ENV_SPI_CS 0
73   -#endif
74   -#ifndef CONFIG_ENV_SPI_MAX_HZ
75   -# define CONFIG_ENV_SPI_MAX_HZ 50000000
76   -#endif
77   -#endif
78   -
79   -/*
80   - * Ethernet Driver configuration
81   - */
82   -#ifdef CONFIG_CMD_NET
83   -#define CONFIG_CMD_MII
84   -#define CONFIG_NETCONSOLE /* include NetConsole support */
85   -#define CONFIG_MII /* expose smi ove miiphy interface */
86   -#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
87   -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
88   -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
89   -#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
90   -#endif /* CONFIG_CMD_NET */
91   -
92   -/*
93   - * USB/EHCI
94   - */
95   -#ifdef CONFIG_CMD_USB
96   -#define CONFIG_USB_EHCI_MARVELL
97   -#define CONFIG_EHCI_IS_TDI
98   -#endif /* CONFIG_CMD_USB */
99   -
100   -/*
101   - * IDE Support on SATA ports
102   - */
103   -#ifdef CONFIG_CMD_IDE
104   -#define __io
105   -#define CONFIG_CMD_EXT2
106   -#define CONFIG_MVSATA_IDE
107   -#define CONFIG_IDE_PREINIT
108   -#define CONFIG_MVSATA_IDE_USE_PORT1
109   -/* Needs byte-swapping for ATA data register */
110   -#define CONFIG_IDE_SWAP_IO
111   -/* Data, registers and alternate blocks are at the same offset */
112   -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
113   -#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
114   -#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
115   -/* Each 8-bit ATA register is aligned to a 4-bytes address */
116   -#define CONFIG_SYS_ATA_STRIDE 4
117   -/* Controller supports 48-bits LBA addressing */
118   -#define CONFIG_LBA48
119   -/* CONFIG_CMD_IDE requires some #defines for ATA registers */
120   -#define CONFIG_SYS_IDE_MAXBUS 2
121   -#define CONFIG_SYS_IDE_MAXDEVICE 2
122   -/* ATA registers base is at SATA controller base */
123   -#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE
124   -#endif /* CONFIG_CMD_IDE */
125   -
126   -/*
127   - * I2C related stuff
128   - */
129   -#ifdef CONFIG_CMD_I2C
130   -#ifndef CONFIG_SYS_I2C_SOFT
131   -#define CONFIG_SYS_I2C
132   -#define CONFIG_SYS_I2C_MVTWSI
133   -#endif
134   -#define CONFIG_SYS_I2C_SLAVE 0x0
135   -#define CONFIG_SYS_I2C_SPEED 100000
136   -#endif
137   -
138   -#endif /* _KW_CONFIG_H */
arch/arm/include/asm/arch-kirkwood/cpu.h
View file @ ea38572
1   -/*
2   - * (C) Copyright 2009
3   - * Marvell Semiconductor <www.marvell.com>
4   - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#ifndef _KWCPU_H
10   -#define _KWCPU_H
11   -
12   -#include <asm/system.h>
13   -
14   -#ifndef __ASSEMBLY__
15   -
16   -#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
17   - | (attr << 8) | (kw_winctrl_calcsize(size) << 16))
18   -
19   -#define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \
20   - ((_x ? KW_EGIGA1_BASE : KW_EGIGA0_BASE) + 0x44c)
21   -
22   -#define KW_REG_PCIE_DEVID (KW_REG_PCIE_BASE + 0x00)
23   -#define KW_REG_PCIE_REVID (KW_REG_PCIE_BASE + 0x08)
24   -#define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34)
25   -#define KW_REG_SYSRST_CNT (KW_MPP_BASE + 0x50)
26   -#define SYSRST_CNT_1SEC_VAL (25*1000000)
27   -#define KW_REG_MPP_OUT_DRV_REG (KW_MPP_BASE + 0xE0)
28   -
29   -enum memory_bank {
30   - BANK0,
31   - BANK1,
32   - BANK2,
33   - BANK3
34   -};
35   -
36   -enum kwcpu_winen {
37   - KWCPU_WIN_DISABLE,
38   - KWCPU_WIN_ENABLE
39   -};
40   -
41   -enum kwcpu_target {
42   - KWCPU_TARGET_RESERVED,
43   - KWCPU_TARGET_MEMORY,
44   - KWCPU_TARGET_1RESERVED,
45   - KWCPU_TARGET_SASRAM,
46   - KWCPU_TARGET_PCIE
47   -};
48   -
49   -enum kwcpu_attrib {
50   - KWCPU_ATTR_SASRAM = 0x01,
51   - KWCPU_ATTR_DRAM_CS0 = 0x0e,
52   - KWCPU_ATTR_DRAM_CS1 = 0x0d,
53   - KWCPU_ATTR_DRAM_CS2 = 0x0b,
54   - KWCPU_ATTR_DRAM_CS3 = 0x07,
55   - KWCPU_ATTR_NANDFLASH = 0x2f,
56   - KWCPU_ATTR_SPIFLASH = 0x1e,
57   - KWCPU_ATTR_BOOTROM = 0x1d,
58   - KWCPU_ATTR_PCIE_IO = 0xe0,
59   - KWCPU_ATTR_PCIE_MEM = 0xe8
60   -};
61   -
62   -/*
63   - * Default Device Address MAP BAR values
64   - */
65   -#define KW_DEFADR_PCI_MEM 0x90000000
66   -#define KW_DEFADR_PCI_IO 0xC0000000
67   -#define KW_DEFADR_PCI_IO_REMAP 0xC0000000
68   -#define KW_DEFADR_SASRAM 0xC8010000
69   -#define KW_DEFADR_NANDF 0xD8000000
70   -#define KW_DEFADR_SPIF 0xE8000000
71   -#define KW_DEFADR_BOOTROM 0xF8000000
72   -
73   -/*
74   - * read feroceon/sheeva core extra feature register
75   - * using co-proc instruction
76   - */
77   -static inline unsigned int readfr_extra_feature_reg(void)
78   -{
79   - unsigned int val;
80   - asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r"
81   - (val)::"cc");
82   - return val;
83   -}
84   -
85   -/*
86   - * write feroceon/sheeva core extra feature register
87   - * using co-proc instruction
88   - */
89   -static inline void writefr_extra_feature_reg(unsigned int val)
90   -{
91   - asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r"
92   - (val):"cc");
93   - isb();
94   -}
95   -
96   -/*
97   - * MBus-L to Mbus Bridge Registers
98   - * Ref: Datasheet sec:A.3
99   - */
100   -struct kwwin_registers {
101   - u32 ctrl;
102   - u32 base;
103   - u32 remap_lo;
104   - u32 remap_hi;
105   -};
106   -
107   -/*
108   - * CPU control and status Registers
109   - * Ref: Datasheet sec:A.3.2
110   - */
111   -struct kwcpu_registers {
112   - u32 config; /*0x20100 */
113   - u32 ctrl_stat; /*0x20104 */
114   - u32 rstoutn_mask; /* 0x20108 */
115   - u32 sys_soft_rst; /* 0x2010C */
116   - u32 ahb_mbus_cause_irq; /* 0x20110 */
117   - u32 ahb_mbus_mask_irq; /* 0x20114 */
118   - u32 pad1[2];
119   - u32 ftdll_config; /* 0x20120 */
120   - u32 pad2;
121   - u32 l2_cfg; /* 0x20128 */
122   -};
123   -
124   -/*
125   - * GPIO Registers
126   - * Ref: Datasheet sec:A.19
127   - */
128   -struct kwgpio_registers {
129   - u32 dout;
130   - u32 oe;
131   - u32 blink_en;
132   - u32 din_pol;
133   - u32 din;
134   - u32 irq_cause;
135   - u32 irq_mask;
136   - u32 irq_level;
137   -};
138   -
139   -/*
140   - * functions
141   - */
142   -unsigned char get_random_hex(void);
143   -unsigned int mvebu_sdram_bar(enum memory_bank bank);
144   -unsigned int mvebu_sdram_bs(enum memory_bank bank);
145   -void mvebu_sdram_size_adjust(enum memory_bank bank);
146   -int kw_config_adr_windows(void);
147   -void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
148   - unsigned int gpp0_oe, unsigned int gpp1_oe);
149   -int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,
150   - unsigned int mpp16_23, unsigned int mpp24_31,
151   - unsigned int mpp32_39, unsigned int mpp40_47,
152   - unsigned int mpp48_55);
153   -unsigned int kw_winctrl_calcsize(unsigned int sizeval);
154   -#endif /* __ASSEMBLY__ */
155   -#endif /* _KWCPU_H */
arch/arm/include/asm/arch-kirkwood/gpio.h
View file @ ea38572
1   -/*
2   - * arch/asm-arm/mach-kirkwood/include/mach/gpio.h
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -/*
8   - * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
9   - * Removed kernel level irq handling. Took some macros from kernel to
10   - * allow build.
11   - *
12   - * Dieter Kiermaier dk-arm-linux@gmx.de
13   - */
14   -
15   -#ifndef __KIRKWOOD_GPIO_H
16   -#define __KIRKWOOD_GPIO_H
17   -
18   -/* got from kernel include/linux/bitops.h */
19   -#define BITS_PER_BYTE 8
20   -#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
21   -
22   -#define GPIO_MAX 50
23   -#define GPIO_OFF(pin) (((pin) >> 5) ? 0x0040 : 0x0000)
24   -#define GPIO_OUT(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x00)
25   -#define GPIO_IO_CONF(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x04)
26   -#define GPIO_BLINK_EN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x08)
27   -#define GPIO_IN_POL(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x0c)
28   -#define GPIO_DATA_IN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x10)
29   -#define GPIO_EDGE_CAUSE(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x14)
30   -#define GPIO_EDGE_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x18)
31   -#define GPIO_LEVEL_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x1c)
32   -
33   -/*
34   - * Kirkwood-specific GPIO API
35   - */
36   -
37   -void kw_gpio_set_valid(unsigned pin, int mode);
38   -int kw_gpio_is_valid(unsigned pin, int mode);
39   -int kw_gpio_direction_input(unsigned pin);
40   -int kw_gpio_direction_output(unsigned pin, int value);
41   -int kw_gpio_get_value(unsigned pin);
42   -void kw_gpio_set_value(unsigned pin, int value);
43   -void kw_gpio_set_blink(unsigned pin, int blink);
44   -void kw_gpio_set_unused(unsigned pin);
45   -
46   -#define GPIO_INPUT_OK (1 << 0)
47   -#define GPIO_OUTPUT_OK (1 << 1)
48   -
49   -#endif
arch/arm/include/asm/arch-kirkwood/kw88f6192.h
View file @ ea38572
1   -/*
2   - * (C) Copyright 2009
3   - * Marvell Semiconductor <www.marvell.com>
4   - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5   - *
6   - * Header file for Feroceon CPU core 88FR131 Based KW88F6192 SOC.
7   - *
8   - * SPDX-License-Identifier: GPL-2.0+
9   - */
10   -
11   -#ifndef _CONFIG_KW88F6192_H
12   -#define _CONFIG_KW88F6192_H
13   -
14   -/* SOC specific definations */
15   -#define KW88F6192_REGS_PHYS_BASE 0xf1000000
16   -#define KW_REGS_PHY_BASE KW88F6192_REGS_PHYS_BASE
17   -
18   -/* TCLK Core Clock defination */
19   -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
20   -
21   -#endif /* _CONFIG_KW88F6192_H */
arch/arm/include/asm/arch-kirkwood/kw88f6281.h
View file @ ea38572
1   -/*
2   - * (C) Copyright 2009
3   - * Marvell Semiconductor <www.marvell.com>
4   - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5   - *
6   - * Header file for Feroceon CPU core 88FR131 Based KW88F6281 SOC.
7   - *
8   - * SPDX-License-Identifier: GPL-2.0+
9   - */
10   -
11   -#ifndef _ASM_ARCH_KW88F6281_H
12   -#define _ASM_ARCH_KW88F6281_H
13   -
14   -/* SOC specific definitions */
15   -#define KW88F6281_REGS_PHYS_BASE 0xf1000000
16   -#define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE
17   -
18   -/* TCLK Core Clock definition */
19   -#ifndef CONFIG_SYS_TCLK
20   -#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
21   -#endif
22   -
23   -#endif /* _ASM_ARCH_KW88F6281_H */
arch/arm/include/asm/arch-kirkwood/mpp.h
View file @ ea38572
1   -/*
2   - * linux/arch/arm/mach-kirkwood/mpp.h -- Multi Purpose Pins
3   - *
4   - * Copyright 2009: Marvell Technology Group Ltd.
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#ifndef __KIRKWOOD_MPP_H
10   -#define __KIRKWOOD_MPP_H
11   -
12   -#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \
13   - /* MPP number */ ((_num) & 0xff) | \
14   - /* MPP select value */ (((_sel) & 0xf) << 8) | \
15   - /* may be input signal */ ((!!(_in)) << 12) | \
16   - /* may be output signal */ ((!!(_out)) << 13) | \
17   - /* available on F6180 */ ((!!(_F6180)) << 14) | \
18   - /* available on F6190 */ ((!!(_F6190)) << 15) | \
19   - /* available on F6192 */ ((!!(_F6192)) << 16) | \
20   - /* available on F6281 */ ((!!(_F6281)) << 17))
21   -
22   -#define MPP_NUM(x) ((x) & 0xff)
23   -#define MPP_SEL(x) (((x) >> 8) & 0xf)
24   -
25   - /* num sel i o 6180 6190 6192 6281 */
26   -
27   -#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0 )
28   -#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0 )
29   -
30   -#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0 )
31   -#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0 )
32   -#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0 )
33   -#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1 )
34   -
35   -#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1 )
36   -#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1 )
37   -#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1 )
38   -
39   -#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1 )
40   -#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1 )
41   -#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1 )
42   -
43   -#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1 )
44   -#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1 )
45   -#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1 )
46   -
47   -#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1 )
48   -#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1 )
49   -#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1 )
50   -
51   -#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1 )
52   -#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1 )
53   -#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1 )
54   -#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1 )
55   -#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1 )
56   -
57   -#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1 )
58   -#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1 )
59   -#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1 )
60   -#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1 )
61   -#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1 )
62   -
63   -#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1 )
64   -#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1 )
65   -#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1 )
66   -
67   -#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1 )
68   -#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1 )
69   -#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 )
70   -#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 )
71   -
72   -#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 )
73   -#define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 )
74   -#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 )
75   -#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 )
76   -#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1 )
77   -#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1 )
78   -#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1 )
79   -#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1 )
80   -
81   -#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1 )
82   -#define MPP9_TW_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1 )
83   -#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1 )
84   -#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1 )
85   -#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1 )
86   -#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1 )
87   -#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1 )
88   -
89   -#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1 )
90   -#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1 )
91   -#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1 )
92   -#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1 )
93   -#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1 )
94   -
95   -#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1 )
96   -#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1 )
97   -#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1 )
98   -#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1 )
99   -#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1 )
100   -#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1 )
101   -#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1 )
102   -
103   -#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1 )
104   -#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1 )
105   -
106   -#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1 )
107   -#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1 )
108   -#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1 )
109   -
110   -#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1 )
111   -#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1 )
112   -#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1 )
113   -#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1 )
114   -#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1 )
115   -
116   -#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1 )
117   -#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1 )
118   -#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1 )
119   -#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1 )
120   -#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1 )
121   -
122   -#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1 )
123   -#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1 )
124   -#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1 )
125   -#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1 )
126   -#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1 )
127   -#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1 )
128   -
129   -#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1 )
130   -#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1 )
131   -#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1 )
132   -
133   -#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1 )
134   -#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1 )
135   -
136   -#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1 )
137   -#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1 )
138   -
139   -#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1 )
140   -#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1 )
141   -#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1 )
142   -#define MPP20_GE1_0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1 )
143   -#define MPP20_AUDIO_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1 )
144   -#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1 )
145   -
146   -#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1 )
147   -#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1 )
148   -#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1 )
149   -#define MPP21_GE1_1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1 )
150   -#define MPP21_AUDIO_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1 )
151   -#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1 )
152   -
153   -#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1 )
154   -#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1 )
155   -#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1 )
156   -#define MPP22_GE1_2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1 )
157   -#define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1 )
158   -#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1 )
159   -
160   -#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1 )
161   -#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1 )
162   -#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1 )
163   -#define MPP23_GE1_3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1 )
164   -#define MPP23_AUDIO_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1 )
165   -#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1 )
166   -
167   -#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1 )
168   -#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1 )
169   -#define MPP24_TDM_SPI_CS0 DEV( 24, 0x2, 0, 1, 0, 0, 1, 1 )
170   -#define MPP24_GE1_4 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1 )
171   -#define MPP24_AUDIO_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1 )
172   -
173   -#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1 )
174   -#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1 )
175   -#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1 )
176   -#define MPP25_GE1_5 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1 )
177   -#define MPP25_AUDIO_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1 )
178   -
179   -#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1 )
180   -#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1 )
181   -#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1 )
182   -#define MPP26_GE1_6 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1 )
183   -#define MPP26_AUDIO_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1 )
184   -
185   -#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1 )
186   -#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1 )
187   -#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1 )
188   -#define MPP27_GE1_7 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1 )
189   -#define MPP27_AUDIO_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1 )
190   -
191   -#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1 )
192   -#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1 )
193   -#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1 )
194   -#define MPP28_GE1_8 MPP( 28, 0x3, 0, 0, 0, 1, 1, 1 )
195   -#define MPP28_AUDIO_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1 )
196   -
197   -#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1 )
198   -#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1 )
199   -#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1 )
200   -#define MPP29_GE1_9 MPP( 29, 0x3, 0, 0, 0, 1, 1, 1 )
201   -
202   -#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1 )
203   -#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1 )
204   -#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1 )
205   -#define MPP30_GE1_10 MPP( 30, 0x3, 0, 0, 0, 1, 1, 1 )
206   -
207   -#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1 )
208   -#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1 )
209   -#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1 )
210   -#define MPP31_GE1_11 MPP( 31, 0x3, 0, 0, 0, 1, 1, 1 )
211   -
212   -#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1 )
213   -#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1 )
214   -#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1 )
215   -#define MPP32_GE1_12 MPP( 32, 0x3, 0, 0, 0, 1, 1, 1 )
216   -
217   -#define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 )
218   -#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 )
219   -#define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 )
220   -
221   -#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 )
222   -#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 )
223   -#define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 )
224   -
225   -#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 )
226   -#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 )
227   -#define MPP35_GE1_15 MPP( 35, 0x3, 0, 0, 0, 1, 1, 1 )
228   -#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1 )
229   -#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1 )
230   -
231   -#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1 )
232   -#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1 )
233   -#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1 )
234   -#define MPP36_AUDIO_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1 )
235   -
236   -#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1 )
237   -#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1 )
238   -#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1 )
239   -#define MPP37_AUDIO_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1 )
240   -
241   -#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1 )
242   -#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1 )
243   -#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1 )
244   -#define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1 )
245   -
246   -#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1 )
247   -#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1 )
248   -#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1 )
249   -#define MPP39_AUDIO_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1 )
250   -
251   -#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1 )
252   -#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1 )
253   -#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1 )
254   -#define MPP40_AUDIO_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1 )
255   -
256   -#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1 )
257   -#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1 )
258   -#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1 )
259   -#define MPP41_AUDIO_I2SLRC MPP( 41, 0x4, 0, 1, 1, 0, 0, 1 )
260   -
261   -#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1 )
262   -#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1 )
263   -#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1 )
264   -#define MPP42_AUDIO_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1 )
265   -
266   -#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1 )
267   -#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1 )
268   -#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1 )
269   -#define MPP43_AUDIO_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1 )
270   -
271   -#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1 )
272   -#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1 )
273   -#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1 )
274   -#define MPP44_AUDIO_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1 )
275   -
276   -#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1 )
277   -#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1 )
278   -#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1 )
279   -
280   -#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1 )
281   -#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1 )
282   -#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1 )
283   -
284   -#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1 )
285   -#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1 )
286   -#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1 )
287   -
288   -#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1 )
289   -#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1 )
290   -#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1 )
291   -
292   -#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1 )
293   -#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1 )
294   -#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1 )
295   -#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1 )
296   -
297   -#define MPP_MAX 49
298   -
299   -void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save);
300   -
301   -#endif
arch/arm/include/asm/arch-kirkwood/soc.h
View file @ ea38572
1   -/*
2   - * (C) Copyright 2009
3   - * Marvell Semiconductor <www.marvell.com>
4   - * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5   - *
6   - * Header file for the Marvell's Feroceon CPU core.
7   - *
8   - * SPDX-License-Identifier: GPL-2.0+
9   - */
10   -
11   -#ifndef _ASM_ARCH_KIRKWOOD_H
12   -#define _ASM_ARCH_KIRKWOOD_H
13   -
14   -#if defined (CONFIG_FEROCEON_88FR131) || defined (CONFIG_SHEEVA_88SV131)
15   -
16   -/* SOC specific definations */
17   -#define INTREG_BASE 0xd0000000
18   -#define KW_REGISTER(x) (KW_REGS_PHY_BASE + x)
19   -#define KW_OFFSET_REG (INTREG_BASE + 0x20080)
20   -
21   -/* undocumented registers */
22   -#define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470))
23   -#define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478))
24   -
25   -#define MVEBU_SDRAM_BASE (KW_REGISTER(0x1500))
26   -#define KW_TWSI_BASE (KW_REGISTER(0x11000))
27   -#define KW_UART0_BASE (KW_REGISTER(0x12000))
28   -#define KW_UART1_BASE (KW_REGISTER(0x12100))
29   -#define KW_MPP_BASE (KW_REGISTER(0x10000))
30   -#define MVEBU_GPIO0_BASE (KW_REGISTER(0x10100))
31   -#define MVEBU_GPIO1_BASE (KW_REGISTER(0x10140))
32   -#define KW_RTC_BASE (KW_REGISTER(0x10300))
33   -#define KW_NANDF_BASE (KW_REGISTER(0x10418))
34   -#define MVEBU_SPI_BASE (KW_REGISTER(0x10600))
35   -#define KW_CPU_WIN_BASE (KW_REGISTER(0x20000))
36   -#define KW_CPU_REG_BASE (KW_REGISTER(0x20100))
37   -#define MVEBU_TIMER_BASE (KW_REGISTER(0x20300))
38   -#define KW_REG_PCIE_BASE (KW_REGISTER(0x40000))
39   -#define KW_USB20_BASE (KW_REGISTER(0x50000))
40   -#define KW_EGIGA0_BASE (KW_REGISTER(0x72000))
41   -#define KW_EGIGA1_BASE (KW_REGISTER(0x76000))
42   -#define KW_SATA_BASE (KW_REGISTER(0x80000))
43   -#define KW_SDIO_BASE (KW_REGISTER(0x90000))
44   -
45   -/* Kirkwood Sata controller has two ports */
46   -#define KW_SATA_PORT0_OFFSET 0x2000
47   -#define KW_SATA_PORT1_OFFSET 0x4000
48   -
49   -/* Kirkwood GbE controller has two ports */
50   -#define MAX_MVGBE_DEVS 2
51   -#define MVGBE0_BASE KW_EGIGA0_BASE
52   -#define MVGBE1_BASE KW_EGIGA1_BASE
53   -
54   -/* Kirkwood USB Host controller */
55   -#define MVUSB0_BASE KW_USB20_BASE
56   -#define MVUSB0_CPU_ATTR_DRAM_CS0 KWCPU_ATTR_DRAM_CS0
57   -#define MVUSB0_CPU_ATTR_DRAM_CS1 KWCPU_ATTR_DRAM_CS1
58   -#define MVUSB0_CPU_ATTR_DRAM_CS2 KWCPU_ATTR_DRAM_CS2
59   -#define MVUSB0_CPU_ATTR_DRAM_CS3 KWCPU_ATTR_DRAM_CS3
60   -
61   -/* Kirkwood CPU memory windows */
62   -#define MVCPU_WIN_CTRL_DATA KWCPU_WIN_CTRL_DATA
63   -#define MVCPU_WIN_ENABLE KWCPU_WIN_ENABLE
64   -#define MVCPU_WIN_DISABLE KWCPU_WIN_DISABLE
65   -
66   -#if defined (CONFIG_KW88F6281)
67   -#include <asm/arch/kw88f6281.h>
68   -#elif defined (CONFIG_KW88F6192)
69   -#include <asm/arch/kw88f6192.h>
70   -#else
71   -#error "SOC Name not defined"
72   -#endif /* CONFIG_KW88F6281 */
73   -#endif /* CONFIG_FEROCEON_88FR131 */
74   -#endif /* _ASM_ARCH_KIRKWOOD_H */
arch/arm/mach-kirkwood/include/mach/config.h
Diff comments   View file @ ea38572
  1 +/*
  2 + * (C) Copyright 2011
  3 + * Marvell Semiconductor <www.marvell.com>
  4 + * Written-by: Lei Wen <leiwen@marvell.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +/*
  10 + * This file should be included in board config header file.
  11 + *
  12 + * It supports common definitions for Kirkwood platform
  13 + */
  14 +
  15 +#ifndef _KW_CONFIG_H
  16 +#define _KW_CONFIG_H
  17 +
  18 +#if defined (CONFIG_KW88F6281)
  19 +#include <asm/arch/kw88f6281.h>
  20 +#elif defined (CONFIG_KW88F6192)
  21 +#include <asm/arch/kw88f6192.h>
  22 +#else
  23 +#error "SOC Name not defined"
  24 +#endif /* CONFIG_KW88F6281 */
  25 +
  26 +#include <asm/arch/soc.h>
  27 +#define CONFIG_SYS_CACHELINE_SIZE 32
  28 + /* default Dcache Line length for kirkwood */
  29 +#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
  30 +#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
  31 +#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
  32 +#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
  33 +
  34 +/*
  35 + * By default kwbimage.cfg from board specific folder is used
  36 + * If for some board, different configuration file need to be used,
  37 + * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
  38 + */
  39 +#ifndef CONFIG_SYS_KWD_CONFIG
  40 +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
  41 +#endif /* CONFIG_SYS_KWD_CONFIG */
  42 +
  43 +/* Kirkwood has 2k of Security SRAM, use it for SP */
  44 +#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
  45 +#define CONFIG_NR_DRAM_BANKS_MAX 2
  46 +
  47 +#define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE
  48 +#define MV_UART_CONSOLE_BASE KW_UART0_BASE
  49 +#define MV_SATA_BASE KW_SATA_BASE
  50 +#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
  51 +#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET
  52 +
  53 +/*
  54 + * NAND configuration
  55 + */
  56 +#ifdef CONFIG_CMD_NAND
  57 +#define CONFIG_NAND_KIRKWOOD
  58 +#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
  59 +#define NAND_ALLOW_ERASE_ALL 1
  60 +#endif
  61 +
  62 +/*
  63 + * SPI Flash configuration
  64 + */
  65 +#ifdef CONFIG_CMD_SF
  66 +#define CONFIG_HARD_SPI 1
  67 +#define CONFIG_KIRKWOOD_SPI 1
  68 +#ifndef CONFIG_ENV_SPI_BUS
  69 +# define CONFIG_ENV_SPI_BUS 0
  70 +#endif
  71 +#ifndef CONFIG_ENV_SPI_CS
  72 +# define CONFIG_ENV_SPI_CS 0
  73 +#endif
  74 +#ifndef CONFIG_ENV_SPI_MAX_HZ
  75 +# define CONFIG_ENV_SPI_MAX_HZ 50000000
  76 +#endif
  77 +#endif
  78 +
  79 +/*
  80 + * Ethernet Driver configuration
  81 + */
  82 +#ifdef CONFIG_CMD_NET
  83 +#define CONFIG_CMD_MII
  84 +#define CONFIG_NETCONSOLE /* include NetConsole support */
  85 +#define CONFIG_MII /* expose smi ove miiphy interface */
  86 +#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
  87 +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
  88 +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
  89 +#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
  90 +#endif /* CONFIG_CMD_NET */
  91 +
  92 +/*
  93 + * USB/EHCI
  94 + */
  95 +#ifdef CONFIG_CMD_USB
  96 +#define CONFIG_USB_EHCI_MARVELL
  97 +#define CONFIG_EHCI_IS_TDI
  98 +#endif /* CONFIG_CMD_USB */
  99 +
  100 +/*
  101 + * IDE Support on SATA ports
  102 + */
  103 +#ifdef CONFIG_CMD_IDE
  104 +#define __io
  105 +#define CONFIG_CMD_EXT2
  106 +#define CONFIG_MVSATA_IDE
  107 +#define CONFIG_IDE_PREINIT
  108 +#define CONFIG_MVSATA_IDE_USE_PORT1
  109 +/* Needs byte-swapping for ATA data register */
  110 +#define CONFIG_IDE_SWAP_IO
  111 +/* Data, registers and alternate blocks are at the same offset */
  112 +#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
  113 +#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
  114 +#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
  115 +/* Each 8-bit ATA register is aligned to a 4-bytes address */
  116 +#define CONFIG_SYS_ATA_STRIDE 4
  117 +/* Controller supports 48-bits LBA addressing */
  118 +#define CONFIG_LBA48
  119 +/* CONFIG_CMD_IDE requires some #defines for ATA registers */
  120 +#define CONFIG_SYS_IDE_MAXBUS 2
  121 +#define CONFIG_SYS_IDE_MAXDEVICE 2
  122 +/* ATA registers base is at SATA controller base */
  123 +#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE
  124 +#endif /* CONFIG_CMD_IDE */
  125 +
  126 +/*
  127 + * I2C related stuff
  128 + */
  129 +#ifdef CONFIG_CMD_I2C
  130 +#ifndef CONFIG_SYS_I2C_SOFT
  131 +#define CONFIG_SYS_I2C
  132 +#define CONFIG_SYS_I2C_MVTWSI
  133 +#endif
  134 +#define CONFIG_SYS_I2C_SLAVE 0x0
  135 +#define CONFIG_SYS_I2C_SPEED 100000
  136 +#endif
  137 +
  138 +#endif /* _KW_CONFIG_H */
arch/arm/mach-kirkwood/include/mach/cpu.h
Diff comments   View file @ ea38572
  1 +/*
  2 + * (C) Copyright 2009
  3 + * Marvell Semiconductor <www.marvell.com>
  4 + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef _KWCPU_H
  10 +#define _KWCPU_H
  11 +
  12 +#include <asm/system.h>
  13 +
  14 +#ifndef __ASSEMBLY__
  15 +
  16 +#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
  17 + | (attr << 8) | (kw_winctrl_calcsize(size) << 16))
  18 +
  19 +#define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \
  20 + ((_x ? KW_EGIGA1_BASE : KW_EGIGA0_BASE) + 0x44c)
  21 +
  22 +#define KW_REG_PCIE_DEVID (KW_REG_PCIE_BASE + 0x00)
  23 +#define KW_REG_PCIE_REVID (KW_REG_PCIE_BASE + 0x08)
  24 +#define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34)
  25 +#define KW_REG_SYSRST_CNT (KW_MPP_BASE + 0x50)
  26 +#define SYSRST_CNT_1SEC_VAL (25*1000000)
  27 +#define KW_REG_MPP_OUT_DRV_REG (KW_MPP_BASE + 0xE0)
  28 +
  29 +enum memory_bank {
  30 + BANK0,
  31 + BANK1,
  32 + BANK2,
  33 + BANK3
  34 +};
  35 +
  36 +enum kwcpu_winen {
  37 + KWCPU_WIN_DISABLE,
  38 + KWCPU_WIN_ENABLE
  39 +};
  40 +
  41 +enum kwcpu_target {
  42 + KWCPU_TARGET_RESERVED,
  43 + KWCPU_TARGET_MEMORY,
  44 + KWCPU_TARGET_1RESERVED,
  45 + KWCPU_TARGET_SASRAM,
  46 + KWCPU_TARGET_PCIE
  47 +};
  48 +
  49 +enum kwcpu_attrib {
  50 + KWCPU_ATTR_SASRAM = 0x01,
  51 + KWCPU_ATTR_DRAM_CS0 = 0x0e,
  52 + KWCPU_ATTR_DRAM_CS1 = 0x0d,
  53 + KWCPU_ATTR_DRAM_CS2 = 0x0b,
  54 + KWCPU_ATTR_DRAM_CS3 = 0x07,
  55 + KWCPU_ATTR_NANDFLASH = 0x2f,
  56 + KWCPU_ATTR_SPIFLASH = 0x1e,
  57 + KWCPU_ATTR_BOOTROM = 0x1d,
  58 + KWCPU_ATTR_PCIE_IO = 0xe0,
  59 + KWCPU_ATTR_PCIE_MEM = 0xe8
  60 +};
  61 +
  62 +/*
  63 + * Default Device Address MAP BAR values
  64 + */
  65 +#define KW_DEFADR_PCI_MEM 0x90000000
  66 +#define KW_DEFADR_PCI_IO 0xC0000000
  67 +#define KW_DEFADR_PCI_IO_REMAP 0xC0000000
  68 +#define KW_DEFADR_SASRAM 0xC8010000
  69 +#define KW_DEFADR_NANDF 0xD8000000
  70 +#define KW_DEFADR_SPIF 0xE8000000
  71 +#define KW_DEFADR_BOOTROM 0xF8000000
  72 +
  73 +/*
  74 + * read feroceon/sheeva core extra feature register
  75 + * using co-proc instruction
  76 + */
  77 +static inline unsigned int readfr_extra_feature_reg(void)
  78 +{
  79 + unsigned int val;
  80 + asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r"
  81 + (val)::"cc");
  82 + return val;
  83 +}
  84 +
  85 +/*
  86 + * write feroceon/sheeva core extra feature register
  87 + * using co-proc instruction
  88 + */
  89 +static inline void writefr_extra_feature_reg(unsigned int val)
  90 +{
  91 + asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r"
  92 + (val):"cc");
  93 + isb();
  94 +}
  95 +
  96 +/*
  97 + * MBus-L to Mbus Bridge Registers
  98 + * Ref: Datasheet sec:A.3
  99 + */
  100 +struct kwwin_registers {
  101 + u32 ctrl;
  102 + u32 base;
  103 + u32 remap_lo;
  104 + u32 remap_hi;
  105 +};
  106 +
  107 +/*
  108 + * CPU control and status Registers
  109 + * Ref: Datasheet sec:A.3.2
  110 + */
  111 +struct kwcpu_registers {
  112 + u32 config; /*0x20100 */
  113 + u32 ctrl_stat; /*0x20104 */
  114 + u32 rstoutn_mask; /* 0x20108 */
  115 + u32 sys_soft_rst; /* 0x2010C */
  116 + u32 ahb_mbus_cause_irq; /* 0x20110 */
  117 + u32 ahb_mbus_mask_irq; /* 0x20114 */
  118 + u32 pad1[2];
  119 + u32 ftdll_config; /* 0x20120 */
  120 + u32 pad2;
  121 + u32 l2_cfg; /* 0x20128 */
  122 +};
  123 +
  124 +/*
  125 + * GPIO Registers
  126 + * Ref: Datasheet sec:A.19
  127 + */
  128 +struct kwgpio_registers {
  129 + u32 dout;
  130 + u32 oe;
  131 + u32 blink_en;
  132 + u32 din_pol;
  133 + u32 din;
  134 + u32 irq_cause;
  135 + u32 irq_mask;
  136 + u32 irq_level;
  137 +};
  138 +
  139 +/*
  140 + * functions
  141 + */
  142 +unsigned char get_random_hex(void);
  143 +unsigned int mvebu_sdram_bar(enum memory_bank bank);
  144 +unsigned int mvebu_sdram_bs(enum memory_bank bank);
  145 +void mvebu_sdram_size_adjust(enum memory_bank bank);
  146 +int kw_config_adr_windows(void);
  147 +void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
  148 + unsigned int gpp0_oe, unsigned int gpp1_oe);
  149 +int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,
  150 + unsigned int mpp16_23, unsigned int mpp24_31,
  151 + unsigned int mpp32_39, unsigned int mpp40_47,
  152 + unsigned int mpp48_55);
  153 +unsigned int kw_winctrl_calcsize(unsigned int sizeval);
  154 +#endif /* __ASSEMBLY__ */
  155 +#endif /* _KWCPU_H */
arch/arm/mach-kirkwood/include/mach/gpio.h
Diff comments   View file @ ea38572
  1 +/*
  2 + * arch/asm-arm/mach-kirkwood/include/mach/gpio.h
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +/*
  8 + * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
  9 + * Removed kernel level irq handling. Took some macros from kernel to
  10 + * allow build.
  11 + *
  12 + * Dieter Kiermaier dk-arm-linux@gmx.de
  13 + */
  14 +
  15 +#ifndef __KIRKWOOD_GPIO_H
  16 +#define __KIRKWOOD_GPIO_H
  17 +
  18 +/* got from kernel include/linux/bitops.h */
  19 +#define BITS_PER_BYTE 8
  20 +#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
  21 +
  22 +#define GPIO_MAX 50
  23 +#define GPIO_OFF(pin) (((pin) >> 5) ? 0x0040 : 0x0000)
  24 +#define GPIO_OUT(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x00)
  25 +#define GPIO_IO_CONF(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x04)
  26 +#define GPIO_BLINK_EN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x08)
  27 +#define GPIO_IN_POL(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x0c)
  28 +#define GPIO_DATA_IN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x10)
  29 +#define GPIO_EDGE_CAUSE(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x14)
  30 +#define GPIO_EDGE_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x18)
  31 +#define GPIO_LEVEL_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x1c)
  32 +
  33 +/*
  34 + * Kirkwood-specific GPIO API
  35 + */
  36 +
  37 +void kw_gpio_set_valid(unsigned pin, int mode);
  38 +int kw_gpio_is_valid(unsigned pin, int mode);
  39 +int kw_gpio_direction_input(unsigned pin);
  40 +int kw_gpio_direction_output(unsigned pin, int value);
  41 +int kw_gpio_get_value(unsigned pin);
  42 +void kw_gpio_set_value(unsigned pin, int value);
  43 +void kw_gpio_set_blink(unsigned pin, int blink);
  44 +void kw_gpio_set_unused(unsigned pin);
  45 +
  46 +#define GPIO_INPUT_OK (1 << 0)
  47 +#define GPIO_OUTPUT_OK (1 << 1)
  48 +
  49 +#endif
arch/arm/mach-kirkwood/include/mach/kw88f6192.h
Diff comments   View file @ ea38572
  1 +/*
  2 + * (C) Copyright 2009
  3 + * Marvell Semiconductor <www.marvell.com>
  4 + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  5 + *
  6 + * Header file for Feroceon CPU core 88FR131 Based KW88F6192 SOC.
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#ifndef _CONFIG_KW88F6192_H
  12 +#define _CONFIG_KW88F6192_H
  13 +
  14 +/* SOC specific definations */
  15 +#define KW88F6192_REGS_PHYS_BASE 0xf1000000
  16 +#define KW_REGS_PHY_BASE KW88F6192_REGS_PHYS_BASE
  17 +
  18 +/* TCLK Core Clock defination */
  19 +#define CONFIG_SYS_TCLK 166000000 /* 166MHz */
  20 +
  21 +#endif /* _CONFIG_KW88F6192_H */
arch/arm/mach-kirkwood/include/mach/kw88f6281.h
Diff comments   View file @ ea38572
  1 +/*
  2 + * (C) Copyright 2009
  3 + * Marvell Semiconductor <www.marvell.com>
  4 + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  5 + *
  6 + * Header file for Feroceon CPU core 88FR131 Based KW88F6281 SOC.
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#ifndef _ASM_ARCH_KW88F6281_H
  12 +#define _ASM_ARCH_KW88F6281_H
  13 +
  14 +/* SOC specific definitions */
  15 +#define KW88F6281_REGS_PHYS_BASE 0xf1000000
  16 +#define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE
  17 +
  18 +/* TCLK Core Clock definition */
  19 +#ifndef CONFIG_SYS_TCLK
  20 +#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
  21 +#endif
  22 +
  23 +#endif /* _ASM_ARCH_KW88F6281_H */
arch/arm/mach-kirkwood/include/mach/mpp.h
Diff comments   View file @ ea38572
  1 +/*
  2 + * linux/arch/arm/mach-kirkwood/mpp.h -- Multi Purpose Pins
  3 + *
  4 + * Copyright 2009: Marvell Technology Group Ltd.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __KIRKWOOD_MPP_H
  10 +#define __KIRKWOOD_MPP_H
  11 +
  12 +#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \
  13 + /* MPP number */ ((_num) & 0xff) | \
  14 + /* MPP select value */ (((_sel) & 0xf) << 8) | \
  15 + /* may be input signal */ ((!!(_in)) << 12) | \
  16 + /* may be output signal */ ((!!(_out)) << 13) | \
  17 + /* available on F6180 */ ((!!(_F6180)) << 14) | \
  18 + /* available on F6190 */ ((!!(_F6190)) << 15) | \
  19 + /* available on F6192 */ ((!!(_F6192)) << 16) | \
  20 + /* available on F6281 */ ((!!(_F6281)) << 17))
  21 +
  22 +#define MPP_NUM(x) ((x) & 0xff)
  23 +#define MPP_SEL(x) (((x) >> 8) & 0xf)
  24 +
  25 + /* num sel i o 6180 6190 6192 6281 */
  26 +
  27 +#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0 )
  28 +#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0 )
  29 +
  30 +#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0 )
  31 +#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0 )
  32 +#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0 )
  33 +#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1 )
  34 +
  35 +#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1 )
  36 +#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1 )
  37 +#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1 )
  38 +
  39 +#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1 )
  40 +#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1 )
  41 +#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1 )
  42 +
  43 +#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1 )
  44 +#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1 )
  45 +#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1 )
  46 +
  47 +#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1 )
  48 +#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1 )
  49 +#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1 )
  50 +
  51 +#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1 )
  52 +#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1 )
  53 +#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1 )
  54 +#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1 )
  55 +#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1 )
  56 +
  57 +#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1 )
  58 +#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1 )
  59 +#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1 )
  60 +#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1 )
  61 +#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1 )
  62 +
  63 +#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1 )
  64 +#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1 )
  65 +#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1 )
  66 +
  67 +#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1 )
  68 +#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1 )
  69 +#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 )
  70 +#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 )
  71 +
  72 +#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 )
  73 +#define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 )
  74 +#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 )
  75 +#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 )
  76 +#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1 )
  77 +#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1 )
  78 +#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1 )
  79 +#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1 )
  80 +
  81 +#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1 )
  82 +#define MPP9_TW_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1 )
  83 +#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1 )
  84 +#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1 )
  85 +#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1 )
  86 +#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1 )
  87 +#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1 )
  88 +
  89 +#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1 )
  90 +#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1 )
  91 +#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1 )
  92 +#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1 )
  93 +#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1 )
  94 +
  95 +#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1 )
  96 +#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1 )
  97 +#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1 )
  98 +#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1 )
  99 +#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1 )
  100 +#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1 )
  101 +#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1 )
  102 +
  103 +#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1 )
  104 +#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1 )
  105 +
  106 +#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1 )
  107 +#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1 )
  108 +#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1 )
  109 +
  110 +#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1 )
  111 +#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1 )
  112 +#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1 )
  113 +#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1 )
  114 +#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1 )
  115 +
  116 +#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1 )
  117 +#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1 )
  118 +#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1 )
  119 +#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1 )
  120 +#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1 )
  121 +
  122 +#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1 )
  123 +#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1 )
  124 +#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1 )
  125 +#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1 )
  126 +#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1 )
  127 +#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1 )
  128 +
  129 +#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1 )
  130 +#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1 )
  131 +#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1 )
  132 +
  133 +#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1 )
  134 +#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1 )
  135 +
  136 +#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1 )
  137 +#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1 )
  138 +
  139 +#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1 )
  140 +#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1 )
  141 +#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1 )
  142 +#define MPP20_GE1_0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1 )
  143 +#define MPP20_AUDIO_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1 )
  144 +#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1 )
  145 +
  146 +#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1 )
  147 +#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1 )
  148 +#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1 )
  149 +#define MPP21_GE1_1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1 )
  150 +#define MPP21_AUDIO_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1 )
  151 +#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1 )
  152 +
  153 +#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1 )
  154 +#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1 )
  155 +#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1 )
  156 +#define MPP22_GE1_2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1 )
  157 +#define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1 )
  158 +#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1 )
  159 +
  160 +#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1 )
  161 +#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1 )
  162 +#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1 )
  163 +#define MPP23_GE1_3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1 )
  164 +#define MPP23_AUDIO_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1 )
  165 +#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1 )
  166 +
  167 +#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1 )
  168 +#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1 )
  169 +#define MPP24_TDM_SPI_CS0 DEV( 24, 0x2, 0, 1, 0, 0, 1, 1 )
  170 +#define MPP24_GE1_4 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1 )
  171 +#define MPP24_AUDIO_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1 )
  172 +
  173 +#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1 )
  174 +#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1 )
  175 +#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1 )
  176 +#define MPP25_GE1_5 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1 )
  177 +#define MPP25_AUDIO_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1 )
  178 +
  179 +#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1 )
  180 +#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1 )
  181 +#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1 )
  182 +#define MPP26_GE1_6 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1 )
  183 +#define MPP26_AUDIO_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1 )
  184 +
  185 +#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1 )
  186 +#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1 )
  187 +#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1 )
  188 +#define MPP27_GE1_7 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1 )
  189 +#define MPP27_AUDIO_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1 )
  190 +
  191 +#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1 )
  192 +#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1 )
  193 +#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1 )
  194 +#define MPP28_GE1_8 MPP( 28, 0x3, 0, 0, 0, 1, 1, 1 )
  195 +#define MPP28_AUDIO_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1 )
  196 +
  197 +#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1 )
  198 +#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1 )
  199 +#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1 )
  200 +#define MPP29_GE1_9 MPP( 29, 0x3, 0, 0, 0, 1, 1, 1 )
  201 +
  202 +#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1 )
  203 +#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1 )
  204 +#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1 )
  205 +#define MPP30_GE1_10 MPP( 30, 0x3, 0, 0, 0, 1, 1, 1 )
  206 +
  207 +#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1 )
  208 +#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1 )
  209 +#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1 )
  210 +#define MPP31_GE1_11 MPP( 31, 0x3, 0, 0, 0, 1, 1, 1 )
  211 +
  212 +#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1 )
  213 +#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1 )
  214 +#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1 )
  215 +#define MPP32_GE1_12 MPP( 32, 0x3, 0, 0, 0, 1, 1, 1 )
  216 +
  217 +#define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 )
  218 +#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 )
  219 +#define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 )
  220 +
  221 +#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 )
  222 +#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 )
  223 +#define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 )
  224 +
  225 +#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 )
  226 +#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 )
  227 +#define MPP35_GE1_15 MPP( 35, 0x3, 0, 0, 0, 1, 1, 1 )
  228 +#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1 )
  229 +#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1 )
  230 +
  231 +#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1 )
  232 +#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1 )
  233 +#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1 )
  234 +#define MPP36_AUDIO_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1 )
  235 +
  236 +#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1 )
  237 +#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1 )
  238 +#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1 )
  239 +#define MPP37_AUDIO_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1 )
  240 +
  241 +#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1 )
  242 +#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1 )
  243 +#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1 )
  244 +#define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1 )
  245 +
  246 +#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1 )
  247 +#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1 )
  248 +#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1 )
  249 +#define MPP39_AUDIO_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1 )
  250 +
  251 +#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1 )
  252 +#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1 )
  253 +#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1 )
  254 +#define MPP40_AUDIO_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1 )
  255 +
  256 +#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1 )
  257 +#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1 )
  258 +#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1 )
  259 +#define MPP41_AUDIO_I2SLRC MPP( 41, 0x4, 0, 1, 1, 0, 0, 1 )
  260 +
  261 +#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1 )
  262 +#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1 )
  263 +#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1 )
  264 +#define MPP42_AUDIO_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1 )
  265 +
  266 +#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1 )
  267 +#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1 )
  268 +#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1 )
  269 +#define MPP43_AUDIO_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1 )
  270 +
  271 +#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1 )
  272 +#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1 )
  273 +#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1 )
  274 +#define MPP44_AUDIO_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1 )
  275 +
  276 +#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1 )
  277 +#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1 )
  278 +#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1 )
  279 +
  280 +#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1 )
  281 +#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1 )
  282 +#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1 )
  283 +
  284 +#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1 )
  285 +#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1 )
  286 +#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1 )
  287 +
  288 +#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1 )
  289 +#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1 )
  290 +#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1 )
  291 +
  292 +#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1 )
  293 +#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1 )
  294 +#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1 )
  295 +#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1 )
  296 +
  297 +#define MPP_MAX 49
  298 +
  299 +void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save);
  300 +
  301 +#endif
arch/arm/mach-kirkwood/include/mach/soc.h
Diff comments   View file @ ea38572
  1 +/*
  2 + * (C) Copyright 2009
  3 + * Marvell Semiconductor <www.marvell.com>
  4 + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  5 + *
  6 + * Header file for the Marvell's Feroceon CPU core.
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#ifndef _ASM_ARCH_KIRKWOOD_H
  12 +#define _ASM_ARCH_KIRKWOOD_H
  13 +
  14 +#if defined (CONFIG_FEROCEON_88FR131) || defined (CONFIG_SHEEVA_88SV131)
  15 +
  16 +/* SOC specific definations */
  17 +#define INTREG_BASE 0xd0000000
  18 +#define KW_REGISTER(x) (KW_REGS_PHY_BASE + x)
  19 +#define KW_OFFSET_REG (INTREG_BASE + 0x20080)
  20 +
  21 +/* undocumented registers */
  22 +#define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470))
  23 +#define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478))
  24 +
  25 +#define MVEBU_SDRAM_BASE (KW_REGISTER(0x1500))
  26 +#define KW_TWSI_BASE (KW_REGISTER(0x11000))
  27 +#define KW_UART0_BASE (KW_REGISTER(0x12000))
  28 +#define KW_UART1_BASE (KW_REGISTER(0x12100))
  29 +#define KW_MPP_BASE (KW_REGISTER(0x10000))
  30 +#define MVEBU_GPIO0_BASE (KW_REGISTER(0x10100))
  31 +#define MVEBU_GPIO1_BASE (KW_REGISTER(0x10140))
  32 +#define KW_RTC_BASE (KW_REGISTER(0x10300))
  33 +#define KW_NANDF_BASE (KW_REGISTER(0x10418))
  34 +#define MVEBU_SPI_BASE (KW_REGISTER(0x10600))
  35 +#define KW_CPU_WIN_BASE (KW_REGISTER(0x20000))
  36 +#define KW_CPU_REG_BASE (KW_REGISTER(0x20100))
  37 +#define MVEBU_TIMER_BASE (KW_REGISTER(0x20300))
  38 +#define KW_REG_PCIE_BASE (KW_REGISTER(0x40000))
  39 +#define KW_USB20_BASE (KW_REGISTER(0x50000))
  40 +#define KW_EGIGA0_BASE (KW_REGISTER(0x72000))
  41 +#define KW_EGIGA1_BASE (KW_REGISTER(0x76000))
  42 +#define KW_SATA_BASE (KW_REGISTER(0x80000))
  43 +#define KW_SDIO_BASE (KW_REGISTER(0x90000))
  44 +
  45 +/* Kirkwood Sata controller has two ports */
  46 +#define KW_SATA_PORT0_OFFSET 0x2000
  47 +#define KW_SATA_PORT1_OFFSET 0x4000
  48 +
  49 +/* Kirkwood GbE controller has two ports */
  50 +#define MAX_MVGBE_DEVS 2
  51 +#define MVGBE0_BASE KW_EGIGA0_BASE
  52 +#define MVGBE1_BASE KW_EGIGA1_BASE
  53 +
  54 +/* Kirkwood USB Host controller */
  55 +#define MVUSB0_BASE KW_USB20_BASE
  56 +#define MVUSB0_CPU_ATTR_DRAM_CS0 KWCPU_ATTR_DRAM_CS0
  57 +#define MVUSB0_CPU_ATTR_DRAM_CS1 KWCPU_ATTR_DRAM_CS1
  58 +#define MVUSB0_CPU_ATTR_DRAM_CS2 KWCPU_ATTR_DRAM_CS2
  59 +#define MVUSB0_CPU_ATTR_DRAM_CS3 KWCPU_ATTR_DRAM_CS3
  60 +
  61 +/* Kirkwood CPU memory windows */
  62 +#define MVCPU_WIN_CTRL_DATA KWCPU_WIN_CTRL_DATA
  63 +#define MVCPU_WIN_ENABLE KWCPU_WIN_ENABLE
  64 +#define MVCPU_WIN_DISABLE KWCPU_WIN_DISABLE
  65 +
  66 +#if defined (CONFIG_KW88F6281)
  67 +#include <asm/arch/kw88f6281.h>
  68 +#elif defined (CONFIG_KW88F6192)
  69 +#include <asm/arch/kw88f6192.h>
  70 +#else
  71 +#error "SOC Name not defined"
  72 +#endif /* CONFIG_KW88F6281 */
  73 +#endif /* CONFIG_FEROCEON_88FR131 */
  74 +#endif /* _ASM_ARCH_KIRKWOOD_H */
include/configs/km/km_arm.h
Diff comments   View file @ ea38572
... ... @@ -195,7 +195,7 @@
195 195 }
196 196  
197 197 #ifndef __ASSEMBLY__
198   -#include <asm/arch-kirkwood/gpio.h>
  198 +#include <asm/arch/gpio.h>
199 199 extern void __set_direction(unsigned pin, int high);
200 200 void set_sda(int state);
201 201 void set_scl(int state);