Eric Lee / smarc-uboot

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Commit ebf8644a113a36b163c2e06fe1e081c73f563c3a

Authored by Albert ARIBAUD
2 parents 7d2f669b94 b219773957
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'

Showing 44 changed files Side-by-side Diff

... ... @@ -336,6 +336,9 @@
336 336 config ARCH_EXYNOS
337 337 bool "Samsung EXYNOS"
338 338  
  339 +config ARCH_S5PC1XX
  340 + bool "Samsung S5PC1XX"
  341 +
339 342 config ARCH_HIGHBANK
340 343 bool "Calxeda Highbank"
341 344  
... ... @@ -432,12 +435,6 @@
432 435 config TARGET_CM_FX6
433 436 bool "Support cm_fx6"
434 437  
435   -config TARGET_S5P_GONI
436   - bool "Support s5p_goni"
437   -
438   -config TARGET_SMDKC100
439   - bool "Support smdkc100"
440   -
441 438 config TARGET_SOCFPGA_CYCLONE5
442 439 bool "Support socfpga_cyclone5"
443 440  
... ... @@ -553,6 +550,8 @@
553 550  
554 551 source "arch/arm/cpu/armv7/rmobile/Kconfig"
555 552  
  553 +source "arch/arm/cpu/armv7/s5pc1xx/Kconfig"
  554 +
556 555 source "arch/arm/cpu/armv7/tegra-common/Kconfig"
557 556  
558 557 source "arch/arm/cpu/armv7/uniphier/Kconfig"
559 558  
... ... @@ -661,9 +660,7 @@
661 660 source "board/ronetix/pm9261/Kconfig"
662 661 source "board/ronetix/pm9263/Kconfig"
663 662 source "board/ronetix/pm9g45/Kconfig"
664   -source "board/samsung/goni/Kconfig"
665 663 source "board/samsung/smdk2410/Kconfig"
666   -source "board/samsung/smdkc100/Kconfig"
667 664 source "board/sandisk/sansa_fuze_plus/Kconfig"
668 665 source "board/scb9328/Kconfig"
669 666 source "board/schulercontrol/sc_sps_1/Kconfig"
arch/arm/cpu/armv7/exynos/Kconfig
Diff comments   View file @ ebf8644
... ... @@ -5,6 +5,7 @@
5 5  
6 6 config TARGET_SMDKV310
7 7 bool "Exynos4210 SMDKV310 board"
  8 + select OF_CONTROL if !SPL_BUILD
8 9  
9 10 config TARGET_TRATS
10 11 bool "Exynos4210 Trats board"
arch/arm/cpu/armv7/s5pc1xx/Kconfig
Diff comments   View file @ ebf8644
  1 +if ARCH_S5PC1XX
  2 +
  3 +choice
  4 + prompt "S5PC1XX board select"
  5 +
  6 +config TARGET_S5P_GONI
  7 + bool "S5P Goni board"
  8 + select OF_CONTROL if !SPL_BUILD
  9 +
  10 +config TARGET_SMDKC100
  11 + bool "Support smdkc100 board"
  12 + select OF_CONTROL if !SPL_BUILD
  13 +
  14 +endchoice
  15 +
  16 +config SYS_CPU
  17 + default "armv7"
  18 +
  19 +config SYS_SOC
  20 + default "s5pc1xx"
  21 +
  22 +source "board/samsung/goni/Kconfig"
  23 +source "board/samsung/smdkc100/Kconfig"
  24 +
  25 +endif
arch/arm/cpu/armv7/s5pc1xx/cache.S
View file @ ebf8644
1   -/*
2   - * Copyright (C) 2009 Samsung Electronics
3   - * Minkyu Kang <mk7.kang@samsung.com>
4   - *
5   - * based on arch/arm/cpu/armv7/omap3/cache.S
6   - *
7   - * SPDX-License-Identifier: GPL-2.0+
8   - */
9   -
10   -.align 5
11   -
12   -#include <linux/linkage.h>
13   -
14   -#ifndef CONFIG_SYS_L2CACHE_OFF
15   -ENTRY(v7_outer_cache_enable)
16   - push {r0, r1, r2, lr}
17   - mrc 15, 0, r3, cr1, cr0, 1
18   - orr r3, r3, #2
19   - mcr 15, 0, r3, cr1, cr0, 1
20   - pop {r1, r2, r3, pc}
21   -ENDPROC(v7_outer_cache_enable)
22   -
23   -ENTRY(v7_outer_cache_disable)
24   - push {r0, r1, r2, lr}
25   - mrc 15, 0, r3, cr1, cr0, 1
26   - bic r3, r3, #2
27   - mcr 15, 0, r3, cr1, cr0, 1
28   - pop {r1, r2, r3, pc}
29   -ENDPROC(v7_outer_cache_disable)
30   -#endif
arch/arm/cpu/armv7/s5pc1xx/cache.c
Diff comments   View file @ ebf8644
  1 +/*
  2 + * Copyright (C) 2014 Samsung Electronics
  3 + * Minkyu Kang <mk7.kang@samsung.com>
  4 + * Robert Baldyga <r.baldyga@samsung.com>
  5 + *
  6 + * based on arch/arm/cpu/armv7/omap3/cache.S
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#include <common.h>
  12 +
  13 +#ifndef CONFIG_SYS_DCACHE_OFF
  14 +void enable_caches(void)
  15 +{
  16 + dcache_enable();
  17 +}
  18 +
  19 +void disable_caches(void)
  20 +{
  21 + dcache_disable();
  22 +}
  23 +#endif
  24 +
  25 +#ifndef CONFIG_SYS_L2CACHE_OFF
  26 +void v7_outer_cache_enable(void)
  27 +{
  28 + __asm(
  29 + "push {r0, r1, r2, lr}\n\t"
  30 + "mrc 15, 0, r3, cr1, cr0, 1\n\t"
  31 + "orr r3, r3, #2\n\t"
  32 + "mcr 15, 0, r3, cr1, cr0, 1\n\t"
  33 + "pop {r1, r2, r3, pc}"
  34 + );
  35 +}
  36 +
  37 +void v7_outer_cache_disable(void)
  38 +{
  39 + __asm(
  40 + "push {r0, r1, r2, lr}\n\t"
  41 + "mrc 15, 0, r3, cr1, cr0, 1\n\t"
  42 + "bic r3, r3, #2\n\t"
  43 + "mcr 15, 0, r3, cr1, cr0, 1\n\t"
  44 + "pop {r1, r2, r3, pc}"
  45 + );
  46 +}
  47 +#endif
arch/arm/dts/Makefile
Diff comments   View file @ ebf8644
  1 +dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb
  2 +dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb
1 3 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
  4 + exynos4210-smdkv310.dtb \
2 5 exynos4210-universal_c210.dtb \
3 6 exynos4210-trats.dtb \
4 7 exynos4412-trats2.dtb \
arch/arm/dts/exynos4210-smdkv310.dts
Diff comments   View file @ ebf8644
  1 +/*
  2 + * Samsung's Exynos4210-based SMDKV310 board device tree source
  3 + *
  4 + * Copyright (c) 2014 Google, Inc
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +/dts-v1/;
  10 +/include/ "exynos4.dtsi"
  11 +
  12 +/ {
  13 + model = "Samsung SMDKV310 on Exynos4210";
  14 + compatible = "samsung,smdkv310", "samsung,exynos4210";
  15 +
  16 + aliases {
  17 + serial0 = "/serial@13800000";
  18 + console = "/serial@13820000";
  19 + };
  20 +
  21 +};
arch/arm/dts/exynos5420-peach-pit.dts
Diff comments   View file @ ebf8644
... ... @@ -28,11 +28,66 @@
28 28 pmic = "/i2c@12ca0000";
29 29 };
30 30  
  31 + cros-ec-keyb {
  32 + compatible = "google,cros-ec-keyb";
  33 + google,key-rows = <8>;
  34 + google,key-columns = <13>;
  35 + google,repeat-delay-ms = <240>;
  36 + google,repeat-rate-ms = <30>;
  37 + google,ghost-filter;
  38 + /*
  39 + * Keymap entries take the form of 0xRRCCKKKK where
  40 + * RR=Row CC=Column KKKK=Key Code
  41 + * The values below are for a US keyboard layout and
  42 + * are taken from the Linux driver. Note that the
  43 + * 102ND key is not used for US keyboards.
  44 + */
  45 + linux,keymap = <
  46 + /* CAPSLCK F1 B F10 */
  47 + 0x0001003a 0x0002003b 0x00030030 0x00040044
  48 + /* N = R_ALT ESC */
  49 + 0x00060031 0x0008000d 0x000a0064 0x01010001
  50 + /* F4 G F7 H */
  51 + 0x0102003e 0x01030022 0x01040041 0x01060023
  52 + /* ' F9 BKSPACE L_CTRL */
  53 + 0x01080028 0x01090043 0x010b000e 0x0200001d
  54 + /* TAB F3 T F6 */
  55 + 0x0201000f 0x0202003d 0x02030014 0x02040040
  56 + /* ] Y 102ND [ */
  57 + 0x0205001b 0x02060015 0x02070056 0x0208001a
  58 + /* F8 GRAVE F2 5 */
  59 + 0x02090042 0x03010029 0x0302003c 0x03030006
  60 + /* F5 6 - \ */
  61 + 0x0304003f 0x03060007 0x0308000c 0x030b002b
  62 + /* R_CTRL A D F */
  63 + 0x04000061 0x0401001e 0x04020020 0x04030021
  64 + /* S K J ; */
  65 + 0x0404001f 0x04050025 0x04060024 0x04080027
  66 + /* L ENTER Z C */
  67 + 0x04090026 0x040b001c 0x0501002c 0x0502002e
  68 + /* V X , M */
  69 + 0x0503002f 0x0504002d 0x05050033 0x05060032
  70 + /* L_SHIFT / . SPACE */
  71 + 0x0507002a 0x05080035 0x05090034 0x050B0039
  72 + /* 1 3 4 2 */
  73 + 0x06010002 0x06020004 0x06030005 0x06040003
  74 + /* 8 7 0 9 */
  75 + 0x06050009 0x06060008 0x0608000b 0x0609000a
  76 + /* L_ALT DOWN RIGHT Q */
  77 + 0x060a0038 0x060b006c 0x060c006a 0x07010010
  78 + /* E R W I */
  79 + 0x07020012 0x07030013 0x07040011 0x07050017
  80 + /* U R_SHIFT P O */
  81 + 0x07060016 0x07070036 0x07080019 0x07090018
  82 + /* UP LEFT */
  83 + 0x070b0067 0x070c0069>;
  84 + };
  85 +
31 86 dmc {
32 87 mem-manuf = "samsung";
33 88 mem-type = "ddr3";
34 89 clock-frequency = <800000000>;
35   - arm-frequency = <1700000000>;
  90 + arm-frequency = <900000000>;
36 91 };
37 92  
38 93 tmu@10060000 {
arch/arm/dts/s5pc1xx-goni.dts
Diff comments   View file @ ebf8644
  1 +/*
  2 + * Samsung's S5PC110-based Goni board device tree source
  3 + *
  4 + * Copyright (c) 2014 Google, Inc
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +/dts-v1/;
  10 +
  11 +#include "skeleton.dtsi"
  12 +
  13 +/ {
  14 + model = "Samsung Goni based on S5PC110";
  15 + compatible = "samsung,goni", "samsung,s5pc110";
  16 +
  17 + aliases {
  18 + serial2 = "/serial@e2900800";
  19 + console = "/serial@e2900800";
  20 + };
  21 +
  22 + serial@e2900800 {
  23 + compatible = "samsung,exynos4210-uart";
  24 + reg = <0xe2900800 0x400>;
  25 + id = <2>;
  26 + };
  27 +
  28 +};
arch/arm/dts/s5pc1xx-smdkc100.dts
Diff comments   View file @ ebf8644
  1 +/*
  2 + * Samsung's Exynos4210-based SMDKV310 board device tree source
  3 + *
  4 + * Copyright (c) 2014 Google, Inc
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +/dts-v1/;
  10 +
  11 +#include "skeleton.dtsi"
  12 +
  13 +/ {
  14 + model = "Samsung SMDKC100 based on S5PC100";
  15 + compatible = "samsung,smdkc100", "samsung,s5pc100";
  16 +
  17 + aliases {
  18 + serial0 = "/serial@ec000000";
  19 + console = "/serial@ec000000";
  20 + };
  21 +
  22 + serial@ec000000 {
  23 + compatible = "samsung,exynos4210-uart";
  24 + reg = <0xec000000 0x100>;
  25 + interrupts = <0 51 0>;
  26 + id = <0>;
  27 + };
  28 +
  29 +};
arch/arm/include/asm/arch-s5pc1xx/periph.h
Diff comments   View file @ ebf8644
  1 +/*
  2 + * Copyright (C) 2012 Samsung Electronics
  3 + * Rajeshwari Shinde <rajeshwari.s@samsung.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef __ASM_ARM_ARCH_PERIPH_H
  9 +#define __ASM_ARM_ARCH_PERIPH_H
  10 +
  11 +/*
  12 + * Peripherals required for pinmux configuration. List will
  13 + * grow with support for more devices getting added.
  14 + * Numbering based on interrupt table.
  15 + *
  16 + */
  17 +enum periph_id {
  18 + PERIPH_ID_UART0 = 51,
  19 + PERIPH_ID_UART1,
  20 + PERIPH_ID_UART2,
  21 + PERIPH_ID_UART3,
  22 + PERIPH_ID_I2C0 = 56,
  23 + PERIPH_ID_I2C1,
  24 + PERIPH_ID_I2C2,
  25 + PERIPH_ID_I2C3,
  26 + PERIPH_ID_I2C4,
  27 + PERIPH_ID_I2C5,
  28 + PERIPH_ID_I2C6,
  29 + PERIPH_ID_I2C7,
  30 + PERIPH_ID_SPI0 = 68,
  31 + PERIPH_ID_SPI1,
  32 + PERIPH_ID_SPI2,
  33 + PERIPH_ID_SDMMC0 = 75,
  34 + PERIPH_ID_SDMMC1,
  35 + PERIPH_ID_SDMMC2,
  36 + PERIPH_ID_SDMMC3,
  37 + PERIPH_ID_I2C8 = 87,
  38 + PERIPH_ID_I2C9,
  39 + PERIPH_ID_I2S0 = 98,
  40 + PERIPH_ID_I2S1 = 99,
  41 +
  42 + /* Since following peripherals do
  43 + * not have shared peripheral interrupts (SPIs)
  44 + * they are numbered arbitiraly after the maximum
  45 + * SPIs Exynos has (128)
  46 + */
  47 + PERIPH_ID_SROMC = 128,
  48 + PERIPH_ID_SPI3,
  49 + PERIPH_ID_SPI4,
  50 + PERIPH_ID_SDMMC4,
  51 + PERIPH_ID_PWM0,
  52 + PERIPH_ID_PWM1,
  53 + PERIPH_ID_PWM2,
  54 + PERIPH_ID_PWM3,
  55 + PERIPH_ID_PWM4,
  56 + PERIPH_ID_I2C10 = 203,
  57 +
  58 + PERIPH_ID_NONE = -1,
  59 +};
  60 +
  61 +#endif /* __ASM_ARM_ARCH_PERIPH_H */
arch/arm/include/asm/arch-s5pc1xx/pinmux.h
Diff comments   View file @ ebf8644
  1 +/*
  2 + * Copyright (C) 2012 Samsung Electronics
  3 + * Abhilash Kesavan <a.kesavan@samsung.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef __ASM_ARM_ARCH_PINMUX_H
  9 +#define __ASM_ARM_ARCH_PINMUX_H
  10 +
  11 +#include "periph.h"
  12 +
  13 +/*
  14 + * Flags for setting specific configarations of peripherals.
  15 + * List will grow with support for more devices getting added.
  16 + */
  17 +enum {
  18 + PINMUX_FLAG_NONE = 0x00000000,
  19 +
  20 + /* Flags for eMMC */
  21 + PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */
  22 +
  23 + /* Flags for SROM controller */
  24 + PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */
  25 + PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */
  26 +};
  27 +
  28 +/**
  29 + * Configures the pinmux for a particular peripheral.
  30 + *
  31 + * Each gpio can be configured in many different ways (4 bits on exynos)
  32 + * such as "input", "output", "special function", "external interrupt"
  33 + * etc. This function will configure the peripheral pinmux along with
  34 + * pull-up/down and drive strength.
  35 + *
  36 + * @param peripheral peripheral to be configured
  37 + * @param flags configure flags
  38 + * @return 0 if ok, -1 on error (e.g. unsupported peripheral)
  39 + */
  40 +int exynos_pinmux_config(int peripheral, int flags);
  41 +
  42 +/**
  43 + * Decode the peripheral id using the interrpt numbers.
  44 + *
  45 + * @param blob Device tree blob
  46 + * @param node FDT I2C node to find
  47 + * @return peripheral id if ok, PERIPH_ID_NONE on error
  48 + */
  49 +int pinmux_decode_periph_id(const void *blob, int node);
  50 +#endif
board/samsung/odroid/odroid.c
Diff comments   View file @ ebf8644
... ... @@ -158,10 +158,10 @@
158 158 * For MOUThpm = 1000 MHz (MOUTapll)
159 159 * doutcopy = MOUThpm / (ratio + 1) = 200 (4)
160 160 * sclkhpm = doutcopy / (ratio + 1) = 200 (4)
161   - * cores_out = armclk / (ratio + 1) = 1000 (0)
  161 + * cores_out = armclk / (ratio + 1) = 200 (4)
162 162 */
163 163 clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7);
164   - set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(0);
  164 + set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4);
165 165  
166 166 clrsetbits_le32(&clk->div_cpu1, clr, set);
167 167  
... ... @@ -195,8 +195,8 @@
195 195 while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
196 196 continue;
197 197  
198   - /* Set MPLL to 880MHz */
199   - set = SDIV(0) | PDIV(3) | MDIV(110) | FSEL(0) | PLL_ENABLE(1);
  198 + /* Set MPLL to 800MHz */
  199 + set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1);
200 200  
201 201 clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
202 202  
203 203  
... ... @@ -220,15 +220,15 @@
220 220 DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7);
221 221 /*
222 222 * For:
223   - * MOUTdmc = 880 MHz
224   - * MOUTdphy = 880 MHz
  223 + * MOUTdmc = 800 MHz
  224 + * MOUTdphy = 800 MHz
225 225 *
226   - * aclk_acp = MOUTdmc / (ratio + 1) = 220 (3)
227   - * pclk_acp = aclk_acp / (ratio + 1) = 110 (1)
228   - * sclk_dphy = MOUTdphy / (ratio + 1) = 440 (1)
229   - * sclk_dmc = MOUTdmc / (ratio + 1) = 440 (1)
230   - * aclk_dmcd = sclk_dmc / (ratio + 1) = 220 (1)
231   - * aclk_dmcp = aclk_dmcd / (ratio + 1) = 110 (1)
  226 + * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3)
  227 + * pclk_acp = aclk_acp / (ratio + 1) = 100 (1)
  228 + * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1)
  229 + * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1)
  230 + * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1)
  231 + * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1)
232 232 */
233 233 set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |
234 234 DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);
235 235  
... ... @@ -244,13 +244,13 @@
244 244 C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127);
245 245 /*
246 246 * For:
247   - * MOUTg2d = 880 MHz
248   - * MOUTc2c = 880 Mhz
  247 + * MOUTg2d = 800 MHz
  248 + * MOUTc2c = 800 Mhz
249 249 * MOUTpwi = 108 MHz
250 250 *
251   - * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 440 (1)
252   - * sclk_c2c = MOUTc2c / (ratio + 1) = 440 (1)
253   - * aclk_c2c = sclk_c2c / (ratio + 1) = 220 (1)
  251 + * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1)
  252 + * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1)
  253 + * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1)
254 254 * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5)
255 255 */
256 256 set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) |
257 257  
... ... @@ -282,9 +282,9 @@
282 282 clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
283 283 UART3_RATIO(15) | UART4_RATIO(15);
284 284 /*
285   - * For MOUTuart0-4: 880MHz
  285 + * For MOUTuart0-4: 800MHz
286 286 *
287   - * SCLK_UARTx = MOUTuartX / (ratio + 1) = 110 (7)
  287 + * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7)
288 288 */
289 289 set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |
290 290 UART3_RATIO(7) | UART4_RATIO(7);
291 291  
... ... @@ -298,12 +298,12 @@
298 298 clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) |
299 299 MMC1_PRE_RATIO(255);
300 300 /*
301   - * For MOUTmmc0-3 = 880 MHz (MPLL)
  301 + * For MOUTmmc0-3 = 800 MHz (MPLL)
302 302 *
303   - * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 110 (7)
304   - * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 60 (1)
305   - * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 110 (7)
306   - * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 60 (1)
  303 + * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7)
  304 + * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1)
  305 + * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7)
  306 + * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1)
307 307 */
308 308 set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |
309 309 MMC1_PRE_RATIO(1);
310 310  
... ... @@ -318,12 +318,12 @@
318 318 clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) |
319 319 MMC3_PRE_RATIO(255);
320 320 /*
321   - * For MOUTmmc0-3 = 880 MHz (MPLL)
  321 + * For MOUTmmc0-3 = 800 MHz (MPLL)
322 322 *
323   - * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 110 (7)
324   - * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 60 (1)
325   - * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 110 (7)
326   - * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 60 (1)
  323 + * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7)
  324 + * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1)
  325 + * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7)
  326 + * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1)
327 327 */
328 328 set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |
329 329 MMC3_PRE_RATIO(1);
330 330  
... ... @@ -337,10 +337,10 @@
337 337 /* CLK_DIV_FSYS3 */
338 338 clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255);
339 339 /*
340   - * For MOUTmmc4 = 880 MHz (MPLL)
  340 + * For MOUTmmc4 = 800 MHz (MPLL)
341 341 *
342   - * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 110 (7)
343   - * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 110 (0)
  342 + * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7)
  343 + * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0)
344 344 */
345 345 set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0);
346 346  
board/samsung/smdk5250/MAINTAINERS
Diff comments   View file @ ebf8644
... ... @@ -6,7 +6,7 @@
6 6 F: configs/smdk5250_defconfig
7 7  
8 8 SNOW BOARD
9   -M: Rajeshwari Shinde <rajeshwari.s@samsung.com>
  9 +M: Akshay Saraswat <akshay.s@samsung.com>
10 10 S: Maintained
11 11 F: include/configs/snow.h
12 12 F: configs/snow_defconfig
board/samsung/smdk5420/MAINTAINERS
Diff comments   View file @ ebf8644
... ... @@ -4,10 +4,6 @@
4 4 F: board/samsung/smdk5420/
5 5 F: include/configs/peach-pit.h
6 6 F: configs/peach-pit_defconfig
7   -
8   -SMDK5420 BOARD
9   -M: Rajeshwari Shinde <rajeshwari.s@samsung.com>
10   -S: Maintained
11 7 F: include/configs/smdk5420.h
12 8 F: configs/smdk5420_defconfig
configs/s5p_goni_defconfig
Diff comments   View file @ ebf8644
1 1 CONFIG_ARM=y
  2 +CONFIG_ARCH_S5PC1XX=y
2 3 CONFIG_TARGET_S5P_GONI=y
  4 +CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-goni"
configs/smdkc100_defconfig
Diff comments   View file @ ebf8644
1 1 CONFIG_ARM=y
2 2 CONFIG_TARGET_SMDKC100=y
  3 +CONFIG_ARCH_S5PC1XX=y
  4 +CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100"
configs/smdkv310_defconfig
Diff comments   View file @ ebf8644
... ... @@ -2,4 +2,5 @@
2 2 +S:CONFIG_ARM=y
3 3 +S:CONFIG_ARCH_EXYNOS=y
4 4 +S:CONFIG_TARGET_SMDKV310=y
  5 +CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310"
drivers/mmc/s5p_sdhci.c
Diff comments   View file @ ebf8644
... ... @@ -14,9 +14,7 @@
14 14 #include <asm/arch/mmc.h>
15 15 #include <asm/arch/clk.h>
16 16 #include <errno.h>
17   -#ifdef CONFIG_OF_CONTROL
18 17 #include <asm/arch/pinmux.h>
19   -#endif
20 18  
21 19 static char *S5P_NAME = "SAMSUNG SDHCI";
22 20 static void s5p_sdhci_set_control_reg(struct sdhci_host *host)
drivers/power/pmic/Makefile
Diff comments   View file @ ebf8644
... ... @@ -11,7 +11,8 @@
11 11 obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
12 12 obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
13 13 obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
14   -obj-$(CONFIG_POWER_TPS65090) += pmic_tps65090.o
  14 +obj-$(CONFIG_POWER_TPS65090_I2C) += pmic_tps65090.o
  15 +obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o
15 16 obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
16 17 obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
17 18 obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
drivers/power/pmic/pmic_tps65090_ec.c
Diff comments   View file @ ebf8644
  1 +/*
  2 + * Copyright (c) 2013 The Chromium OS Authors.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <cros_ec.h>
  9 +#include <errno.h>
  10 +#include <power/tps65090_pmic.h>
  11 +
  12 +DECLARE_GLOBAL_DATA_PTR;
  13 +
  14 +#define TPS65090_ADDR 0x48
  15 +
  16 +static struct tps65090 {
  17 + struct cros_ec_dev *dev; /* The CROS_EC device */
  18 +} config;
  19 +
  20 +/* TPS65090 register addresses */
  21 +enum {
  22 + REG_IRQ1 = 0,
  23 + REG_CG_CTRL0 = 4,
  24 + REG_CG_STATUS1 = 0xa,
  25 + REG_FET1_CTRL = 0x0f,
  26 + REG_FET2_CTRL,
  27 + REG_FET3_CTRL,
  28 + REG_FET4_CTRL,
  29 + REG_FET5_CTRL,
  30 + REG_FET6_CTRL,
  31 + REG_FET7_CTRL,
  32 + TPS65090_NUM_REGS,
  33 +};
  34 +
  35 +enum {
  36 + IRQ1_VBATG = 1 << 3,
  37 + CG_CTRL0_ENC_MASK = 0x01,
  38 +
  39 + MAX_FET_NUM = 7,
  40 + MAX_CTRL_READ_TRIES = 5,
  41 +
  42 + /* TPS65090 FET_CTRL register values */
  43 + FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */
  44 + FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */
  45 + FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */
  46 + FET_CTRL_ADENFET = 1 << 1, /* Enable output auto discharge */
  47 + FET_CTRL_ENFET = 1 << 0, /* Enable FET */
  48 +};
  49 +
  50 +/**
  51 + * tps65090_read - read a byte from tps6090
  52 + *
  53 + * @param reg The register address to read from.
  54 + * @param val We'll return value value read here.
  55 + * @return 0 if ok; error if EC returns failure.
  56 + */
  57 +static int tps65090_read(u32 reg, u8 *val)
  58 +{
  59 + return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1,
  60 + val, 1, true);
  61 +}
  62 +
  63 +/**
  64 + * tps65090_write - write a byte to tps6090
  65 + *
  66 + * @param reg The register address to write to.
  67 + * @param val The value to write.
  68 + * @return 0 if ok; error if EC returns failure.
  69 + */
  70 +static int tps65090_write(u32 reg, u8 val)
  71 +{
  72 + return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1,
  73 + &val, 1, false);
  74 +}
  75 +
  76 +/**
  77 + * Checks for a valid FET number
  78 + *
  79 + * @param fet_id FET number to check
  80 + * @return 0 if ok, -EINVAL if FET value is out of range
  81 + */
  82 +static int tps65090_check_fet(unsigned int fet_id)
  83 +{
  84 + if (fet_id == 0 || fet_id > MAX_FET_NUM) {
  85 + debug("parameter fet_id is out of range, %u not in 1 ~ %u\n",
  86 + fet_id, MAX_FET_NUM);
  87 + return -EINVAL;
  88 + }
  89 +
  90 + return 0;
  91 +}
  92 +
  93 +/**
  94 + * Set the power state for a FET
  95 + *
  96 + * @param fet_id Fet number to set (1..MAX_FET_NUM)
  97 + * @param set 1 to power on FET, 0 to power off
  98 + * @return -EIO if we got a comms error, -EAGAIN if the FET failed to
  99 + * change state. If all is ok, returns 0.
  100 + */
  101 +static int tps65090_fet_set(int fet_id, bool set)
  102 +{
  103 + int retry;
  104 + u8 reg, value;
  105 +
  106 + value = FET_CTRL_ADENFET | FET_CTRL_WAIT;
  107 + if (set)
  108 + value |= FET_CTRL_ENFET;
  109 +
  110 + if (tps65090_write(REG_FET1_CTRL + fet_id - 1, value))
  111 + return -EIO;
  112 +
  113 + /* Try reading until we get a result */
  114 + for (retry = 0; retry < MAX_CTRL_READ_TRIES; retry++) {
  115 + if (tps65090_read(REG_FET1_CTRL + fet_id - 1, &reg))
  116 + return -EIO;
  117 +
  118 + /* Check that the fet went into the expected state */
  119 + if (!!(reg & FET_CTRL_PGFET) == set)
  120 + return 0;
  121 +
  122 + /* If we got a timeout, there is no point in waiting longer */
  123 + if (reg & FET_CTRL_TOFET)
  124 + break;
  125 +
  126 + mdelay(1);
  127 + }
  128 +
  129 + debug("FET %d: Power good should have set to %d but reg=%#02x\n",
  130 + fet_id, set, reg);
  131 + return -EAGAIN;
  132 +}
  133 +
  134 +int tps65090_fet_enable(unsigned int fet_id)
  135 +{
  136 + ulong start;
  137 + int loops;
  138 + int ret;
  139 +
  140 + ret = tps65090_check_fet(fet_id);
  141 + if (ret)
  142 + return ret;
  143 +
  144 + start = get_timer(0);
  145 + for (loops = 0;; loops++) {
  146 + ret = tps65090_fet_set(fet_id, true);
  147 + if (!ret)
  148 + break;
  149 +
  150 + if (get_timer(start) > 100)
  151 + break;
  152 +
  153 + /* Turn it off and try again until we time out */
  154 + tps65090_fet_set(fet_id, false);
  155 + }
  156 +
  157 + if (ret) {
  158 + debug("%s: FET%d failed to power on: time=%lums, loops=%d\n",
  159 + __func__, fet_id, get_timer(start), loops);
  160 + } else if (loops) {
  161 + debug("%s: FET%d powered on after %lums, loops=%d\n",
  162 + __func__, fet_id, get_timer(start), loops);
  163 + }
  164 + /*
  165 + * Unfortunately, there are some conditions where the power
  166 + * good bit will be 0, but the fet still comes up. One such
  167 + * case occurs with the lcd backlight. We'll just return 0 here
  168 + * and assume that the fet will eventually come up.
  169 + */
  170 + if (ret == -EAGAIN)
  171 + ret = 0;
  172 +
  173 + return ret;
  174 +}
  175 +
  176 +int tps65090_fet_disable(unsigned int fet_id)
  177 +{
  178 + int ret;
  179 +
  180 + ret = tps65090_check_fet(fet_id);
  181 + if (ret)
  182 + return ret;
  183 +
  184 + ret = tps65090_fet_set(fet_id, false);
  185 +
  186 + return ret;
  187 +}
  188 +
  189 +int tps65090_fet_is_enabled(unsigned int fet_id)
  190 +{
  191 + u8 reg = 0;
  192 + int ret;
  193 +
  194 + ret = tps65090_check_fet(fet_id);
  195 + if (ret)
  196 + return ret;
  197 + ret = tps65090_read(REG_FET1_CTRL + fet_id - 1, &reg);
  198 + if (ret) {
  199 + debug("fail to read FET%u_CTRL register over I2C", fet_id);
  200 + return -EIO;
  201 + }
  202 +
  203 + return reg & FET_CTRL_ENFET;
  204 +}
  205 +
  206 +int tps65090_init(void)
  207 +{
  208 + puts("TPS65090 PMIC EC init\n");
  209 +
  210 + config.dev = board_get_cros_ec_dev();
  211 + if (!config.dev) {
  212 + debug("%s: no cros_ec device: cannot init tps65090\n",
  213 + __func__);
  214 + return -ENODEV;
  215 + }
  216 +
  217 + return 0;
  218 +}
include/configs/arndale.h
Diff comments   View file @ ebf8644
... ... @@ -9,109 +9,19 @@
9 9 #ifndef __CONFIG_ARNDALE_H
10 10 #define __CONFIG_ARNDALE_H
11 11  
12   -/* High Level Configuration Options */
13   -#define CONFIG_SAMSUNG /* in a SAMSUNG core */
14   -#define CONFIG_S5P /* S5P Family */
15   -#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
16   -#define CONFIG_EXYNOS5250
  12 +#include "exynos5250-common.h"
17 13  
18   -#include <asm/arch/cpu.h> /* get chip and board defs */
19   -
20   -#define CONFIG_SYS_GENERIC_BOARD
21   -#define CONFIG_ARCH_CPU_INIT
22   -#define CONFIG_DISPLAY_CPUINFO
23   -#define CONFIG_DISPLAY_BOARDINFO
24   -
25   -
26   -/* Allow tracing to be enabled */
27   -#define CONFIG_TRACE
28   -#define CONFIG_CMD_TRACE
29   -#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
30   -#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
31   -#define CONFIG_TRACE_EARLY
32   -#define CONFIG_TRACE_EARLY_ADDR 0x50000000
33   -
34   -/* Keep L2 Cache Disabled */
35   -#define CONFIG_SYS_DCACHE_OFF
36   -
37   -#define CONFIG_SYS_SDRAM_BASE 0x40000000
38   -#define CONFIG_SYS_TEXT_BASE 0x43E00000
39   -
40   -/* input clock of PLL: SMDK5250 has 24MHz input clock */
41   -#define CONFIG_SYS_CLK_FREQ 24000000
42   -
43   -#define CONFIG_SETUP_MEMORY_TAGS
44   -#define CONFIG_CMDLINE_TAG
45   -#define CONFIG_INITRD_TAG
46   -#define CONFIG_CMDLINE_EDITING
47   -
48   -/* Power Down Modes */
49   -#define S5P_CHECK_SLEEP 0x00000BAD
50   -#define S5P_CHECK_DIDLE 0xBAD00000
51   -#define S5P_CHECK_LPA 0xABAD0000
52   -
53   -/* Offset for inform registers */
54   -#define INFORM0_OFFSET 0x800
55   -#define INFORM1_OFFSET 0x804
56   -
57   -/* Size of malloc() pool */
58   -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
59   -
60   -/* select serial console configuration */
61   -#define CONFIG_BAUDRATE 115200
62   -#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
63   -#define CONFIG_SILENT_CONSOLE
64   -
65   -/* Console configuration */
66   -#define CONFIG_CONSOLE_MUX
67   -#define CONFIG_SYS_CONSOLE_IS_IN_ENV
68   -#define EXYNOS_DEVICE_SETTINGS \
69   - "stdin=serial\0" \
70   - "stdout=serial\0" \
71   - "stderr=serial\0"
72   -
73   -#define CONFIG_EXTRA_ENV_SETTINGS \
74   - EXYNOS_DEVICE_SETTINGS
75   -
76 14 /* SD/MMC configuration */
77   -#define CONFIG_GENERIC_MMC
78   -#define CONFIG_MMC
79   -#define CONFIG_SDHCI
80   -#define CONFIG_S5P_SDHCI
81   -#define CONFIG_DWMMC
82   -#define CONFIG_EXYNOS_DWMMC
83 15 #define CONFIG_SUPPORT_EMMC_BOOT
84   -#define CONFIG_BOUNCE_BUFFER
85 16  
86   -
87   -#define CONFIG_BOARD_EARLY_INIT_F
88   -#define CONFIG_SKIP_LOWLEVEL_INIT
89   -
90   -/* PWM */
91   -#define CONFIG_PWM
92   -
93 17 /* allow to overwrite serial and ethaddr */
94 18 #define CONFIG_ENV_OVERWRITE
95 19  
96   -/* Command definition*/
97   -#include <config_cmd_default.h>
98   -
99   -#define CONFIG_CMD_PING
100   -#define CONFIG_CMD_ELF
101   -#define CONFIG_CMD_MMC
102 20 #define CONFIG_CMD_EXT2
103   -#define CONFIG_CMD_FAT
104   -#define CONFIG_CMD_NET
105   -#define CONFIG_CMD_HASH
106 21  
107   -#define CONFIG_BOOTDELAY 3
108   -#define CONFIG_ZERO_BOOTDELAY_CHECK
109   -
110 22 /* USB */
111   -#define CONFIG_CMD_USB
112 23 #define CONFIG_USB_EHCI
113 24 #define CONFIG_USB_EHCI_EXYNOS
114   -#define CONFIG_USB_STORAGE
115 25  
116 26 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
117 27 #define CONFIG_USB_HOST_ETHER
118 28  
119 29  
120 30  
121 31  
122 32  
123 33  
124 34  
125 35  
126 36  
127 37  
128 38  
... ... @@ -119,106 +29,23 @@
119 29  
120 30 /* MMC SPL */
121 31 #define CONFIG_EXYNOS_SPL
122   -#define COPY_BL2_FNPTR_ADDR 0x02020030
123 32  
124   -#define CONFIG_SPL_LIBCOMMON_SUPPORT
125   -
126   -/* specific .lds file */
127   -#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
128   -#define CONFIG_SPL_TEXT_BASE 0x02023400
129   -#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
130   -
131   -#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
132   -
133 33 /* Miscellaneous configurable options */
134   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
135   -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
136 34 #define CONFIG_SYS_PROMPT "ARNDALE # "
137   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
138   -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
139   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
140 35 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
141   -/* Boot Argument Buffer Size */
142   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
143   -/* memtest works on */
144   -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
145   -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
146   -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
147 36  
148   -#define CONFIG_RD_LVL
149   -
150 37 #define CONFIG_NR_DRAM_BANKS 8
151 38 #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
152   -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
153   -#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
154   -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
155   -#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
156   -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
157   -#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
158   -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
159   -#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
160   -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
161   -#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
162   -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
163   -#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
164   -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
165   -#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
166   -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
167   -#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
168 39  
169   -#define CONFIG_SYS_MONITOR_BASE 0x00000000
170   -
171   -/* FLASH and environment organization */
172   -#define CONFIG_SYS_NO_FLASH
173   -#undef CONFIG_CMD_IMLS
174 40 #define CONFIG_IDENT_STRING " for ARNDALE"
175 41  
176   -#define CONFIG_SYS_MMC_ENV_DEV 0
177   -
178 42 #define CONFIG_ENV_IS_IN_MMC
179   -#define CONFIG_SECURE_BL1_ONLY
180   -
181   -/* Secure FW size configuration */
182   -#ifdef CONFIG_SECURE_BL1_ONLY
183   -#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
184   -#else
185   -#define CONFIG_SEC_FW_SIZE 0
186   -#endif
187   -
188   -/* Configuration of BL1, BL2, ENV Blocks on mmc */
189   -#define CONFIG_RES_BLOCK_SIZE (512)
190   -#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
191   -#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
192   -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
193   -
194   -#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
195   -#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
196 43 #define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
197 44  
198   -/* U-boot copy size from boot Media to DRAM.*/
199   -#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
200   -#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
201   -
202   -#define CONFIG_DOS_PARTITION
203   -#define CONFIG_EFI_PARTITION
204   -#define CONFIG_CMD_PART
205   -#define CONFIG_PARTITION_UUIDS
206   -
207   -
208 45 #define CONFIG_IRAM_STACK 0x02050000
209 46  
210 47 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK
211 48  
212   -/* I2C */
213   -#define CONFIG_SYS_I2C_INIT_BOARD
214   -#define CONFIG_SYS_I2C
215   -#define CONFIG_CMD_I2C
216   -#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
217   -#define CONFIG_SYS_I2C_S3C24X0
218   -#define CONFIG_MAX_I2C_NUM 8
219   -#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
220   -#define CONFIG_I2C_EDID
221   -
222 49 /* PMIC */
223 50 #define CONFIG_PMIC
224 51 #define CONFIG_POWER_I2C
... ... @@ -226,26 +53,6 @@
226 53  
227 54  
228 55 #define CONFIG_PREBOOT
229   -
230   -/* Ethernet Controllor Driver */
231   -#ifdef CONFIG_CMD_NET
232   -#define CONFIG_SMC911X
233   -#define CONFIG_SMC911X_BASE 0x5000000
234   -#define CONFIG_SMC911X_16_BIT
235   -#define CONFIG_ENV_SROM_BANK 1
236   -#endif /*CONFIG_CMD_NET*/
237   -
238   -/* Enable PXE Support */
239   -#ifdef CONFIG_CMD_NET
240   -#define CONFIG_CMD_PXE
241   -#define CONFIG_MENU
242   -#endif
243   -
244   -/* Enable devicetree support */
245   -#define CONFIG_OF_LIBFDT
246   -
247   -/* Enable Time Command */
248   -#define CONFIG_CMD_TIME
249 56  
250 57 #define CONFIG_S5P_PA_SYSRAM 0x02020000
251 58 #define CONFIG_SMP_PEN_ADDR CONFIG_S5P_PA_SYSRAM
include/configs/exynos-common.h
Diff comments   View file @ ebf8644
  1 +/*
  2 + * Copyright (C) 2013 Samsung Electronics
  3 + *
  4 + * Common configuration settings for the SAMSUNG EXYNOS boards.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __EXYNOS_COMMON_H
  10 +#define __EXYNOS_COMMON_H
  11 +
  12 +/* High Level Configuration Options */
  13 +#define CONFIG_SAMSUNG /* in a SAMSUNG core */
  14 +#define CONFIG_S5P /* S5P Family */
  15 +
  16 +#include <asm/arch/cpu.h> /* get chip and board defs */
  17 +#include <linux/sizes.h>
  18 +
  19 +#define CONFIG_SYS_GENERIC_BOARD
  20 +#define CONFIG_ARCH_CPU_INIT
  21 +#define CONFIG_DISPLAY_CPUINFO
  22 +#define CONFIG_DISPLAY_BOARDINFO
  23 +#define CONFIG_SKIP_LOWLEVEL_INIT
  24 +#define CONFIG_BOARD_EARLY_INIT_F
  25 +
  26 +/* Enable fdt support */
  27 +#define CONFIG_OF_LIBFDT
  28 +
  29 +/* Keep L2 Cache Disabled */
  30 +#define CONFIG_CMD_CACHE
  31 +
  32 +/* input clock of PLL: 24MHz input clock */
  33 +#define CONFIG_SYS_CLK_FREQ 24000000
  34 +
  35 +#define CONFIG_SETUP_MEMORY_TAGS
  36 +#define CONFIG_CMDLINE_TAG
  37 +#define CONFIG_INITRD_TAG
  38 +#define CONFIG_CMDLINE_EDITING
  39 +#define CONFIG_ENV_OVERWRITE
  40 +
  41 +/* Size of malloc() pool before and after relocation */
  42 +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
  43 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20))
  44 +
  45 +/* select serial console configuration */
  46 +#define CONFIG_BAUDRATE 115200
  47 +
  48 +/* SD/MMC configuration */
  49 +#define CONFIG_GENERIC_MMC
  50 +#define CONFIG_MMC
  51 +#define CONFIG_S5P_SDHCI
  52 +#define CONFIG_SDHCI
  53 +#define CONFIG_DWMMC
  54 +#define CONFIG_EXYNOS_DWMMC
  55 +#define CONFIG_BOUNCE_BUFFER
  56 +
  57 +#define CONFIG_BOOTDELAY 3
  58 +#define CONFIG_ZERO_BOOTDELAY_CHECK
  59 +
  60 +/* PWM */
  61 +#define CONFIG_PWM
  62 +
  63 +/* Command definition*/
  64 +#include <config_cmd_default.h>
  65 +
  66 +#define CONFIG_CMD_MMC
  67 +#define CONFIG_CMD_EXT4
  68 +#define CONFIG_CMD_EXT4_WRITE
  69 +#define CONFIG_CMD_FAT
  70 +#define CONFIG_FAT_WRITE
  71 +
  72 +#define CONFIG_DOS_PARTITION
  73 +#define CONFIG_EFI_PARTITION
  74 +#define CONFIG_CMD_PART
  75 +#define CONFIG_PARTITION_UUIDS
  76 +
  77 +/* Miscellaneous configurable options */
  78 +#define CONFIG_SYS_LONGHELP /* undef to save memory */
  79 +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  80 +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  81 +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
  82 +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  83 +
  84 +/* Boot Argument Buffer Size */
  85 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  86 +
  87 +/* FLASH and environment organization */
  88 +#define CONFIG_SYS_NO_FLASH
  89 +#undef CONFIG_CMD_IMLS
  90 +
  91 +#endif /* __CONFIG_H */
include/configs/exynos4-common.h
Diff comments   View file @ ebf8644
  1 +/*
  2 + * Copyright (C) 2014 Samsung Electronics
  3 + *
  4 + * Configuration settings for the SAMSUNG EXYNOS5 board.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __CONFIG_EXYNOS4_COMMON_H
  10 +#define __CONFIG_EXYNOS4_COMMON_H
  11 +
  12 +#define CONFIG_EXYNOS4 /* Exynos4 Family */
  13 +
  14 +#include "exynos-common.h"
  15 +
  16 +#define CONFIG_BOARD_COMMON
  17 +
  18 +#define CONFIG_SYS_CACHELINE_SIZE 32
  19 +#define CONFIG_REVISION_TAG
  20 +
  21 +/* SD/MMC configuration */
  22 +#define CONFIG_MMC_SDMA
  23 +#define CONFIG_MMC_DEFAULT_DEV 0
  24 +
  25 +#undef CONFIG_CMD_FPGA
  26 +#undef CONFIG_CMD_MISC
  27 +#undef CONFIG_CMD_NET
  28 +#undef CONFIG_CMD_NFS
  29 +#undef CONFIG_CMD_XIMG
  30 +#undef CONFIG_CMD_ONENAND
  31 +#undef CONFIG_CMD_MTDPARTS
  32 +#define CONFIG_CMD_DFU
  33 +#define CONFIG_CMD_GPT
  34 +#define CONFIG_CMD_PMIC
  35 +#define CONFIG_CMD_SETEXPR
  36 +
  37 +/* USB Composite download gadget - g_dnl */
  38 +#define CONFIG_USBDOWNLOAD_GADGET
  39 +
  40 +/* TIZEN THOR downloader support */
  41 +#define CONFIG_CMD_THOR_DOWNLOAD
  42 +#define CONFIG_THOR_FUNCTION
  43 +
  44 +#define CONFIG_DFU_FUNCTION
  45 +#define CONFIG_DFU_MMC
  46 +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
  47 +#define DFU_DEFAULT_POLL_TIMEOUT 300
  48 +
  49 +/* USB Samsung's IDs */
  50 +#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
  51 +#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
  52 +#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
  53 +#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
  54 +#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
  55 +#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
  56 +#define CONFIG_G_DNL_MANUFACTURER "Samsung"
  57 +
  58 +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
  59 +
  60 +#define CONFIG_USB_GADGET
  61 +#define CONFIG_USB_GADGET_S3C_UDC_OTG
  62 +#define CONFIG_USB_GADGET_DUALSPEED
  63 +#define CONFIG_USB_GADGET_VBUS_DRAW 2
  64 +
  65 +#define CONFIG_CMD_USB_MASS_STORAGE
  66 +#define CONFIG_USB_GADGET_MASS_STORAGE
  67 +
  68 +#endif /* __CONFIG_EXYNOS4_COMMON_H */
include/configs/exynos4-dt.h
View file @ ebf8644
1   -/*
2   - * Copyright (C) 2014 Samsung Electronics
3   - *
4   - * Configuration settings for the SAMSUNG EXYNOS5 board.
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#ifndef __CONFIG_H
10   -#define __CONFIG_H
11   -
12   -/* High Level Configuration Options */
13   -#define CONFIG_SAMSUNG /* in a SAMSUNG core */
14   -#define CONFIG_S5P /* S5P Family */
15   -#define CONFIG_EXYNOS4 /* which is in a Exynos4 Family */
16   -
17   -#include <asm/arch/cpu.h> /* get chip and board defs */
18   -
19   -#define CONFIG_ARCH_CPU_INIT
20   -#define CONFIG_DISPLAY_CPUINFO
21   -#define CONFIG_DISPLAY_BOARDINFO
22   -#define CONFIG_BOARD_COMMON
23   -#define CONFIG_SYS_GENERIC_BOARD
24   -
25   -#define CONFIG_SYS_CACHELINE_SIZE 32
26   -
27   -/* input clock of PLL: EXYNOS4 boards have 24MHz input clock */
28   -#define CONFIG_SYS_CLK_FREQ 24000000
29   -
30   -#define CONFIG_SETUP_MEMORY_TAGS
31   -#define CONFIG_CMDLINE_TAG
32   -#define CONFIG_REVISION_TAG
33   -#define CONFIG_INITRD_TAG
34   -#define CONFIG_CMDLINE_EDITING
35   -
36   -#include <linux/sizes.h>
37   -
38   -/* SD/MMC configuration */
39   -#define CONFIG_GENERIC_MMC
40   -#define CONFIG_MMC
41   -#define CONFIG_S5P_SDHCI
42   -#define CONFIG_SDHCI
43   -#define CONFIG_MMC_SDMA
44   -#define CONFIG_DWMMC
45   -#define CONFIG_EXYNOS_DWMMC
46   -#define CONFIG_BOUNCE_BUFFER
47   -#define CONFIG_MMC_DEFAULT_DEV 0
48   -
49   -/* PWM */
50   -#define CONFIG_PWM
51   -
52   -#define CONFIG_BOARD_EARLY_INIT_F
53   -#define CONFIG_SKIP_LOWLEVEL_INIT
54   -
55   -/* allow to overwrite serial and ethaddr */
56   -#define CONFIG_ENV_OVERWRITE
57   -
58   -/* Command definition*/
59   -#include <config_cmd_default.h>
60   -
61   -#undef CONFIG_CMD_FPGA
62   -#undef CONFIG_CMD_MISC
63   -#undef CONFIG_CMD_NET
64   -#undef CONFIG_CMD_NFS
65   -#undef CONFIG_CMD_XIMG
66   -#undef CONFIG_CMD_CACHE
67   -#undef CONFIG_CMD_ONENAND
68   -#undef CONFIG_CMD_MTDPARTS
69   -#define CONFIG_CMD_CACHE
70   -#define CONFIG_CMD_MMC
71   -#define CONFIG_CMD_DFU
72   -#define CONFIG_CMD_GPT
73   -#define CONFIG_CMD_PMIC
74   -#define CONFIG_CMD_SETEXPR
75   -
76   -#define CONFIG_BOOTDELAY 3
77   -#define CONFIG_ZERO_BOOTDELAY_CHECK
78   -
79   -/* FAT */
80   -#define CONFIG_CMD_FAT
81   -#define CONFIG_FAT_WRITE
82   -
83   -/* EXT4 */
84   -#define CONFIG_CMD_EXT4
85   -#define CONFIG_CMD_EXT4_WRITE
86   -
87   -/* USB Composite download gadget - g_dnl */
88   -#define CONFIG_USBDOWNLOAD_GADGET
89   -
90   -/* TIZEN THOR downloader support */
91   -#define CONFIG_CMD_THOR_DOWNLOAD
92   -#define CONFIG_THOR_FUNCTION
93   -
94   -#define CONFIG_DFU_FUNCTION
95   -#define CONFIG_DFU_MMC
96   -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
97   -#define DFU_DEFAULT_POLL_TIMEOUT 300
98   -
99   -/* USB Samsung's IDs */
100   -#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
101   -#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
102   -#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
103   -#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
104   -#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
105   -#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
106   -#define CONFIG_G_DNL_MANUFACTURER "Samsung"
107   -
108   -/* Miscellaneous configurable options */
109   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
110   -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
111   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
112   -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
113   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
114   -/* Boot Argument Buffer Size */
115   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
116   -
117   -/* FLASH and environment organization */
118   -#define CONFIG_SYS_NO_FLASH
119   -#undef CONFIG_CMD_IMLS
120   -
121   -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
122   -
123   -#define CONFIG_DOS_PARTITION
124   -#define CONFIG_EFI_PARTITION
125   -#define CONFIG_CMD_PART
126   -#define CONFIG_PARTITION_UUIDS
127   -
128   -#define CONFIG_USB_GADGET
129   -#define CONFIG_USB_GADGET_S3C_UDC_OTG
130   -#define CONFIG_USB_GADGET_DUALSPEED
131   -#define CONFIG_USB_GADGET_VBUS_DRAW 2
132   -
133   -#define CONFIG_CMD_USB_MASS_STORAGE
134   -#define CONFIG_USB_GADGET_MASS_STORAGE
135   -
136   -/* Enable devicetree support */
137   -#define CONFIG_OF_LIBFDT
138   -
139   -#endif /* __CONFIG_H */
include/configs/exynos5-common.h
Diff comments   View file @ ebf8644
  1 +/*
  2 + * Copyright (C) 2013 Samsung Electronics
  3 + *
  4 + * Configuration settings for the SAMSUNG EXYNOS5 board.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __CONFIG_EXYNOS5_COMMON_H
  10 +#define __CONFIG_EXYNOS5_COMMON_H
  11 +
  12 +#define CONFIG_EXYNOS5 /* Exynos5 Family */
  13 +
  14 +#include "exynos-common.h"
  15 +
  16 +#define CONFIG_SYS_CACHELINE_SIZE 64
  17 +#define CONFIG_EXYNOS_SPL
  18 +
  19 +/* Allow tracing to be enabled */
  20 +#define CONFIG_TRACE
  21 +#define CONFIG_CMD_TRACE
  22 +#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
  23 +#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
  24 +#define CONFIG_TRACE_EARLY
  25 +#define CONFIG_TRACE_EARLY_ADDR 0x50000000
  26 +
  27 +
  28 +/* Enable ACE acceleration for SHA1 and SHA256 */
  29 +#define CONFIG_EXYNOS_ACE_SHA
  30 +#define CONFIG_SHA_HW_ACCEL
  31 +
  32 +/* Power Down Modes */
  33 +#define S5P_CHECK_SLEEP 0x00000BAD
  34 +#define S5P_CHECK_DIDLE 0xBAD00000
  35 +#define S5P_CHECK_LPA 0xABAD0000
  36 +
  37 +/* Offset for inform registers */
  38 +#define INFORM0_OFFSET 0x800
  39 +#define INFORM1_OFFSET 0x804
  40 +#define INFORM2_OFFSET 0x808
  41 +#define INFORM3_OFFSET 0x80c
  42 +
  43 +/* select serial console configuration */
  44 +#define CONFIG_BAUDRATE 115200
  45 +#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
  46 +#define CONFIG_SILENT_CONSOLE
  47 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
  48 +#define CONFIG_CONSOLE_MUX
  49 +
  50 +#define EXYNOS_DEVICE_SETTINGS \
  51 + "stdin=serial\0" \
  52 + "stdout=serial\0" \
  53 + "stderr=serial\0"
  54 +
  55 +#define CONFIG_EXTRA_ENV_SETTINGS \
  56 + EXYNOS_DEVICE_SETTINGS
  57 +
  58 +#define CONFIG_CMD_PING
  59 +#define CONFIG_CMD_ELF
  60 +#define CONFIG_CMD_NET
  61 +#define CONFIG_CMD_HASH
  62 +
  63 +/* Thermal Management Unit */
  64 +#define CONFIG_EXYNOS_TMU
  65 +#define CONFIG_CMD_DTT
  66 +#define CONFIG_TMU_CMD_DTT
  67 +
  68 +/* TPM */
  69 +#define CONFIG_TPM
  70 +#define CONFIG_CMD_TPM
  71 +#define CONFIG_TPM_TIS_I2C
  72 +#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3
  73 +#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20
  74 +
  75 +/* MMC SPL */
  76 +#define COPY_BL2_FNPTR_ADDR 0x02020030
  77 +#define CONFIG_SUPPORT_EMMC_BOOT
  78 +
  79 +#define CONFIG_SPL_LIBCOMMON_SUPPORT
  80 +#define CONFIG_SPL_GPIO_SUPPORT
  81 +
  82 +/* specific .lds file */
  83 +#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
  84 +
  85 +/* Boot Argument Buffer Size */
  86 +/* memtest works on */
  87 +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
  88 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
  89 +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
  90 +
  91 +#define CONFIG_RD_LVL
  92 +
  93 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
  94 +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
  95 +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
  96 +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
  97 +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
  98 +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
  99 +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
  100 +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
  101 +#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
  102 +#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
  103 +#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
  104 +#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
  105 +#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
  106 +#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
  107 +#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
  108 +#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
  109 +
  110 +#define CONFIG_SYS_MONITOR_BASE 0x00000000
  111 +
  112 +#define CONFIG_SYS_MMC_ENV_DEV 0
  113 +
  114 +#define CONFIG_SECURE_BL1_ONLY
  115 +
  116 +/* Secure FW size configuration */
  117 +#ifdef CONFIG_SECURE_BL1_ONLY
  118 +#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
  119 +#else
  120 +#define CONFIG_SEC_FW_SIZE 0
  121 +#endif
  122 +
  123 +/* Configuration of BL1, BL2, ENV Blocks on mmc */
  124 +#define CONFIG_RES_BLOCK_SIZE (512)
  125 +#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
  126 +#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
  127 +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
  128 +
  129 +#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
  130 +#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
  131 +
  132 +/* U-boot copy size from boot Media to DRAM.*/
  133 +#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
  134 +#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
  135 +
  136 +#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
  137 +#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
  138 +
  139 +/* I2C */
  140 +#define CONFIG_SYS_I2C_INIT_BOARD
  141 +#define CONFIG_SYS_I2C
  142 +#define CONFIG_CMD_I2C
  143 +#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
  144 +#define CONFIG_SYS_I2C_S3C24X0
  145 +#define CONFIG_I2C_MULTI_BUS
  146 +#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
  147 +#define CONFIG_I2C_EDID
  148 +
  149 +/* SPI */
  150 +#ifdef CONFIG_SPI_FLASH
  151 +#define CONFIG_EXYNOS_SPI
  152 +#define CONFIG_CMD_SF
  153 +#define CONFIG_CMD_SPI
  154 +#define CONFIG_SPI_FLASH_WINBOND
  155 +#define CONFIG_SPI_FLASH_GIGADEVICE
  156 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
  157 +#define CONFIG_SF_DEFAULT_SPEED 50000000
  158 +#define EXYNOS5_SPI_NUM_CONTROLLERS 5
  159 +#define CONFIG_OF_SPI
  160 +#endif
  161 +
  162 +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
  163 +#define CONFIG_ENV_SPI_MODE SPI_MODE_0
  164 +#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
  165 +#define CONFIG_ENV_SPI_BUS 1
  166 +#define CONFIG_ENV_SPI_MAX_HZ 50000000
  167 +#endif
  168 +
  169 +/* Ethernet Controllor Driver */
  170 +#ifdef CONFIG_CMD_NET
  171 +#define CONFIG_SMC911X
  172 +#define CONFIG_SMC911X_BASE 0x5000000
  173 +#define CONFIG_SMC911X_16_BIT
  174 +#define CONFIG_ENV_SROM_BANK 1
  175 +#endif /*CONFIG_CMD_NET*/
  176 +
  177 +/* Enable PXE Support */
  178 +#ifdef CONFIG_CMD_NET
  179 +#define CONFIG_CMD_PXE
  180 +#define CONFIG_MENU
  181 +#endif
  182 +
  183 +/* SHA hashing */
  184 +#define CONFIG_CMD_HASH
  185 +#define CONFIG_HASH_VERIFY
  186 +#define CONFIG_SHA1
  187 +#define CONFIG_SHA256
  188 +
  189 +/* Enable Time Command */
  190 +#define CONFIG_CMD_TIME
  191 +
  192 +#define CONFIG_CMD_BOOTZ
  193 +
  194 +#define CONFIG_CMD_GPIO
  195 +
  196 +/* USB boot mode */
  197 +#define CONFIG_USB_BOOTING
  198 +#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
  199 +#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
  200 +#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
  201 +
  202 +/* Enable FIT support and comparison */
  203 +#define CONFIG_FIT
  204 +#define CONFIG_FIT_BEST_MATCH
  205 +
  206 +#endif /* __CONFIG_EXYNOS5_COMMON_H */
include/configs/exynos5-dt-common.h
Diff comments   View file @ ebf8644
  1 +/*
  2 + * Copyright (C) 2014 Google, Inc
  3 + *
  4 + * Configuration settings for generic Exynos 5 board
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __CONFIG_EXYNOS5_DT_COMMON_H
  10 +#define __CONFIG_EXYNOS5_DT_COMMON_H
  11 +
  12 +#include "exynos5-common.h"
  13 +
  14 +/* PMIC */
  15 +#define CONFIG_POWER
  16 +#define CONFIG_POWER_I2C
  17 +#define CONFIG_POWER_TPS65090
  18 +
  19 +/* Enable keyboard */
  20 +#define CONFIG_CROS_EC /* CROS_EC protocol */
  21 +#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */
  22 +#define CONFIG_CMD_CROS_EC
  23 +#define CONFIG_KEYBOARD
  24 +
  25 +/* Console configuration */
  26 +#undef EXYNOS_DEVICE_SETTINGS
  27 +#define EXYNOS_DEVICE_SETTINGS \
  28 + "stdin=serial,cros-ec-keyb\0" \
  29 + "stdout=serial,lcd\0" \
  30 + "stderr=serial,lcd\0"
  31 +
  32 +#define CONFIG_EXTRA_ENV_SETTINGS \
  33 + EXYNOS_DEVICE_SETTINGS
  34 +
  35 +#endif
include/configs/exynos5-dt.h
View file @ ebf8644
1   -/*
2   - * Copyright (C) 2013 Samsung Electronics
3   - *
4   - * Configuration settings for the SAMSUNG EXYNOS5 board.
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#ifndef __CONFIG_H
10   -#define __CONFIG_H
11   -
12   -/* High Level Configuration Options */
13   -#define CONFIG_SAMSUNG /* in a SAMSUNG core */
14   -#define CONFIG_S5P /* S5P Family */
15   -#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
16   -
17   -#include <asm/arch/cpu.h> /* get chip and board defs */
18   -
19   -#define CONFIG_SYS_GENERIC_BOARD
20   -#define CONFIG_ARCH_CPU_INIT
21   -#define CONFIG_DISPLAY_CPUINFO
22   -#define CONFIG_DISPLAY_BOARDINFO
23   -#define CONFIG_BOARD_COMMON
24   -#define CONFIG_ARCH_EARLY_INIT_R
25   -#define CONFIG_EXYNOS_SPL
26   -
27   -/* Allow tracing to be enabled */
28   -#define CONFIG_TRACE
29   -#define CONFIG_CMD_TRACE
30   -#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
31   -#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
32   -#define CONFIG_TRACE_EARLY
33   -#define CONFIG_TRACE_EARLY_ADDR 0x50000000
34   -
35   -/* Keep L2 Cache Disabled */
36   -#define CONFIG_SYS_DCACHE_OFF
37   -#define CONFIG_SYS_CACHELINE_SIZE 64
38   -
39   -/* Enable ACE acceleration for SHA1 and SHA256 */
40   -#define CONFIG_EXYNOS_ACE_SHA
41   -#define CONFIG_SHA_HW_ACCEL
42   -
43   -/* input clock of PLL: SMDK5250 has 24MHz input clock */
44   -#define CONFIG_SYS_CLK_FREQ 24000000
45   -
46   -#define CONFIG_SETUP_MEMORY_TAGS
47   -#define CONFIG_CMDLINE_TAG
48   -#define CONFIG_INITRD_TAG
49   -#define CONFIG_CMDLINE_EDITING
50   -
51   -/* Power Down Modes */
52   -#define S5P_CHECK_SLEEP 0x00000BAD
53   -#define S5P_CHECK_DIDLE 0xBAD00000
54   -#define S5P_CHECK_LPA 0xABAD0000
55   -
56   -/* Offset for inform registers */
57   -#define INFORM0_OFFSET 0x800
58   -#define INFORM1_OFFSET 0x804
59   -#define INFORM2_OFFSET 0x808
60   -#define INFORM3_OFFSET 0x80c
61   -
62   -/* Size of malloc() pool */
63   -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
64   -
65   -/* select serial console configuration */
66   -#define CONFIG_BAUDRATE 115200
67   -#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
68   -#define CONFIG_SILENT_CONSOLE
69   -
70   -/* Enable keyboard */
71   -#define CONFIG_CROS_EC /* CROS_EC protocol */
72   -#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
73   -#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */
74   -#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */
75   -#define CONFIG_CMD_CROS_EC
76   -#define CONFIG_KEYBOARD
77   -
78   -/* Console configuration */
79   -#define CONFIG_CONSOLE_MUX
80   -#define CONFIG_SYS_CONSOLE_IS_IN_ENV
81   -#define EXYNOS_DEVICE_SETTINGS \
82   - "stdin=serial,cros-ec-keyb\0" \
83   - "stdout=serial,lcd\0" \
84   - "stderr=serial,lcd\0"
85   -
86   -#define CONFIG_EXTRA_ENV_SETTINGS \
87   - EXYNOS_DEVICE_SETTINGS
88   -
89   -/* SD/MMC configuration */
90   -#define CONFIG_GENERIC_MMC
91   -#define CONFIG_MMC
92   -#define CONFIG_SDHCI
93   -#define CONFIG_S5P_SDHCI
94   -#define CONFIG_DWMMC
95   -#define CONFIG_EXYNOS_DWMMC
96   -#define CONFIG_SUPPORT_EMMC_BOOT
97   -#define CONFIG_BOUNCE_BUFFER
98   -
99   -#define CONFIG_BOARD_EARLY_INIT_F
100   -#define CONFIG_SKIP_LOWLEVEL_INIT
101   -
102   -/* PWM */
103   -#define CONFIG_PWM
104   -
105   -/* allow to overwrite serial and ethaddr */
106   -#define CONFIG_ENV_OVERWRITE
107   -
108   -/* Command definition*/
109   -#include <config_cmd_default.h>
110   -
111   -#define CONFIG_CMD_PING
112   -#define CONFIG_CMD_ELF
113   -#define CONFIG_CMD_MMC
114   -#define CONFIG_CMD_EXT2
115   -#define CONFIG_CMD_FAT
116   -#define CONFIG_CMD_NET
117   -#define CONFIG_CMD_HASH
118   -
119   -#define CONFIG_BOOTDELAY 3
120   -#define CONFIG_ZERO_BOOTDELAY_CHECK
121   -
122   -/* Thermal Management Unit */
123   -#define CONFIG_EXYNOS_TMU
124   -#define CONFIG_CMD_DTT
125   -#define CONFIG_TMU_CMD_DTT
126   -
127   -/* TPM */
128   -#define CONFIG_TPM
129   -#define CONFIG_CMD_TPM
130   -#define CONFIG_TPM_TIS_I2C
131   -#define CONFIG_TPM_TIS_I2C_BUS_NUMBER 3
132   -#define CONFIG_TPM_TIS_I2C_SLAVE_ADDR 0x20
133   -
134   -/* MMC SPL */
135   -#define COPY_BL2_FNPTR_ADDR 0x02020030
136   -
137   -#define CONFIG_SPL_LIBCOMMON_SUPPORT
138   -#define CONFIG_SPL_GPIO_SUPPORT
139   -
140   -/* specific .lds file */
141   -#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
142   -
143   -/* Miscellaneous configurable options */
144   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
145   -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
146   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
147   -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
148   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
149   -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
150   -/* Boot Argument Buffer Size */
151   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
152   -/* memtest works on */
153   -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
154   -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
155   -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
156   -
157   -#define CONFIG_RD_LVL
158   -
159   -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
160   -#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
161   -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
162   -#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
163   -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
164   -#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
165   -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
166   -#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
167   -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
168   -#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
169   -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
170   -#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
171   -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
172   -#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
173   -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
174   -#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
175   -
176   -#define CONFIG_SYS_MONITOR_BASE 0x00000000
177   -
178   -/* FLASH and environment organization */
179   -#define CONFIG_SYS_NO_FLASH
180   -#undef CONFIG_CMD_IMLS
181   -
182   -#define CONFIG_SYS_MMC_ENV_DEV 0
183   -
184   -#define CONFIG_SECURE_BL1_ONLY
185   -
186   -/* Secure FW size configuration */
187   -#ifdef CONFIG_SECURE_BL1_ONLY
188   -#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
189   -#else
190   -#define CONFIG_SEC_FW_SIZE 0
191   -#endif
192   -
193   -/* Configuration of BL1, BL2, ENV Blocks on mmc */
194   -#define CONFIG_RES_BLOCK_SIZE (512)
195   -#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
196   -#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
197   -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
198   -
199   -#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
200   -#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
201   -
202   -/* Store environment at the end of a 4 MB SPI flash */
203   -#define FLASH_SIZE (0x4 << 20)
204   -#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
205   -
206   -/* U-boot copy size from boot Media to DRAM.*/
207   -#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
208   -#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
209   -
210   -#define CONFIG_SPI_BOOTING
211   -#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
212   -#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
213   -
214   -#define CONFIG_DOS_PARTITION
215   -#define CONFIG_EFI_PARTITION
216   -#define CONFIG_CMD_PART
217   -#define CONFIG_PARTITION_UUIDS
218   -
219   -/* I2C */
220   -#define CONFIG_SYS_I2C_INIT_BOARD
221   -#define CONFIG_SYS_I2C
222   -#define CONFIG_CMD_I2C
223   -#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */
224   -#define CONFIG_SYS_I2C_S3C24X0
225   -#define CONFIG_I2C_MULTI_BUS
226   -#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0
227   -#define CONFIG_I2C_EDID
228   -
229   -/* SPI */
230   -#define CONFIG_ENV_IS_IN_SPI_FLASH
231   -#define CONFIG_SPI_FLASH
232   -#define CONFIG_ENV_SPI_BASE 0x12D30000
233   -
234   -#ifdef CONFIG_SPI_FLASH
235   -#define CONFIG_EXYNOS_SPI
236   -#define CONFIG_CMD_SF
237   -#define CONFIG_CMD_SPI
238   -#define CONFIG_SPI_FLASH_WINBOND
239   -#define CONFIG_SPI_FLASH_GIGADEVICE
240   -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
241   -#define CONFIG_SF_DEFAULT_SPEED 50000000
242   -#define EXYNOS5_SPI_NUM_CONTROLLERS 5
243   -#define CONFIG_OF_SPI
244   -#endif
245   -
246   -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
247   -#define CONFIG_ENV_SPI_MODE SPI_MODE_0
248   -#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
249   -#define CONFIG_ENV_SPI_BUS 1
250   -#define CONFIG_ENV_SPI_MAX_HZ 50000000
251   -#endif
252   -
253   -/* PMIC */
254   -#define CONFIG_POWER
255   -#define CONFIG_POWER_I2C
256   -#define CONFIG_POWER_TPS65090
257   -
258   -/* Ethernet Controllor Driver */
259   -#ifdef CONFIG_CMD_NET
260   -#define CONFIG_SMC911X
261   -#define CONFIG_SMC911X_BASE 0x5000000
262   -#define CONFIG_SMC911X_16_BIT
263   -#define CONFIG_ENV_SROM_BANK 1
264   -#endif /*CONFIG_CMD_NET*/
265   -
266   -/* Enable PXE Support */
267   -#ifdef CONFIG_CMD_NET
268   -#define CONFIG_CMD_PXE
269   -#define CONFIG_MENU
270   -#endif
271   -
272   -/* Enable devicetree support */
273   -#define CONFIG_OF_LIBFDT
274   -
275   -/* SHA hashing */
276   -#define CONFIG_CMD_HASH
277   -#define CONFIG_HASH_VERIFY
278   -#define CONFIG_SHA1
279   -#define CONFIG_SHA256
280   -
281   -/* Enable Time Command */
282   -#define CONFIG_CMD_TIME
283   -
284   -#define CONFIG_CMD_BOOTZ
285   -
286   -#define CONFIG_CMD_GPIO
287   -
288   -/* USB boot mode */
289   -#define CONFIG_USB_BOOTING
290   -#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
291   -#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
292   -#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
293   -
294   -#endif /* __CONFIG_H */
include/configs/exynos5250-common.h
Diff comments   View file @ ebf8644
  1 +
  2 +/*
  3 + * Copyright (C) 2012 Samsung Electronics
  4 + *
  5 + * Configuration settings for the SAMSUNG EXYNOS5250 board.
  6 + *
  7 + * SPDX-License-Identifier: GPL-2.0+
  8 + */
  9 +
  10 +#ifndef __CONFIG_5250_H
  11 +#define __CONFIG_5250_H
  12 +
  13 +#include <configs/exynos5-common.h>
  14 +#define CONFIG_EXYNOS5250
  15 +
  16 +#define CONFIG_SYS_SDRAM_BASE 0x40000000
  17 +#define CONFIG_SYS_TEXT_BASE 0x43E00000
  18 +
  19 +/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
  20 +#define MACH_TYPE_SMDK5250 3774
  21 +#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250
  22 +
  23 +#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
  24 +
  25 +/* USB */
  26 +#define CONFIG_CMD_USB
  27 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
  28 +#define CONFIG_USB_STORAGE
  29 +
  30 +#define CONFIG_SPL_TEXT_BASE 0x02023400
  31 +
  32 +#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
  33 +
  34 +#define CONFIG_IRAM_STACK 0x02050000
  35 +
  36 +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK
  37 +
  38 +/* PMIC */
  39 +#define CONFIG_POWER_MAX77686
  40 +
  41 +/* Sound */
  42 +#define CONFIG_CMD_SOUND
  43 +#ifdef CONFIG_CMD_SOUND
  44 +#define CONFIG_SOUND
  45 +#define CONFIG_I2S_SAMSUNG
  46 +#define CONFIG_I2S
  47 +#define CONFIG_SOUND_MAX98095
  48 +#define CONFIG_SOUND_WM8994
  49 +#endif
  50 +
  51 +/* I2C */
  52 +#define CONFIG_MAX_I2C_NUM 8
  53 +
  54 +/* Display */
  55 +#define CONFIG_LCD
  56 +#ifdef CONFIG_LCD
  57 +#define CONFIG_EXYNOS_FB
  58 +#define CONFIG_EXYNOS_DP
  59 +#define LCD_BPP LCD_COLOR16
  60 +#endif
  61 +
  62 +/* DRAM Memory Banks */
  63 +#define CONFIG_NR_DRAM_BANKS 8
  64 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
  65 +
  66 +#endif /* __CONFIG_5250_H */
include/configs/exynos5250-dt.h
View file @ ebf8644
1   -
2   -/*
3   - * Copyright (C) 2012 Samsung Electronics
4   - *
5   - * Configuration settings for the SAMSUNG EXYNOS5250 board.
6   - *
7   - * SPDX-License-Identifier: GPL-2.0+
8   - */
9   -
10   -#ifndef __CONFIG_5250_H
11   -#define __CONFIG_5250_H
12   -
13   -#include <configs/exynos5-dt.h>
14   -#define CONFIG_EXYNOS5250
15   -
16   -#define CONFIG_SYS_SDRAM_BASE 0x40000000
17   -#define CONFIG_SYS_TEXT_BASE 0x43E00000
18   -
19   -/* MACH_TYPE_SMDK5250 macro will be removed once added to mach-types */
20   -#define MACH_TYPE_SMDK5250 3774
21   -#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250
22   -
23   -#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
24   -
25   -/* USB */
26   -#define CONFIG_CMD_USB
27   -#define CONFIG_USB_XHCI
28   -#define CONFIG_USB_XHCI_EXYNOS
29   -#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
30   -#define CONFIG_USB_STORAGE
31   -
32   -#define CONFIG_SPL_TEXT_BASE 0x02023400
33   -
34   -#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
35   -
36   -#define CONFIG_SYS_PROMPT "SMDK5250 # "
37   -#define CONFIG_IDENT_STRING " for SMDK5250"
38   -
39   -#define CONFIG_IRAM_STACK 0x02050000
40   -
41   -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK
42   -
43   -/* PMIC */
44   -#define CONFIG_POWER_MAX77686
45   -
46   -/* Sound */
47   -#define CONFIG_CMD_SOUND
48   -#ifdef CONFIG_CMD_SOUND
49   -#define CONFIG_SOUND
50   -#define CONFIG_I2S_SAMSUNG
51   -#define CONFIG_I2S
52   -#define CONFIG_SOUND_MAX98095
53   -#define CONFIG_SOUND_WM8994
54   -#endif
55   -
56   -/* I2C */
57   -#define CONFIG_MAX_I2C_NUM 8
58   -
59   -/* Display */
60   -#define CONFIG_LCD
61   -#ifdef CONFIG_LCD
62   -#define CONFIG_EXYNOS_FB
63   -#define CONFIG_EXYNOS_DP
64   -#define LCD_BPP LCD_COLOR16
65   -#endif
66   -
67   -/* DRAM Memory Banks */
68   -#define CONFIG_NR_DRAM_BANKS 8
69   -#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
70   -
71   -#endif /* __CONFIG_5250_H */
include/configs/exynos5420-common.h
Diff comments   View file @ ebf8644
  1 +/*
  2 + * Copyright (C) 2013 Samsung Electronics
  3 + *
  4 + * Configuration settings for the SAMSUNG EXYNOS5420 SoC
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __CONFIG_EXYNOS5420_H
  10 +#define __CONFIG_EXYNOS5420_H
  11 +
  12 +#define CONFIG_EXYNOS5420
  13 +
  14 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  15 +#define CONFIG_SPI_FLASH
  16 +#define CONFIG_ENV_SPI_BASE 0x12D30000
  17 +#define FLASH_SIZE (0x4 << 20)
  18 +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
  19 +#define CONFIG_SPI_BOOTING
  20 +
  21 +#include <configs/exynos5-common.h>
  22 +
  23 +#define CONFIG_ARCH_EARLY_INIT_R
  24 +
  25 +#define MACH_TYPE_SMDK5420 8002
  26 +#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420
  27 +
  28 +#define CONFIG_VAR_SIZE_SPL
  29 +
  30 +#define CONFIG_SYS_SDRAM_BASE 0x20000000
  31 +#define CONFIG_SYS_TEXT_BASE 0x23E00000
  32 +#ifdef CONFIG_VAR_SIZE_SPL
  33 +#define CONFIG_SPL_TEXT_BASE 0x02024410
  34 +#else
  35 +#define CONFIG_SPL_TEXT_BASE 0x02024400
  36 +#endif
  37 +#define CONFIG_IRAM_TOP 0x02074000
  38 +
  39 +#define CONFIG_SPL_MAX_FOOTPRINT (30 * 1024)
  40 +
  41 +#define CONFIG_DEVICE_TREE_LIST "exynos5420-peach-pit exynos5420-smdk5420"
  42 +
  43 +#define CONFIG_MAX_I2C_NUM 11
  44 +
  45 +#define CONFIG_BOARD_REV_GPIO_COUNT 2
  46 +
  47 +#define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000"
  48 +
  49 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
  50 +
  51 +/*
  52 + * Put the initial stack pointer 1KB below this to allow room for the
  53 + * SPL marker. This value is arbitrary, but gd_t is placed starting here.
  54 + */
  55 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800)
  56 +
  57 +/* DRAM Memory Banks */
  58 +#define CONFIG_NR_DRAM_BANKS 7
  59 +#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
  60 +
  61 +/* Miscellaneous configurable options */
  62 +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
  63 +
  64 +#endif /* __CONFIG_EXYNOS5420_H */
include/configs/exynos5420.h
View file @ ebf8644
1   -/*
2   - * Copyright (C) 2013 Samsung Electronics
3   - *
4   - * Configuration settings for the SAMSUNG EXYNOS5420 SoC
5   - *
6   - * SPDX-License-Identifier: GPL-2.0+
7   - */
8   -
9   -#ifndef __CONFIG_EXYNOS5420_H
10   -#define __CONFIG_EXYNOS5420_H
11   -
12   -#define CONFIG_EXYNOS5420 /* which is in a Exynos5 Family */
13   -
14   -#define MACH_TYPE_SMDK5420 8002
15   -#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420
16   -
17   -#define CONFIG_VAR_SIZE_SPL
18   -
19   -#define CONFIG_SYS_SDRAM_BASE 0x20000000
20   -#define CONFIG_SYS_TEXT_BASE 0x23E00000
21   -#ifdef CONFIG_VAR_SIZE_SPL
22   -#define CONFIG_SPL_TEXT_BASE 0x02024410
23   -#else
24   -#define CONFIG_SPL_TEXT_BASE 0x02024400
25   -#endif
26   -#define CONFIG_IRAM_TOP 0x02074000
27   -
28   -#define CONFIG_SPL_MAX_FOOTPRINT (30 * 1024)
29   -
30   -#define CONFIG_DEVICE_TREE_LIST "exynos5420-peach-pit exynos5420-smdk5420"
31   -
32   -#define CONFIG_MAX_I2C_NUM 11
33   -
34   -/* Enable FIT support and comparison */
35   -#define CONFIG_FIT
36   -#define CONFIG_FIT_BEST_MATCH
37   -
38   -#define CONFIG_BOARD_REV_GPIO_COUNT 2
39   -
40   -#define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000"
41   -
42   -/*
43   - * Put the initial stack pointer 1KB below this to allow room for the
44   - * SPL marker. This value is arbitrary, but gd_t is placed starting here.
45   - */
46   -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800)
47   -
48   -/* DRAM Memory Banks */
49   -#define CONFIG_NR_DRAM_BANKS 7
50   -#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
51   -
52   -#endif /* __CONFIG_EXYNOS5420_H */
include/configs/odroid.h
Diff comments   View file @ ebf8644
... ... @@ -12,7 +12,7 @@
12 12 #ifndef __CONFIG_ODROID_U3_H
13 13 #define __CONFIG_ODROID_U3_H
14 14  
15   -#include <configs/exynos4-dt.h>
  15 +#include <configs/exynos4-common.h>
16 16  
17 17 #define CONFIG_SYS_PROMPT "Odroid # " /* Monitor Command Prompt */
18 18  
... ... @@ -37,8 +37,6 @@
37 37 #define CONFIG_SYS_TEXT_BASE 0x43e00000
38 38  
39 39 #include <linux/sizes.h>
40   -/* Size of malloc() pool */
41   -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M))
42 40  
43 41 /* select serial console configuration */
44 42 #define CONFIG_SERIAL1
include/configs/origen.h
Diff comments   View file @ ebf8644
... ... @@ -9,7 +9,7 @@
9 9 #ifndef __CONFIG_ORIGEN_H
10 10 #define __CONFIG_ORIGEN_H
11 11  
12   -#include <configs/exynos4-dt.h>
  12 +#include <configs/exynos4-common.h>
13 13  
14 14 #define CONFIG_SYS_PROMPT "ORIGEN # "
15 15  
... ... @@ -34,9 +34,6 @@
34 34 #define CONFIG_SYS_TEXT_BASE 0x43E00000
35 35  
36 36 #define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN
37   -
38   -/* Size of malloc() pool */
39   -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M))
40 37  
41 38 /* select serial console configuration */
42 39 #define CONFIG_SERIAL2
include/configs/peach-pit.h
Diff comments   View file @ ebf8644
... ... @@ -9,10 +9,16 @@
9 9 #ifndef __CONFIG_PEACH_PIT_H
10 10 #define __CONFIG_PEACH_PIT_H
11 11  
12   -#include <configs/exynos5-dt.h>
  12 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  13 +#define CONFIG_SPI_FLASH
  14 +#define CONFIG_ENV_SPI_BASE 0x12D30000
  15 +#define FLASH_SIZE (0x4 << 20)
  16 +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
13 17  
14   -#include <configs/exynos5420.h>
  18 +#include <configs/exynos5420-common.h>
  19 +#include <configs/exynos5-dt-common.h>
15 20  
  21 +#define CONFIG_BOARD_COMMON
16 22  
17 23 /* select serial console configuration */
18 24 #define CONFIG_SERIAL3 /* use SERIAL 3 */
... ... @@ -29,6 +35,12 @@
29 35 #define CONFIG_EXYNOS_DP
30 36 #define LCD_BPP LCD_COLOR16
31 37 #endif
  38 +
  39 +#define CONFIG_POWER_TPS65090_EC
  40 +#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
  41 +
  42 +#define CONFIG_USB_XHCI
  43 +#define CONFIG_USB_XHCI_EXYNOS
32 44  
33 45 #endif /* __CONFIG_PEACH_PIT_H */
include/configs/s5p_goni.h
Diff comments   View file @ ebf8644
... ... @@ -39,8 +39,9 @@
39 39 #define CONFIG_INITRD_TAG
40 40 #define CONFIG_CMDLINE_EDITING
41 41  
42   -/* Size of malloc() pool.*/
43   -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 80 * SZ_1M)
  42 +/* Size of malloc() pool before and after relocation */
  43 +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
  44 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20))
44 45  
45 46 /*
46 47 * select serial console configuration
... ... @@ -53,6 +54,7 @@
53 54 #define CONFIG_MMC
54 55 #define CONFIG_SDHCI
55 56 #define CONFIG_S5P_SDHCI
  57 +#define SDHCI_MAX_HOSTS 4
56 58  
57 59 /* PWM */
58 60 #define CONFIG_PWM 1
... ... @@ -106,7 +108,6 @@
106 108 ",12m(modem)"\
107 109 ",60m(qboot)\0"
108 110  
109   -#define CONFIG_BOOTDELAY 1
110 111 #define CONFIG_ZERO_BOOTDELAY_CHECK
111 112  
112 113 /* partitions definitions */
... ... @@ -282,6 +283,8 @@
282 283 #define CONFIG_USB_GADGET_VBUS_DRAW 2
283 284 #define CONFIG_CMD_USB_MASS_STORAGE
284 285 #define CONFIG_USB_GADGET_MASS_STORAGE
  286 +
  287 +#define CONFIG_OF_LIBFDT
285 288  
286 289 #endif /* __CONFIG_H */
include/configs/s5pc210_universal.h
Diff comments   View file @ ebf8644
... ... @@ -10,7 +10,7 @@
10 10 #ifndef __CONFIG_UNIVERSAL_H
11 11 #define __CONFIG_UNIVERSAL_H
12 12  
13   -#include <configs/exynos4-dt.h>
  13 +#include <configs/exynos4-common.h>
14 14  
15 15 #define CONFIG_SYS_PROMPT "Universal # " /* Monitor Command Prompt */
16 16  
... ... @@ -26,9 +26,6 @@
26 26 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
27 27  
28 28 #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
29   -
30   -/* Size of malloc() pool */
31   -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M))
32 29  
33 30 /* select serial console configuration */
34 31 #define CONFIG_SERIAL2
include/configs/smdk5250.h
Diff comments   View file @ ebf8644
... ... @@ -9,12 +9,27 @@
9 9 #ifndef __CONFIG_SMDK_H
10 10 #define __CONFIG_SMDK_H
11 11  
12   -#include <configs/exynos5250-dt.h>
  12 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  13 +#define CONFIG_SPI_FLASH
  14 +#define CONFIG_ENV_SPI_BASE 0x12D30000
  15 +#define FLASH_SIZE (0x4 << 20)
  16 +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
  17 +#define CONFIG_SPI_BOOTING
13 18  
  19 +#include <configs/exynos5250-common.h>
14 20  
15   -/* Enable FIT support and comparison */
16   -#define CONFIG_FIT
17   -#define CONFIG_FIT_BEST_MATCH
  21 +
  22 +#define CONFIG_BOARD_COMMON
  23 +#define CONFIG_ARCH_EARLY_INIT_R
  24 +
  25 +#define CONFIG_USB_XHCI
  26 +#define CONFIG_USB_XHCI_EXYNOS
  27 +
  28 +#define CONFIG_SYS_PROMPT "SMDK5250 # "
  29 +#define CONFIG_IDENT_STRING " for SMDK5250"
  30 +
  31 +/* Miscellaneous configurable options */
  32 +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
18 33  
19 34 #endif /* __CONFIG_SMDK_H */
include/configs/smdk5420.h
Diff comments   View file @ ebf8644
... ... @@ -9,9 +9,9 @@
9 9 #ifndef __CONFIG_SMDK5420_H
10 10 #define __CONFIG_SMDK5420_H
11 11  
12   -#include <configs/exynos5-dt.h>
  12 +#include <configs/exynos5420-common.h>
13 13  
14   -#include <configs/exynos5420.h>
  14 +#define CONFIG_BOARD_COMMON
15 15  
16 16 #define CONFIG_SMDK5420 /* which is in a SMDK5420 */
17 17  
... ... @@ -21,6 +21,7 @@
21 21  
22 22 #define CONFIG_SYS_PROMPT "SMDK5420 # "
23 23 #define CONFIG_IDENT_STRING " for SMDK5420"
  24 +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
24 25  
25 26 #endif /* __CONFIG_SMDK5420_H */
include/configs/smdkc100.h
Diff comments   View file @ ebf8644
... ... @@ -47,6 +47,10 @@
47 47 * 1MB = 0x100000, 0x100000 = 1024 * 1024
48 48 */
49 49 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
  50 +
  51 +/* Small malloc pool before relocation */
  52 +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10)
  53 +
50 54 /*
51 55 * select serial console configuration
52 56 */
... ... @@ -216,6 +220,8 @@
216 220 #define CONFIG_SMC911X_BASE 0x98800300 /* SMC911X Drive Base */
217 221 #define CONFIG_ENV_SROM_BANK 3 /* Select SROM Bank-3 for Ethernet*/
218 222 #endif /* CONFIG_CMD_NET */
  223 +
  224 +#define CONFIG_OF_LIBFDT
219 225  
220 226 #endif /* __CONFIG_H */
include/configs/smdkv310.h
Diff comments   View file @ ebf8644
... ... @@ -9,72 +9,43 @@
9 9 #ifndef __CONFIG_H
10 10 #define __CONFIG_H
11 11  
  12 +#include "exynos4-common.h"
  13 +
  14 +#undef CONFIG_BOARD_COMMON
  15 +#undef CONFIG_USB_GADGET
  16 +#undef CONFIG_USB_GADGET_S3C_UDC_OTG
  17 +#undef CONFIG_CMD_USB_MASS_STORAGE
  18 +#undef CONFIG_REVISION_TAG
  19 +#undef CONFIG_CMD_THOR_DOWNLOAD
  20 +#undef CONFIG_CMD_DFU
  21 +
12 22 /* High Level Configuration Options */
13   -#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
14   -#define CONFIG_S5P 1 /* S5P Family */
15   -#define CONFIG_EXYNOS4 /* EXYNOS4 Family */
16 23 #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
17 24 #define CONFIG_SMDKV310 1 /* working with SMDKV310*/
18 25  
19   -#include <asm/arch/cpu.h> /* get chip and board defs */
20   -
21   -#define CONFIG_ARCH_CPU_INIT
22   -#define CONFIG_DISPLAY_CPUINFO
23   -#define CONFIG_DISPLAY_BOARDINFO
24   -#define CONFIG_BOARD_EARLY_INIT_F
25   -
26 26 /* Mach Type */
27 27 #define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310
28 28  
29 29 #define CONFIG_SYS_SDRAM_BASE 0x40000000
30 30 #define CONFIG_SYS_TEXT_BASE 0x43E00000
31 31  
32   -/* input clock of PLL: SMDKV310 has 24MHz input clock */
33   -#define CONFIG_SYS_CLK_FREQ 24000000
34   -
35   -#define CONFIG_SETUP_MEMORY_TAGS
36   -#define CONFIG_CMDLINE_TAG
37   -#define CONFIG_INITRD_TAG
38   -#define CONFIG_CMDLINE_EDITING
39   -
40 32 /* Handling Sleep Mode*/
41 33 #define S5P_CHECK_SLEEP 0x00000BAD
42 34 #define S5P_CHECK_DIDLE 0xBAD00000
43 35 #define S5P_CHECK_LPA 0xABAD0000
44 36  
45   -/* Size of malloc() pool */
46   -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
47   -
48 37 /* select serial console configuration */
49 38 #define CONFIG_SERIAL1 1 /* use SERIAL 1 */
50   -#define CONFIG_BAUDRATE 115200
51 39 #define EXYNOS4_DEFAULT_UART_OFFSET 0x010000
52 40  
53   -/* SD/MMC configuration */
54   -#define CONFIG_GENERIC_MMC
55   -#define CONFIG_MMC
56   -#define CONFIG_SDHCI
57   -#define CONFIG_S5P_SDHCI
58   -
59   -/* PWM */
60   -#define CONFIG_PWM 1
61   -
62 41 /* allow to overwrite serial and ethaddr */
63 42 #define CONFIG_ENV_OVERWRITE
64 43  
65   -/* Command definition*/
66   -#include <config_cmd_default.h>
67   -
68 44 #define CONFIG_CMD_PING
69 45 #define CONFIG_CMD_ELF
70 46 #define CONFIG_CMD_DHCP
71   -#define CONFIG_CMD_MMC
72 47 #define CONFIG_CMD_NET
73   -#define CONFIG_CMD_FAT
74 48  
75   -#define CONFIG_BOOTDELAY 3
76   -#define CONFIG_ZERO_BOOTDELAY_CHECK
77   -
78 49 /* MMC SPL */
79 50 #define CONFIG_SKIP_LOWLEVEL_INIT
80 51 #define COPY_BL2_FNPTR_ADDR 0x00002488
81 52  
82 53  
... ... @@ -84,15 +55,8 @@
84 55 #define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
85 56  
86 57 /* Miscellaneous configurable options */
87   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
88   -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
89 58 #define CONFIG_SYS_PROMPT "SMDKV310 # "
90   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/
91   -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
92   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
93 59 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
94   -/* Boot Argument Buffer Size */
95   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
96 60 /* memtest works on */
97 61 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
98 62 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
... ... @@ -111,8 +75,6 @@
111 75 #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
112 76  
113 77 /* FLASH and environment organization */
114   -#define CONFIG_SYS_NO_FLASH 1
115   -#undef CONFIG_CMD_IMLS
116 78 #define CONFIG_IDENT_STRING " for SMDKC210/V310"
117 79  
118 80 #define CONFIG_CLK_1000_400_200
... ... @@ -126,7 +88,6 @@
126 88 #define RESERVE_BLOCK_SIZE (512)
127 89 #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
128 90 #define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE)
129   -#define CONFIG_DOS_PARTITION 1
130 91  
131 92 #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
132 93 #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
... ... @@ -146,7 +107,5 @@
146 107 #define CONFIG_ENV_SROM_BANK 1
147 108 #endif /*CONFIG_CMD_NET*/
148 109  
149   -/* Enable devicetree support */
150   -#define CONFIG_OF_LIBFDT
151 110 #endif /* __CONFIG_H */
include/configs/snow.h
Diff comments   View file @ ebf8644
... ... @@ -9,12 +9,29 @@
9 9 #ifndef __CONFIG_SNOW_H
10 10 #define __CONFIG_SNOW_H
11 11  
12   -#include <configs/exynos5250-dt.h>
  12 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  13 +#define CONFIG_SPI_FLASH
  14 +#define CONFIG_ENV_SPI_BASE 0x12D30000
  15 +#define FLASH_SIZE (0x4 << 20)
  16 +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
  17 +#define CONFIG_SPI_BOOTING
13 18  
  19 +#include <configs/exynos5250-common.h>
  20 +#include <configs/exynos5-dt-common.h>
14 21  
15   -/* Enable FIT support and comparison */
16   -#define CONFIG_FIT
17   -#define CONFIG_FIT_BEST_MATCH
  22 +
  23 +#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */
  24 +#define CONFIG_POWER_TPS65090_I2C
  25 +
  26 +#define CONFIG_BOARD_COMMON
  27 +#define CONFIG_ARCH_EARLY_INIT_R
  28 +
  29 +#define CONFIG_USB_XHCI
  30 +#define CONFIG_USB_XHCI_EXYNOS
  31 +
  32 +#define CONFIG_SYS_PROMPT "snow # "
  33 +#define CONFIG_IDENT_STRING " for snow"
  34 +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
18 35  
19 36 #endif /* __CONFIG_SNOW_H */
include/configs/trats.h
Diff comments   View file @ ebf8644
... ... @@ -10,7 +10,7 @@
10 10 #ifndef __CONFIG_TRATS_H
11 11 #define __CONFIG_TRATS_H
12 12  
13   -#include <configs/exynos4-dt.h>
  13 +#include <configs/exynos4-common.h>
14 14  
15 15 #define CONFIG_SYS_PROMPT "Trats # " /* Monitor Command Prompt */
16 16  
... ... @@ -38,10 +38,6 @@
38 38 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
39 39  
40 40 #define CONFIG_SYS_TEXT_BASE 0x63300000
41   -
42   -#include <linux/sizes.h>
43   -/* Size of malloc() pool */
44   -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M))
45 41  
46 42 /* select serial console configuration */
47 43 #define CONFIG_SERIAL2
include/configs/trats2.h
Diff comments   View file @ ebf8644
... ... @@ -11,7 +11,7 @@
11 11 #ifndef __CONFIG_TRATS2_H
12 12 #define __CONFIG_TRATS2_H
13 13  
14   -#include <configs/exynos4-dt.h>
  14 +#include <configs/exynos4-common.h>
15 15  
16 16 #define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */
17 17  
... ... @@ -35,10 +35,6 @@
35 35 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
36 36  
37 37 #define CONFIG_SYS_TEXT_BASE 0x43e00000
38   -
39   -#include <linux/sizes.h>
40   -/* Size of malloc() pool */
41   -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M))
42 38  
43 39 /* select serial console configuration */
44 40 #define CONFIG_SERIAL2