Commit ec27deab06b022a5d7738f22431fb38e29ec2f74
1 parent
489929be02
Exists in
smarc-rel_imx_4.1.15_2.0.0_ga
MLK-12748-1 imx: adjust i.mx7d standby voltage setting
i.MX7D VDD_ARM/SOC standby voltage should be 0.95V, adding 25mV margin, so set it to 0.975V; Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Showing 5 changed files with 14 additions and 14 deletions Side-by-side Diff
board/freescale/mx7d_12x12_ddr3_arm2/mx7d_12x12_ddr3_arm2.c
... | ... | @@ -298,12 +298,12 @@ |
298 | 298 | pmic_reg_write(p, PFUZE3000_SW1AMODE, reg); |
299 | 299 | pmic_reg_write(p, PFUZE3000_SW1BMODE, reg); |
300 | 300 | |
301 | - /* SW1A/1B standby voltage set to 1.025V */ | |
302 | - reg = 0xd; | |
301 | + /* SW1A/1B standby voltage set to 0.975V */ | |
302 | + reg = 0xb; | |
303 | 303 | pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg); |
304 | 304 | pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg); |
305 | 305 | |
306 | - /* decrease SW1B normal voltage to 0.975V */ | |
306 | + /* set SW1B normal voltage to 0.975V */ | |
307 | 307 | pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®); |
308 | 308 | reg &= ~0x1f; |
309 | 309 | reg |= PFUZE3000_SW1AB_SETP(975); |
board/freescale/mx7d_12x12_lpddr3_arm2/mx7d_12x12_lpddr3_arm2.c
... | ... | @@ -760,8 +760,8 @@ |
760 | 760 | pmic_reg_write(p, PFUZE3000_SW1AMODE, reg); |
761 | 761 | pmic_reg_write(p, PFUZE3000_SW1BMODE, reg); |
762 | 762 | |
763 | - /* SW1A/1B standby voltage set to 1.025V */ | |
764 | - reg = 0xd; | |
763 | + /* SW1A/1B standby voltage set to 0.975V */ | |
764 | + reg = 0xb; | |
765 | 765 | pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg); |
766 | 766 | pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg); |
767 | 767 | |
... | ... | @@ -782,7 +782,7 @@ |
782 | 782 | reg |= 0x20; |
783 | 783 | pmic_reg_write(p, PFUZE3000_SW2MODE, reg); |
784 | 784 | |
785 | - /* decrease SW1B normal voltage to 0.975V */ | |
785 | + /* set SW1B normal voltage to 0.975V */ | |
786 | 786 | pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®); |
787 | 787 | reg &= ~0x1f; |
788 | 788 | reg |= PFUZE3000_SW1AB_SETP(975); |
board/freescale/mx7d_19x19_ddr3_arm2/mx7d_19x19_ddr3_arm2.c
... | ... | @@ -548,12 +548,12 @@ |
548 | 548 | pmic_reg_write(p, PFUZE3000_SW1AMODE, reg); |
549 | 549 | pmic_reg_write(p, PFUZE3000_SW1BMODE, reg); |
550 | 550 | |
551 | - /* SW1A/1B standby voltage set to 1.025V */ | |
552 | - reg = 0xd; | |
551 | + /* SW1A/1B standby voltage set to 0.975V */ | |
552 | + reg = 0xb; | |
553 | 553 | pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg); |
554 | 554 | pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg); |
555 | 555 | |
556 | - /* decrease SW1B normal voltage to 0.975V */ | |
556 | + /* set SW1B normal voltage to 0.975V */ | |
557 | 557 | pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®); |
558 | 558 | reg &= ~0x1f; |
559 | 559 | reg |= PFUZE3000_SW1AB_SETP(975); |
board/freescale/mx7d_19x19_lpddr3_arm2/mx7d_19x19_lpddr3_arm2.c
... | ... | @@ -547,12 +547,12 @@ |
547 | 547 | pmic_reg_write(p, PFUZE3000_SW1AMODE, reg); |
548 | 548 | pmic_reg_write(p, PFUZE3000_SW1BMODE, reg); |
549 | 549 | |
550 | - /* SW1A/1B standby voltage set to 1.025V */ | |
551 | - reg = 0xd; | |
550 | + /* SW1A/1B standby voltage set to 0.975V */ | |
551 | + reg = 0xb; | |
552 | 552 | pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg); |
553 | 553 | pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg); |
554 | 554 | |
555 | - /* decrease SW1B normal voltage to 0.975V */ | |
555 | + /* set SW1B normal voltage to 0.975V */ | |
556 | 556 | pmic_reg_read(p, PFUZE3000_SW1BVOLT, ®); |
557 | 557 | reg &= ~0x1f; |
558 | 558 | reg |= PFUZE3000_SW1AB_SETP(975); |
board/freescale/mx7dsabresd/mx7dsabresd.c
... | ... | @@ -987,8 +987,8 @@ |
987 | 987 | pmic_reg_write(p, PFUZE3000_SW1AMODE, reg); |
988 | 988 | pmic_reg_write(p, PFUZE3000_SW1BMODE, reg); |
989 | 989 | |
990 | - /* SW1A/1B standby voltage set to 1.025V */ | |
991 | - reg = 0xd; | |
990 | + /* SW1A/1B standby voltage set to 0.975V */ | |
991 | + reg = 0xb; | |
992 | 992 | pmic_reg_write(p, PFUZE3000_SW1ASTBY, reg); |
993 | 993 | pmic_reg_write(p, PFUZE3000_SW1BSTBY, reg); |
994 | 994 |