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Commit ef531c73570794b7676b62de4224bd294919b83b

Authored by Shengzhou Liu
Committed by York Sun
1 parent 4d66668300
Exists in v2017.01-smarct4x and in 40 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

board/t2080rdb: some update for t2080rdb 

- update readme.
- add CONFIG_SYS_CORTINA_FW_IN_* for loading Cortina PHY CS4315
  ucode from NOR/NAND/SPI/SD/REMOTE.
- update cpld vbank with SW3[5:7]=000 as default vbank0 instead of
  previous SW3[5:7]=111 as default vbank.
- fix CONFIG_SYS_I2C_EEPROM_ADDR_LEN to 2.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

Showing 4 changed files with 15 additions and 10 deletions Side-by-side Diff

board/freescale/t208xrdb/README
Diff comments   View file @ ef531c7
... ... @@ -67,7 +67,7 @@
67 67 - One PCIe x2 end-point device (C293 Crypto co-processor)
68 68 - IFC/Local Bus
69 69 - NOR: 128MB 16-bit NOR Flash
70   - - NAND: 512MB 8-bit NAND flash
  70 + - NAND: 1GB 8-bit NAND flash
71 71 - CPLD: for system controlling with programable header on-board
72 72 - SATA
73 73 - Two SATA 2.0 onnectors on-board
74 74  
... ... @@ -156,11 +156,11 @@
156 156 Switching between default bank and alternate bank on NOR flash
157 157 To change boot source to vbank4:
158 158 via software: run command 'cpld reset altbank' in u-boot.
159   - via DIP-switch: set SW3[5:7] = '011'
  159 + via DIP-switch: set SW3[5:7] = '100'
160 160  
161 161 To change boot source to vbank0:
162 162 via software: run command 'cpld reset' in u-boot.
163   - via DIP-Switch: set SW3[5:7] = '111'
  163 + via DIP-Switch: set SW3[5:7] = '000'
164 164  
165 165 2. NAND Boot:
166 166 a. build PBL image for NAND boot
board/freescale/t208xrdb/cpld.h
Diff comments   View file @ ef531c7
... ... @@ -35,8 +35,8 @@
35 35 #define CPLD_LBMAP_MASK 0x3F
36 36 #define CPLD_BANK_SEL_MASK 0x07
37 37 #define CPLD_BANK_OVERRIDE 0x40
38   -#define CPLD_LBMAP_ALTBANK 0x43 /* BANK OR | BANK 4 */
39   -#define CPLD_LBMAP_DFLTBANK 0x47 /* BANK OR | BANK 0 */
  38 +#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
  39 +#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */
40 40 #define CPLD_LBMAP_RESET 0xFF
41 41 #define CPLD_LBMAP_SHIFT 0x03
42 42 #define CPLD_BOOT_SEL 0x80
board/freescale/t208xrdb/t208xrdb.c
Diff comments   View file @ ef531c7
... ... @@ -44,7 +44,7 @@
44 44 puts("NAND\n");
45 45 } else {
46 46 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
47   - printf("NOR vBank%d\n", ~reg & 0x7);
  47 + printf("NOR vBank%d\n", reg);
48 48 }
49 49 #endif
50 50  
include/configs/T208xRDB.h
Diff comments   View file @ ef531c7
... ... @@ -208,7 +208,7 @@
208 208 #define CONFIG_SYS_I2C_EEPROM_NXID
209 209 #define CONFIG_SYS_EEPROM_BUS_NUM 0
210 210 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
211   -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  211 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
212 212  
213 213 /*
214 214 * DDR Setup
... ... @@ -584,7 +584,8 @@
584 584 * env, so we got 0x110000.
585 585 */
586 586 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
587   -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
  587 +#define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
  588 +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
588 589 #define CONFIG_CORTINA_FW_ADDR 0x120000
589 590  
590 591 #elif defined(CONFIG_SDCARD)
591 592  
... ... @@ -594,11 +595,13 @@
594 595 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
595 596 */
596 597 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
  598 +#define CONFIG_SYS_CORTINA_FW_IN_MMC
597 599 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
598 600 #define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
599 601  
600 602 #elif defined(CONFIG_NAND)
601 603 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
  604 +#define CONFIG_SYS_CORTINA_FW_IN_NAND
602 605 #define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
603 606 #define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
604 607 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
605 608  
... ... @@ -610,11 +613,13 @@
610 613 * master LAW->the ucode address in master's memory space.
611 614 */
612 615 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
613   -#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
  616 +#define CONFIG_SYS_CORTINA_FW_IN_REMOTE
  617 +#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
614 618 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000
615 619 #else
616 620 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
617   -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
  621 +#define CONFIG_SYS_CORTINA_FW_IN_NOR
  622 +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
618 623 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000
619 624 #endif
620 625 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000