Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit f267d207cea0eab157014bc9709820556d9a76c4

Authored by BJ DevOps Team
2 parents a42789ade3 03a3bdb7a9
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

Merge remote-tracking branch 'origin/ls_v2020.04' into lf_v2020.04 

* origin/ls_v2020.04:
  net: memac_phy: add a timeout to MDIO operations
  armv8: lx2: SVR_SOC_VER: Mask CAN_FD and security bit

Showing 2 changed files Side-by-side Diff

arch/arm/include/asm/arch-fsl-layerscape/soc.h
Diff comments   View file @ f267d20
1 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 2 /*
3   - * Copyright 2017-2020 NXP
  3 + * Copyright 2017-2021 NXP
4 4 * Copyright 2015 Freescale Semiconductor
5 5 */
6 6  
7 7  
... ... @@ -82,10 +82,13 @@
82 82 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
83 83 #define SVR_MIN(svr) (((svr) >> 0) & 0xf)
84 84 #define SVR_REV(svr) (((svr) >> 0) & 0xff)
85   -#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
86 85 #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
87 86 #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
88 87 #define IS_C_PROCESSOR(svr) (!((svr >> 12) & 0x1))
  88 +#define SVR_WO_CE 0xFFFFEE
  89 +#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_CE)
  90 +#else
  91 +#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
89 92 #endif
90 93 #ifdef CONFIG_ARCH_LS1028A
91 94 #define IS_MULTIMEDIA_EN(svr) (!((svr >> 10) & 0x1))
drivers/net/fm/memac_phy.c
Diff comments   View file @ f267d20
... ... @@ -22,6 +22,8 @@
22 22 #define memac_setbits_32(a, v) setbits_be32(a, v)
23 23 #endif
24 24  
  25 +#define MAX_NUM_RETRIES 1000
  26 +
25 27 static u32 memac_in_32(u32 *reg)
26 28 {
27 29 #ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
... ... @@ -32,6 +34,42 @@
32 34 }
33 35  
34 36 /*
  37 + * Wait until the MDIO bus is free
  38 + */
  39 +static int memac_wait_until_free(struct memac_mdio_controller *regs)
  40 +{
  41 + unsigned int timeout = MAX_NUM_RETRIES;
  42 +
  43 + while ((memac_in_32(&regs->mdio_stat) & MDIO_STAT_BSY) && timeout--)
  44 + ;
  45 +
  46 + if (!timeout) {
  47 + printf("timeout waiting for MDIO bus to be free\n");
  48 + return -ETIMEDOUT;
  49 + }
  50 +
  51 + return 0;
  52 +}
  53 +
  54 +/*
  55 + * Wait till the MDIO read or write operation is complete
  56 + */
  57 +static int memac_wait_until_done(struct memac_mdio_controller *regs)
  58 +{
  59 + unsigned int timeout = MAX_NUM_RETRIES;
  60 +
  61 + while ((memac_in_32(&regs->mdio_data) & MDIO_DATA_BSY) && timeout--)
  62 + ;
  63 +
  64 + if (!timeout) {
  65 + printf("timeout waiting for MDIO operation to complete\n");
  66 + return -ETIMEDOUT;
  67 + }
  68 +
  69 + return 0;
  70 +}
  71 +
  72 +/*
35 73 * Write value to the PHY for this device to the register at regnum, waiting
36 74 * until the write is done before it returns. All PHY configuration has to be
37 75 * done through the TSEC1 MIIM regs
... ... @@ -42,6 +80,7 @@
42 80 u32 mdio_ctl;
43 81 struct memac_mdio_controller *regs = bus->priv;
44 82 u32 c45 = 1; /* Default to 10G interface */
  83 + int err;
45 84  
46 85 if (dev_addr == MDIO_DEVAD_NONE) {
47 86 c45 = 0; /* clause 22 */
... ... @@ -50,9 +89,9 @@
50 89 } else
51 90 memac_setbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
52 91  
53   - /* Wait till the bus is free */
54   - while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
55   - ;
  92 + err = memac_wait_until_free(regs);
  93 + if (err)
  94 + return err;
56 95  
57 96 /* Set the port and dev addr */
58 97 mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
59 98  
... ... @@ -62,16 +101,16 @@
62 101 if (c45)
63 102 memac_out_32(&regs->mdio_addr, regnum & 0xffff);
64 103  
65   - /* Wait till the bus is free */
66   - while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
67   - ;
  104 + err = memac_wait_until_free(regs);
  105 + if (err)
  106 + return err;
68 107  
69 108 /* Write the value to the register */
70 109 memac_out_32(&regs->mdio_data, MDIO_DATA(value));
71 110  
72   - /* Wait till the MDIO write is complete */
73   - while ((memac_in_32(&regs->mdio_data)) & MDIO_DATA_BSY)
74   - ;
  111 + err = memac_wait_until_done(regs);
  112 + if (err)
  113 + return err;
75 114  
76 115 return 0;
77 116 }
... ... @@ -87,6 +126,7 @@
87 126 u32 mdio_ctl;
88 127 struct memac_mdio_controller *regs = bus->priv;
89 128 u32 c45 = 1;
  129 + int err;
90 130  
91 131 if (dev_addr == MDIO_DEVAD_NONE) {
92 132 if (!strcmp(bus->name, DEFAULT_FM_TGEC_MDIO_NAME))
... ... @@ -97,9 +137,9 @@
97 137 } else
98 138 memac_setbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
99 139  
100   - /* Wait till the bus is free */
101   - while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
102   - ;
  140 + err = memac_wait_until_free(regs);
  141 + if (err)
  142 + return err;
103 143  
104 144 /* Set the Port and Device Addrs */
105 145 mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
106 146  
... ... @@ -109,17 +149,17 @@
109 149 if (c45)
110 150 memac_out_32(&regs->mdio_addr, regnum & 0xffff);
111 151  
112   - /* Wait till the bus is free */
113   - while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
114   - ;
  152 + err = memac_wait_until_free(regs);
  153 + if (err)
  154 + return err;
115 155  
116 156 /* Initiate the read */
117 157 mdio_ctl |= MDIO_CTL_READ;
118 158 memac_out_32(&regs->mdio_ctl, mdio_ctl);
119 159  
120   - /* Wait till the MDIO write is complete */
121   - while ((memac_in_32(&regs->mdio_data)) & MDIO_DATA_BSY)
122   - ;
  160 + err = memac_wait_until_done(regs);
  161 + if (err)
  162 + return err;
123 163  
124 164 /* Return all Fs if nothing was there */
125 165 if (memac_in_32(&regs->mdio_stat) & MDIO_STAT_RD_ER)