Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit f31be1ee0994a79dba7f8eb62ac4f08cafe687fd

Authored by BJ DevOps Team
2 parents f267d207ce ec9bce0ae4
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

Merge remote-tracking branch 'origin/ls_v2020.04' into lf_v2020.04 

* origin/ls_v2020.04:
  arm: dts: ls1028a: define QDS networking protocol combinations

Showing 16 changed files Inline Diff

arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi
Diff comments   View file @ f31be1e
File was created 1 // SPDX-License-Identifier: GPL-2.0+ OR X11
2 /*
3 * NXP LS1028A-QDS device tree fragment for RCW 1xxx
4 *
5 * Copyright 2019-2021 NXP Semiconductors
6 */
7
8 /*
9 * This setup is using a SCH-30842 card with AQR112 PHY in slot 1 for ENETC
10 * port 0 USXGMII.
11 */
12 &slot1 {
13 #include "fsl-sch-30842.dtsi"
14 };
15
16 &enetc0 {
17 status = "okay";
18 phy-mode = "usxgmii";
19 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
20 };
21
arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi
Diff comments   View file @ f31be1e
File was created 1 // SPDX-License-Identifier: GPL-2.0+ OR X11
2 /*
3 * NXP LS1028A-QDS device tree fragment for RCW 6xxx
4 *
5 * Copyright 2019-2021 NXP Semiconductors
6 */
7
8 /*
9 * This setup is using SCH-30842 cards with AQR112 PHY.
10 */
11 &slot1 {
12 #include "fsl-sch-30842.dtsi"
13 };
14
15 &enetc0 {
16 status = "okay";
17 phy-mode = "sgmii-2500";
18 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
19 };
20
arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
Diff comments   View file @ f31be1e
File was created 1 // SPDX-License-Identifier: GPL-2.0+ OR X11
2 /*
3 * NXP LS1028A-QDS device tree fragment for RCW 7777
4 *
5 * Copyright 2019-2021 NXP Semiconductors
6 */
7
8 /*
9 * This setup is using a SCH-30841 card with AQR412 10G quad PHY.
10 *
11 * Switch ports are mapped 1:1 to AQR412 card ports seated in slot 1.
12 * Bottom port is port 0.
13 * Note that this is only usable for:
14 * - QDS boards WITHOUT lane B rework,
15 * - AQR412 card WITHOUT lane A -> lane C rework
16 *
17 * The following DTS assumes DIP SW5[1-3] = 000b.
18 */
19 &slot1 {
20 #include "fsl-sch-30841.dtsi"
21 };
22
23 &ethsw_ports {
24 port@0 {
25 status = "okay";
26 phy-mode = "sgmii-2500";
27 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>;
28 };
29 port@1 {
30 status = "okay";
31 phy-mode = "sgmii-2500";
32 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>;
33 };
34 port@2 {
35 status = "okay";
36 phy-mode = "sgmii-2500";
37 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
38 };
39 port@3 {
40 status = "okay";
41 phy-mode = "sgmii-2500";
42 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
43 };
44 };
45
arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
Diff comments   View file @ f31be1e
File was created 1 // SPDX-License-Identifier: GPL-2.0+ OR X11
2 /*
3 * NXP LS1028A-QDS device tree fragment for RCW 7xx7
4 *
5 * Copyright 2019-2021 NXP Semiconductors
6 */
7
8 &slot1 {
9 #include "fsl-sch-30841.dtsi"
10 };
11
12 &ethsw_ports {
13 port@0 {
14 status = "okay";
15 phy-mode = "sgmii-2500";
16 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
17 };
18 port@3 {
19 status = "okay";
20 phy-mode = "sgmii-2500";
21 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
22 };
23 };
24
arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi
Diff comments   View file @ f31be1e
File was created 1 // SPDX-License-Identifier: GPL-2.0+ OR X11
2 /*
3 * NXP LS1028A-QDS device tree fragment for RCW 8xxx
4 *
5 * Copyright 2019-2021 NXP Semiconductors
6 */
7
8 /*
9 * This setup is using SCH-24801 cards with VSC8234 quad SGMII PHY in slot 1.
10 */
11 &slot1 {
12 #include "fsl-sch-24801.dtsi"
13 };
14
15 &enetc0 {
16 status = "okay";
17 phy-mode = "sgmii";
18 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
19 };
20
arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
Diff comments   View file @ f31be1e
File was created 1 // SPDX-License-Identifier: GPL-2.0+ OR X11
2 /*
3 * NXP LS1028A-QDS device tree fragment for RCW 9999
4 *
5 * Copyright 2019-2021 NXP Semiconductors
6 */
7
8 /*
9 * This setup is using SCH-24801 cards with VSC8234 quad SGMII PHY.
10 * LS1028A QDS boards with lane B rework require two cards for the 4 switch
11 * ports, QDS boards without the lane B rework only require one card.
12 *
13 * Switch ports are routed as follows:
14 * Port 0 goes to 1st port of VSC8234 quad card in slot 1,
15 * Port 1:
16 * - if the QDS has had lane B rework, it is 1st port in slot 2,
17 * - otherwise it is 2nd port in slot 1.
18 * Port 2:
19 * - if DIP SW5[1] = 0 it is 3rd port in slot 1,
20 * - otherwise it is 1st port in slot 3.
21 * Port 3:
22 * - if DIP SW5[2-3] = 00b it is 4th port in slot 1,
23 * - if DIP SW5[2-3] = 01b it is 2nd port in slot 3,
24 * - if DIP SW5[2-3] = 11b it is 1st port in slot 4.
25 *
26 * The following DTS assumes QDS lane B rework and DIP SW5[1-3] = 000b. Two
27 * SCH-24801 cards are required in slots 1 and 2.
28 */
29 &slot1 {
30 #include "fsl-sch-24801.dtsi"
31 };
32
33 &slot2 {
34 #include "fsl-sch-24801.dtsi"
35 };
36
37 &ethsw_ports {
38 port@0 {
39 status = "okay";
40 phy-mode = "sgmii";
41 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
42 };
43 port@1 {
44 status = "okay";
45 phy-mode = "sgmii";
46 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@1c}>;
47 };
48 port@2 {
49 status = "okay";
50 phy-mode = "sgmii";
51 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
52 };
53 port@3 {
54 status = "okay";
55 phy-mode = "sgmii";
56 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
57 };
58 };
59
arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
Diff comments   View file @ f31be1e
File was created 1 // SPDX-License-Identifier: GPL-2.0+ OR X11
2 /*
3 * NXP LS1028A-QDS device tree fragment for RCW 9999
4 *
5 * Copyright 2019-2021 NXP Semiconductors
6 *
7 */
8
9 /*
10 * This set-up is using SCH-24801 cards with VSC8234 quad SGMII PHY.
11 *
12 * Switch ports are mapped 1:1 to VSC8234 card ports seated in slot 1.
13 * Top port is port 0.
14 *
15 * The following DTS assumes DIP SW5[1-3] = 000b.
16 */
17
18 &slot1 {
19 #include "fsl-sch-24801.dtsi"
20 };
21
22 &ethsw_ports {
23 port@0 {
24 status = "okay";
25 phy-mode = "sgmii";
26 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
27 };
28 port@1 {
29 status = "okay";
30 phy-mode = "sgmii";
31 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1d}>;
32 };
33 port@2 {
34 status = "okay";
35 phy-mode = "sgmii";
36 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
37 };
38 port@3 {
39 status = "okay";
40 phy-mode = "sgmii";
41 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
42 };
43 };
44
arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
Diff comments   View file @ f31be1e
File was created 1 // SPDX-License-Identifier: GPL-2.0+ OR X11
2 /*
3 * NXP LS1028A-QDS device tree fragment for RCW x3xx
4 *
5 * Copyright 2019-2021 NXP Semiconductors
6 */
7
8 /*
9 * This setup is using a SCH-30841-R card with AQR412 quad PHY in slot 2. This
10 * is used for the 4 integrated ethernet switch in a multiplexes USXGMII set-up.
11 *
12 * We're including the normal .dsti file, not the reworked card .dtsi
13 * intentionally. We are using multiplexing of the 4 interfaces on a single
14 * lane and the rework doesn't actually disable any port. The rework is in fact
15 * needed, otherwise the PHY won't work with the default wiring on the QDS/PHY
16 * card.
17 */
18 &slot2 {
19 #include "fsl-sch-30841.dtsi"
20 };
21
22 &ethsw_ports {
23 port@0 {
24 status = "okay";
25 phy-mode = "usxgmii";
26 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@00}>;
27 };
28 port@1 {
29 status = "okay";
30 phy-mode = "usxgmii";
31 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@01}>;
32 };
33 port@2 {
34 status = "okay";
35 phy-mode = "usxgmii";
36 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
37 };
38 port@3 {
39 status = "okay";
40 phy-mode = "usxgmii";
41 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>;
42 };
43 };
44
arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
Diff comments   View file @ f31be1e
File was created 1 // SPDX-License-Identifier: GPL-2.0+ OR X11
2 /*
3 * NXP LS1028A-QDS device tree fragment for RCW x5xx
4 *
5 * Copyright 2019-2021 NXP Semiconductors
6 */
7
8 /*
9 * This setup is using SCH-28021 cards with VSC8514 QSGMII PHY in slot 2.
10 * This is only available on LS1028A QDS boards with lane B rework.
11 */
12 &slot2 {
13 #include "fsl-sch-28021.dtsi"
14 };
15
16 &ethsw_ports {
17 port@0 {
18 status = "okay";
19 phy-mode = "qsgmii";
20 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>;
21 };
22 port@1 {
23 status = "okay";
24 phy-mode = "qsgmii";
25 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>;
26 };
27 port@2 {
28 status = "okay";
29 phy-mode = "qsgmii";
30 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>;
31 };
32 port@3 {
33 status = "okay";
34 phy-mode = "qsgmii";
35 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>;
36 };
37 };
38
arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
Diff comments   View file @ f31be1e
File was created 1 // SPDX-License-Identifier: GPL-2.0+ OR X11
2 /*
3 * NXP LS1028A-QDS device tree fragment for RCW 7777
4 *
5 * Copyright 2019-2021 NXP Semiconductors
6 */
7
8 &slot2 {
9 #include "fsl-sch-30842.dtsi"
10 };
11
12 &ethsw_ports {
13 port@1 {
14 status = "okay";
15 phy-mode = "sgmii-2500";
16 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
17 };
18 };
19
arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
Diff comments   View file @ f31be1e
File was created 1 // SPDX-License-Identifier: GPL-2.0+ OR X11
2 /*
3 * NXP LS1028A-QDS device tree fragment for RCW 7777
4 *
5 * Copyright 2019-2021 NXP Semiconductors
6 */
7
8 &slot3 {
9 #include "fsl-sch-30842.dtsi"
10 };
11
12 &ethsw_ports {
13 port@2 {
14 status = "okay";
15 phy-mode = "sgmii-2500";
16 phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>;
17 };
18 };
19
arch/arm/dts/fsl-ls1028a-qds.dtsi
Diff comments   View file @ f31be1e
1 // SPDX-License-Identifier: GPL-2.0+ OR X11 1 // SPDX-License-Identifier: GPL-2.0+ OR X11
2 /* 2 /*
3 * NXP ls1028AQDS device tree source 3 * NXP ls1028AQDS device tree source
4 * 4 *
5 * Copyright 2019 NXP 5 * Copyright 2019 NXP
6 * 6 *
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 10
11 #include "fsl-ls1028a.dtsi" 11 #include "fsl-ls1028a.dtsi"
12 12
13 / { 13 / {
14 model = "NXP Layerscape 1028a QDS Board"; 14 model = "NXP Layerscape 1028a QDS Board";
15 compatible = "fsl,ls1028a-qds", "fsl,ls1028a"; 15 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
16 aliases { 16 aliases {
17 spi0 = &fspi; 17 spi0 = &fspi;
18 spi1 = &dspi0; 18 spi1 = &dspi0;
19 spi2 = &dspi1; 19 spi2 = &dspi1;
20 spi3 = &dspi2; 20 spi3 = &dspi2;
21 }; 21 };
22 22
23 }; 23 };
24 24
25 &dspi0 { 25 &dspi0 {
26 bus-num = <0>; 26 bus-num = <0>;
27 status = "okay"; 27 status = "okay";
28 28
29 dflash0: sst25wf040b { 29 dflash0: sst25wf040b {
30 #address-cells = <1>; 30 #address-cells = <1>;
31 #size-cells = <1>; 31 #size-cells = <1>;
32 compatible = "spi-flash"; 32 compatible = "spi-flash";
33 spi-max-frequency = <3000000>; 33 spi-max-frequency = <3000000>;
34 spi-cpol; 34 spi-cpol;
35 spi-cpha; 35 spi-cpha;
36 reg = <0>; 36 reg = <0>;
37 }; 37 };
38 38
39 dflash1: en25s64 { 39 dflash1: en25s64 {
40 #address-cells = <1>; 40 #address-cells = <1>;
41 #size-cells = <1>; 41 #size-cells = <1>;
42 compatible = "spi-flash"; 42 compatible = "spi-flash";
43 spi-max-frequency = <3000000>; 43 spi-max-frequency = <3000000>;
44 spi-cpol; 44 spi-cpol;
45 spi-cpha; 45 spi-cpha;
46 reg = <1>; 46 reg = <1>;
47 }; 47 };
48 dflash2: n25q128a { 48 dflash2: n25q128a {
49 #address-cells = <1>; 49 #address-cells = <1>;
50 #size-cells = <1>; 50 #size-cells = <1>;
51 compatible = "spi-flash"; 51 compatible = "spi-flash";
52 spi-max-frequency = <3000000>; 52 spi-max-frequency = <3000000>;
53 spi-cpol; 53 spi-cpol;
54 spi-cpha; 54 spi-cpha;
55 reg = <2>; 55 reg = <2>;
56 }; 56 };
57 }; 57 };
58 58
59 &dspi1 { 59 &dspi1 {
60 bus-num = <0>; 60 bus-num = <0>;
61 status = "okay"; 61 status = "okay";
62 62
63 dflash3: sst25wf040b { 63 dflash3: sst25wf040b {
64 #address-cells = <1>; 64 #address-cells = <1>;
65 #size-cells = <1>; 65 #size-cells = <1>;
66 compatible = "spi-flash"; 66 compatible = "spi-flash";
67 spi-max-frequency = <3000000>; 67 spi-max-frequency = <3000000>;
68 spi-cpol; 68 spi-cpol;
69 spi-cpha; 69 spi-cpha;
70 reg = <0>; 70 reg = <0>;
71 }; 71 };
72 72
73 dflash4: en25s64 { 73 dflash4: en25s64 {
74 #address-cells = <1>; 74 #address-cells = <1>;
75 #size-cells = <1>; 75 #size-cells = <1>;
76 compatible = "spi-flash"; 76 compatible = "spi-flash";
77 spi-max-frequency = <3000000>; 77 spi-max-frequency = <3000000>;
78 spi-cpol; 78 spi-cpol;
79 spi-cpha; 79 spi-cpha;
80 reg = <1>; 80 reg = <1>;
81 }; 81 };
82 dflash5: n25q128a { 82 dflash5: n25q128a {
83 #address-cells = <1>; 83 #address-cells = <1>;
84 #size-cells = <1>; 84 #size-cells = <1>;
85 compatible = "spi-flash"; 85 compatible = "spi-flash";
86 spi-max-frequency = <3000000>; 86 spi-max-frequency = <3000000>;
87 spi-cpol; 87 spi-cpol;
88 spi-cpha; 88 spi-cpha;
89 reg = <2>; 89 reg = <2>;
90 }; 90 };
91 }; 91 };
92 92
93 &dspi2 { 93 &dspi2 {
94 bus-num = <0>; 94 bus-num = <0>;
95 status = "okay"; 95 status = "okay";
96 96
97 dflash8: en25s64 { 97 dflash8: en25s64 {
98 #address-cells = <1>; 98 #address-cells = <1>;
99 #size-cells = <1>; 99 #size-cells = <1>;
100 compatible = "spi-flash"; 100 compatible = "spi-flash";
101 spi-max-frequency = <3000000>; 101 spi-max-frequency = <3000000>;
102 spi-cpol; 102 spi-cpol;
103 spi-cpha; 103 spi-cpha;
104 reg = <0>; 104 reg = <0>;
105 }; 105 };
106 }; 106 };
107 107
108 &esdhc0 { 108 &esdhc0 {
109 status = "okay"; 109 status = "okay";
110 }; 110 };
111 111
112 &esdhc1 { 112 &esdhc1 {
113 status = "okay"; 113 status = "okay";
114 114
115 }; 115 };
116 116
117 &fspi { 117 &fspi {
118 status = "okay"; 118 status = "okay";
119 119
120 mt35xu02g0: flash@0 { 120 mt35xu02g0: flash@0 {
121 #address-cells = <1>; 121 #address-cells = <1>;
122 #size-cells = <1>; 122 #size-cells = <1>;
123 compatible = "jedec,spi-nor"; 123 compatible = "jedec,spi-nor";
124 spi-max-frequency = <50000000>; 124 spi-max-frequency = <50000000>;
125 reg = <0>; 125 reg = <0>;
126 spi-rx-bus-width = <8>; 126 spi-rx-bus-width = <8>;
127 spi-tx-bus-width = <1>; 127 spi-tx-bus-width = <1>;
128 }; 128 };
129 }; 129 };
130 130
131 &i2c0 { 131 &i2c0 {
132 status = "okay"; 132 status = "okay";
133 u-boot,dm-pre-reloc; 133 u-boot,dm-pre-reloc;
134 134
135 fpga@66 { 135 fpga@66 {
136 #address-cells = <1>; 136 #address-cells = <1>;
137 #size-cells = <0>; 137 #size-cells = <0>;
138 compatible = "simple-mfd"; 138 compatible = "simple-mfd";
139 reg = <0x66>; 139 reg = <0x66>;
140 140
141 mux-mdio@54 { 141 mux-mdio@54 {
142 #address-cells = <1>; 142 #address-cells = <1>;
143 #size-cells = <0>; 143 #size-cells = <0>;
144 compatible = "mdio-mux-i2creg"; 144 compatible = "mdio-mux-i2creg";
145 reg = <0x54>; 145 reg = <0x54>;
146 #mux-control-cells = <1>; 146 #mux-control-cells = <1>;
147 mux-reg-masks = <0x54 0xf0>; 147 mux-reg-masks = <0x54 0xf0>;
148 mdio-parent-bus = <&mdio0>; 148 mdio-parent-bus = <&mdio0>;
149 149
150 /* on-board MDIO with a single RGMII PHY */ 150 /* on-board MDIO with a single RGMII PHY */
151 mdio@00 { 151 mdio@00 {
152 #address-cells = <1>; 152 #address-cells = <1>;
153 #size-cells = <0>; 153 #size-cells = <0>;
154 reg = <0x00>; 154 reg = <0x00>;
155 155
156 qds_phy0: phy@5 { 156 qds_phy0: phy@5 {
157 reg = <5>; 157 reg = <5>;
158 }; 158 };
159 }; 159 };
160 /* slot 1 */ 160 /* slot 1 */
161 slot1: mdio@40 { 161 slot1: mdio@40 {
162 #address-cells = <1>; 162 #address-cells = <1>;
163 #size-cells = <0>; 163 #size-cells = <0>;
164 reg = <0x40>; 164 reg = <0x40>;
165 }; 165 };
166 /* slot 2 */ 166 /* slot 2 */
167 slot2: mdio@50 { 167 slot2: mdio@50 {
168 #address-cells = <1>; 168 #address-cells = <1>;
169 #size-cells = <0>; 169 #size-cells = <0>;
170 reg = <0x50>; 170 reg = <0x50>;
171 }; 171 };
172 /* slot 3 */ 172 /* slot 3 */
173 slot3: mdio@60 { 173 slot3: mdio@60 {
174 #address-cells = <1>; 174 #address-cells = <1>;
175 #size-cells = <0>; 175 #size-cells = <0>;
176 reg = <0x60>; 176 reg = <0x60>;
177 }; 177 };
178 /* slot 4 */ 178 /* slot 4 */
179 slot4: mdio@70 { 179 slot4: mdio@70 {
180 #address-cells = <1>; 180 #address-cells = <1>;
181 #size-cells = <0>; 181 #size-cells = <0>;
182 reg = <0x70>; 182 reg = <0x70>;
183 }; 183 };
184 }; 184 };
185 }; 185 };
186 186
187 i2c-mux@77 { 187 i2c-mux@77 {
188 compatible = "nxp,pca9547"; 188 compatible = "nxp,pca9547";
189 reg = <0x77>; 189 reg = <0x77>;
190 #address-cells = <1>; 190 #address-cells = <1>;
191 #size-cells = <0>; 191 #size-cells = <0>;
192 }; 192 };
193 }; 193 };
194 194
195 &i2c1 { 195 &i2c1 {
196 status = "okay"; 196 status = "okay";
197 197
198 rtc@51 { 198 rtc@51 {
199 compatible = "pcf2127-rtc"; 199 compatible = "pcf2127-rtc";
200 reg = <0x51>; 200 reg = <0x51>;
201 }; 201 };
202 }; 202 };
203 203
204 &i2c2 { 204 &i2c2 {
205 status = "okay"; 205 status = "okay";
206 }; 206 };
207 207
208 &i2c3 { 208 &i2c3 {
209 status = "okay"; 209 status = "okay";
210 }; 210 };
211 211
212 &i2c4 { 212 &i2c4 {
213 status = "okay"; 213 status = "okay";
214 }; 214 };
215 215
216 &i2c5 { 216 &i2c5 {
217 status = "okay"; 217 status = "okay";
218 }; 218 };
219 219
220 &i2c6 { 220 &i2c6 {
221 status = "okay"; 221 status = "okay";
222 }; 222 };
223 223
224 &i2c7 { 224 &i2c7 {
225 status = "okay"; 225 status = "okay";
226 }; 226 };
227 227
228 &lpuart0 { 228 &lpuart0 {
229 status = "okay"; 229 status = "okay";
230 }; 230 };
231 231
232 &sata { 232 &sata {
233 status = "okay"; 233 status = "okay";
234 }; 234 };
235 235
236 &serial0 { 236 &serial0 {
237 status = "okay"; 237 status = "okay";
238 }; 238 };
239 239
240 &serial1 { 240 &serial1 {
241 status = "okay"; 241 status = "okay";
242 }; 242 };
243 243
244 &usb1 { 244 &usb1 {
245 status = "okay"; 245 status = "okay";
246 }; 246 };
247 247
248 &usb2 { 248 &usb2 {
249 status = "okay"; 249 status = "okay";
250 }; 250 };
251 251
252 &enetc1 { 252 &enetc1 {
253 status = "okay"; 253 status = "okay";
254 phy-mode = "rgmii"; 254 phy-mode = "rgmii";
255 phy-handle = <&qds_phy0>; 255 phy-handle = <&qds_phy0>;
256 }; 256 };
257 257
258 &mdio0 { 258 &mdio0 {
259 status = "okay"; 259 status = "okay";
260 }; 260 };
261
262 #include "fsl-ls1028a-qds-8xxx-sch-24801.dtsi"
263 #include "fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi"
261 264
arch/arm/dts/fsl-sch-24801.dtsi
Diff comments   View file @ f31be1e
File was created 1 // SPDX-License-Identifier: GPL-2.0+ OR X11
2 /*
3 * Device tree fragment for RCW SCH-24801 card
4 *
5 * Copyright 2019-2021 NXP Semiconductors
6 */
7
8 /*
9 * SCH-24801 is a 4xSGMII add-on card used with various FSL QDS boards.
10 * It integrates a VSC8234 quad PHY which supports 4 SGMII interfaces.
11 * PHY addresses are 0x1c - 0x1f.
12 * On the card the first port is the top port (farthest from PEX connector).
13 */
14 phy@1c {
15 reg = <0x1c>;
16 };
17
18 phy@1d {
19 reg = <0x1d>;
20 };
21
22 phy@1e {
23 reg = <0x1e>;
24 };
25
26 phy@1f {
27 reg = <0x1f>;
28 };
29
arch/arm/dts/fsl-sch-28021.dtsi
Diff comments   View file @ f31be1e
File was created 1 // SPDX-License-Identifier: GPL-2.0+ OR X11
2 /*
3 * Device tree fragment for RCW SCH-28021 card
4 *
5 * Copyright 2019-2021 NXP Semiconductors
6 */
7
8 /*
9 * SCH-28021 is a QSGMII add-on card used with various FSL QDS boards.
10 * It integrates a VSC8514 quad PHY which supports 4 interfaces muxed on a
11 * single QSGMII lane.
12 * PHY addresses are 0x08 - 0x0b.
13 * On the card the first port is the top port (farthest from PEX connector).
14 */
15 phy@08 {
16 reg = <0x08>;
17 };
18
19 phy@09 {
20 reg = <0x09>;
21 };
22
23 phy@0a {
24 reg = <0x0a>;
25 };
26
27 phy@0b {
28 reg = <0x0b>;
29 };
30
arch/arm/dts/fsl-sch-30841.dtsi
Diff comments   View file @ f31be1e
File was created 1 // SPDX-License-Identifier: GPL-2.0+ OR X11
2 /*
3 * Device tree fragment for RCW SCH-30841 card
4 *
5 * Copyright 2019-2021 NXP Semiconductors
6 */
7
8 /*
9 * SCH-30841 is a 4 port add-on card used with various FSL QDS boards.
10 * It integrates a AQR412C quad PHY which supports 4 interfaces either muxed
11 * together on a single lane or mapped 1:1 to serdes lanes.
12 * It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, XFI.
13 * PHY addresses are 0x00 - 0x03.
14 * On the card the first port is the bottom port (closest to PEX connector).
15 */
16 phy@00 {
17 reg = <0x00>;
18 mdi-reversal = <1>;
19 smb-addr = <0x25>;
20 };
21
22 phy@01 {
23 reg = <0x01>;
24 mdi-reversal = <1>;
25 smb-addr = <0x26>;
26 };
27
28 phy@02 {
29 reg = <0x02>;
30 mdi-reversal = <1>;
31 smb-addr = <0x27>;
32 };
33
34 phy@03 {
35 reg = <0x03>;
36 mdi-reversal = <1>;
37 smb-addr = <0x28>;
38 };
39
arch/arm/dts/fsl-sch-30842.dtsi
Diff comments   View file @ f31be1e
File was created 1 // SPDX-License-Identifier: GPL-2.0+ OR X11
2 /*
3 * Device tree fragment for RCW SCH-30842 card
4 *
5 * Copyright 2019-2021 NXP Semiconductors
6 */
7
8 /*
9 * SCH-30842 is a single port add-on card used with various FSL QDS boards.
10 * It integrates a AQR112 PHY, which supports several protocols - SGMII,
11 * SGMII-2500, USXGMII, XFI.
12 * PHY address is 0x02.
13 */
14 phy@02 {
15 reg = <0x02>;
16 mdi-reversal = <1>;
17 smb-addr = <0x25>;
18 };
19