Eric Lee / smarc-uboot

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Commit ff2b924f39cd6d5b6e66ffcac38b3a7faa5777df

Authored by BJ DevOps Team
2 parents 3e181b83a5 ac43a0cb5b
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

Merge remote-tracking branch 'origin/dn_uboot' into lf_uboot 

* origin/dn_uboot: (14 commits)
  Revert "mmc: move mmc_power_cycle() after controller initialization"
  Revert "mmc: rework mmc_set_initial_state"
  board: freescale: vid.c: add parantheses to fix build warning
  net: pfe_eth: read PFE ESBC header flash with spi_flash_read API
  lx2160a: Fix address for secure boot headers
  ...

Showing 38 changed files Side-by-side Diff

arch/arm/cpu/armv8/fsl-layerscape/fdt.c
Diff comments   View file @ ff2b924
... ... @@ -391,10 +391,13 @@
391 391  
392 392 while (jr_node != -FDT_ERR_NOTFOUND) {
393 393 reg = (fdt32_t *)fdt_getprop(blob, jr_node, "reg", &len);
394   - jr_offset = fdt_read_number(reg, addr_cells);
395   - if (jr_offset == used_jr) {
396   - fdt_del_node(blob, jr_node);
397   - break;
  394 + if(reg != NULL)
  395 + {
  396 + jr_offset = fdt_read_number(reg, addr_cells);
  397 + if (jr_offset == used_jr) {
  398 + fdt_del_node(blob, jr_node);
  399 + break;
  400 + }
398 401 }
399 402 jr_node = fdt_node_offset_by_compatible(blob, jr_node,
400 403 "fsl,sec-v4.0-job-ring");
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
Diff comments   View file @ ff2b924
... ... @@ -180,7 +180,8 @@
180 180 #ifdef CONFIG_FSL_ESDHC
181 181 #if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
182 182 clock = sys_info.freq_cga_m2;
183   -#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A)
  183 +#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) || \
  184 + defined(CONFIG_ARCH_LS2080A)
184 185 clock = sys_info.freq_systembus;
185 186 #endif
186 187 gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV;
board/freescale/common/sys_eeprom.c
Diff comments   View file @ ff2b924
... ... @@ -173,9 +173,11 @@
173 173 struct udevice *dev;
174 174 #ifdef CONFIG_SYS_EEPROM_BUS_NUM
175 175 ret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,
176   - CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev);
  176 + CONFIG_SYS_I2C_EEPROM_ADDR,
  177 + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
177 178 #else
178   - ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev);
  179 + ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,
  180 + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, &dev);
179 181 #endif
180 182 if (!ret)
181 183 ret = dm_i2c_read(dev, 0, (void *)&e, sizeof(e));
board/freescale/common/vid.c
Diff comments   View file @ ff2b924
... ... @@ -967,13 +967,15 @@
967 967 char * const argv[])
968 968 {
969 969 ulong override;
970   -
  970 + int ret = 0;
971 971 if (argc < 2)
972 972 return CMD_RET_USAGE;
973 973  
974   - if (!strict_strtoul(argv[1], 10, &override))
975   - adjust_vdd(override); /* the value is checked by callee */
976   - else
  974 + if (!strict_strtoul(argv[1], 10, &override)) {
  975 + ret = adjust_vdd(override); /* the value is checked by callee */
  976 + if (ret < 0)
  977 + return CMD_RET_FAILURE;
  978 + } else
977 979 return CMD_RET_USAGE;
978 980 return 0;
979 981 }
board/freescale/corenet_ds/eth_hydra.c
Diff comments   View file @ ff2b924
... ... @@ -349,6 +349,9 @@
349 349 }
350 350 break;
351 351 case PHY_INTERFACE_MODE_RGMII:
  352 + case PHY_INTERFACE_MODE_RGMII_TXID:
  353 + case PHY_INTERFACE_MODE_RGMII_RXID:
  354 + case PHY_INTERFACE_MODE_RGMII_ID:
352 355 fdt_status_okay_by_alias(fdt, "emi1_rgmii");
353 356 break;
354 357 default:
... ... @@ -448,6 +451,9 @@
448 451 miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"));
449 452 break;
450 453 case PHY_INTERFACE_MODE_RGMII:
  454 + case PHY_INTERFACE_MODE_RGMII_TXID:
  455 + case PHY_INTERFACE_MODE_RGMII_RXID:
  456 + case PHY_INTERFACE_MODE_RGMII_ID:
451 457 /*
452 458 * If DTSEC4 is RGMII, then it's routed via via EC1 to
453 459 * the first on-board RGMII port. If DTSEC5 is RGMII,
board/freescale/corenet_ds/eth_p4080.c
Diff comments   View file @ ff2b924
... ... @@ -364,6 +364,9 @@
364 364 };
365 365 break;
366 366 case PHY_INTERFACE_MODE_RGMII:
  367 + case PHY_INTERFACE_MODE_RGMII_TXID:
  368 + case PHY_INTERFACE_MODE_RGMII_RXID:
  369 + case PHY_INTERFACE_MODE_RGMII_ID:
367 370 fm_info_set_phy_address(i, 0);
368 371 mdio_mux[i] = EMI1_RGMII;
369 372 fm_info_set_mdio(i,
... ... @@ -431,6 +434,9 @@
431 434 };
432 435 break;
433 436 case PHY_INTERFACE_MODE_RGMII:
  437 + case PHY_INTERFACE_MODE_RGMII_TXID:
  438 + case PHY_INTERFACE_MODE_RGMII_RXID:
  439 + case PHY_INTERFACE_MODE_RGMII_ID:
434 440 fm_info_set_phy_address(i, 0);
435 441 mdio_mux[i] = EMI1_RGMII;
436 442 fm_info_set_mdio(i,
board/freescale/corenet_ds/eth_superhydra.c
Diff comments   View file @ ff2b924
... ... @@ -315,6 +315,9 @@
315 315 }
316 316 break;
317 317 case PHY_INTERFACE_MODE_RGMII:
  318 + case PHY_INTERFACE_MODE_RGMII_TXID:
  319 + case PHY_INTERFACE_MODE_RGMII_RXID:
  320 + case PHY_INTERFACE_MODE_RGMII_ID:
318 321 fdt_status_okay_by_alias(fdt, "hydra_rg");
319 322 debug("Enabled MDIO node hydra_rg\n");
320 323 break;
... ... @@ -351,6 +354,9 @@
351 354 }
352 355 break;
353 356 case PHY_INTERFACE_MODE_RGMII:
  357 + case PHY_INTERFACE_MODE_RGMII_TXID:
  358 + case PHY_INTERFACE_MODE_RGMII_RXID:
  359 + case PHY_INTERFACE_MODE_RGMII_ID:
354 360 fdt_status_okay_by_alias(fdt, "hydra_rg");
355 361 debug("Enabled MDIO node hydra_rg\n");
356 362 break;
... ... @@ -555,6 +561,9 @@
555 561 miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"));
556 562 break;
557 563 case PHY_INTERFACE_MODE_RGMII:
  564 + case PHY_INTERFACE_MODE_RGMII_TXID:
  565 + case PHY_INTERFACE_MODE_RGMII_RXID:
  566 + case PHY_INTERFACE_MODE_RGMII_ID:
558 567 /*
559 568 * FM1 DTSEC5 is routed via EC1 to the first on-board
560 569 * RGMII port. FM2 DTSEC5 is routed via EC2 to the
... ... @@ -702,6 +711,9 @@
702 711  
703 712 break;
704 713 case PHY_INTERFACE_MODE_RGMII:
  714 + case PHY_INTERFACE_MODE_RGMII_TXID:
  715 + case PHY_INTERFACE_MODE_RGMII_RXID:
  716 + case PHY_INTERFACE_MODE_RGMII_ID:
705 717 /*
706 718 * FM1 DTSEC5 is routed via EC1 to the first on-board
707 719 * RGMII port. FM2 DTSEC5 is routed via EC2 to the
board/freescale/ls1012afrdm/Kconfig
Diff comments   View file @ ff2b924
... ... @@ -16,6 +16,10 @@
16 16 hex "Flash address of PFE firmware"
17 17 default 0x40a00000
18 18  
  19 +config SYS_LS_PFE_FW_LENGTH
  20 + hex "length of PFE firmware"
  21 + default 0x40000
  22 +
19 23 config SYS_LS_PPA_FW_ADDR
20 24 hex "PPA Firmware Addr"
21 25 default 0x40400000
... ... @@ -65,6 +69,10 @@
65 69 hex "Flash address of PFE firmware"
66 70 default 0x40020000
67 71  
  72 +config SYS_LS_PFE_FW_LENGTH
  73 + hex "length of PFE firmware"
  74 + default 0x40000
  75 +
68 76 config SYS_LS_PPA_FW_ADDR
69 77 hex "PPA Firmware Addr"
70 78 default 0x40060000
... ... @@ -77,6 +85,9 @@
77 85 hex "PFE Firmware HDR Addr"
78 86 default 0x401f8000
79 87  
  88 +config SYS_LS_PFE_ESBC_LENGTH
  89 + hex "length of PFE Firmware HDR"
  90 + default 0xc00
80 91 endif
81 92  
82 93 if TARGET_LS1012AFRDM || TARGET_LS1012AFRWY
board/freescale/ls1012aqds/Kconfig
Diff comments   View file @ ff2b924
... ... @@ -20,6 +20,14 @@
20 20 config SYS_LS_PPA_ESBC_ADDR
21 21 hex "PPA Firmware HDR Addr"
22 22 default 0x40680000
  23 +
  24 +config SYS_LS_PFE_ESBC_ADDR
  25 + hex "PFE Firmware HDR Addr"
  26 + default 0x40700000
  27 +
  28 +config SYS_LS_PFE_ESBC_LENGTH
  29 + hex "length of PFE Firmware HDR"
  30 + default 0xc00
23 31 endif
24 32  
25 33 if FSL_PFE
... ... @@ -39,9 +47,9 @@
39 47 hex "Flash address of PFE firmware"
40 48 default 0x40a00000
41 49  
42   -config SYS_LS_PFE_ESBC_ADDR
43   - hex "PFE Firmware HDR Addr"
44   - default 0x40700000
  50 +config SYS_LS_PFE_FW_LENGTH
  51 + hex "length of PFE firmware"
  52 + default 0x300000
45 53  
46 54 config DDR_PFE_PHYS_BASEADDR
47 55 hex "PFE DDR physical base address"
board/freescale/ls1012ardb/Kconfig
Diff comments   View file @ ff2b924
... ... @@ -20,6 +20,14 @@
20 20 config SYS_LS_PPA_ESBC_ADDR
21 21 hex "PPA Firmware HDR Addr"
22 22 default 0x40680000
  23 +
  24 +config SYS_LS_PFE_ESBC_ADDR
  25 + hex "PFE Firmware HDR Addr"
  26 + default 0x40640000
  27 +
  28 +config SYS_LS_PFE_ESBC_LENGTH
  29 + hex "length of PFE Firmware HDR"
  30 + default 0xc00
23 31 endif
24 32  
25 33 if FSL_PFE
... ... @@ -33,9 +41,9 @@
33 41 hex "Flash address of PFE firmware"
34 42 default 0x40a00000
35 43  
36   -config SYS_LS_PFE_ESBC_ADDR
37   - hex "PFE Firmware HDR Addr"
38   - default 0x40640000
  44 +config SYS_LS_PFE_FW_LENGTH
  45 + hex "length of PFE firmware"
  46 + default 0x300000
39 47  
40 48 config DDR_PFE_PHYS_BASEADDR
41 49 hex "PFE DDR physical base address"
... ... @@ -88,6 +96,10 @@
88 96 config SYS_LS_PFE_FW_ADDR
89 97 hex "Flash address of PFE firmware"
90 98 default 0x40a00000
  99 +
  100 +config SYS_LS_PFE_FW_LENGTH
  101 + hex "length of PFE firmware"
  102 + default 0x300000
91 103  
92 104 config DDR_PFE_PHYS_BASEADDR
93 105 hex "PFE DDR physical base address"
board/freescale/ls1043aqds/eth.c
Diff comments   View file @ ff2b924
... ... @@ -477,6 +477,8 @@
477 477 break;
478 478 case PHY_INTERFACE_MODE_RGMII:
479 479 case PHY_INTERFACE_MODE_RGMII_TXID:
  480 + case PHY_INTERFACE_MODE_RGMII_RXID:
  481 + case PHY_INTERFACE_MODE_RGMII_ID:
480 482 if (i == FM1_DTSEC3)
481 483 mdio_mux[i] = EMI1_RGMII1;
482 484 else if (i == FM1_DTSEC4)
board/freescale/ls1046aqds/eth.c
Diff comments   View file @ ff2b924
... ... @@ -412,6 +412,8 @@
412 412 break;
413 413 case PHY_INTERFACE_MODE_RGMII:
414 414 case PHY_INTERFACE_MODE_RGMII_TXID:
  415 + case PHY_INTERFACE_MODE_RGMII_RXID:
  416 + case PHY_INTERFACE_MODE_RGMII_ID:
415 417 if (i == FM1_DTSEC3)
416 418 mdio_mux[i] = EMI1_RGMII1;
417 419 else if (i == FM1_DTSEC4)
board/freescale/p2041rdb/eth.c
Diff comments   View file @ ff2b924
... ... @@ -80,17 +80,21 @@
80 80 {
81 81 phy_interface_t intf = fm_info_get_enet_if(port);
82 82 char phy[16];
  83 + int lane;
  84 + u8 slot;
83 85  
  86 + switch (intf) {
84 87 /* The RGMII PHY is identified by the MAC connected to it */
85   - if (intf == PHY_INTERFACE_MODE_RGMII) {
  88 + case PHY_INTERFACE_MODE_RGMII:
  89 + case PHY_INTERFACE_MODE_RGMII_TXID:
  90 + case PHY_INTERFACE_MODE_RGMII_RXID:
  91 + case PHY_INTERFACE_MODE_RGMII_ID:
86 92 sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC5 ? 0 : 1);
87 93 fdt_set_phy_handle(fdt, compat, addr, phy);
88   - }
89   -
  94 + break;
90 95 /* The SGMII PHY is identified by the MAC connected to it */
91   - if (intf == PHY_INTERFACE_MODE_SGMII) {
92   - int lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);
93   - u8 slot;
  96 + case PHY_INTERFACE_MODE_SGMII:
  97 + lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port);
94 98 if (lane < 0)
95 99 return;
96 100 slot = lane_to_slot[lane];
97 101  
98 102  
... ... @@ -105,16 +109,18 @@
105 109 + (port - FM1_DTSEC1));
106 110 fdt_set_phy_handle(fdt, compat, addr, phy);
107 111 }
108   - }
109   -
110   - if (intf == PHY_INTERFACE_MODE_XGMII) {
  112 + break;
  113 + case PHY_INTERFACE_MODE_XGMII:
111 114 /* XAUI */
112   - int lane = serdes_get_first_lane(XAUI_FM1);
  115 + lane = serdes_get_first_lane(XAUI_FM1);
113 116 if (lane >= 0) {
114 117 /* The XAUI PHY is identified by the slot */
115 118 sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
116 119 fdt_set_phy_handle(fdt, compat, addr, phy);
117 120 }
  121 + break;
  122 + default:
  123 + break;
118 124 }
119 125 }
120 126 #endif /* #ifdef CONFIG_FMAN_ENET */
... ... @@ -168,6 +174,9 @@
168 174 fm_info_set_phy_address(i, riser_phy_addr[i]);
169 175 break;
170 176 case PHY_INTERFACE_MODE_RGMII:
  177 + case PHY_INTERFACE_MODE_RGMII_TXID:
  178 + case PHY_INTERFACE_MODE_RGMII_RXID:
  179 + case PHY_INTERFACE_MODE_RGMII_ID:
171 180 /* Only DTSEC4 and DTSEC5 can be routed to RGMII */
172 181 fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
173 182 CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
board/freescale/t102xqds/eth_t102xqds.c
Diff comments   View file @ ff2b924
... ... @@ -168,14 +168,19 @@
168 168 {
169 169 struct fixed_link f_link;
170 170  
171   - if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_RGMII) {
  171 + switch (fm_info_get_enet_if(port)) {
  172 + case PHY_INTERFACE_MODE_RGMII:
  173 + case PHY_INTERFACE_MODE_RGMII_TXID:
  174 + case PHY_INTERFACE_MODE_RGMII_RXID:
  175 + case PHY_INTERFACE_MODE_RGMII_ID:
172 176 if (port == FM1_DTSEC3) {
173 177 fdt_set_phy_handle(fdt, compat, addr, "rgmii_phy2");
174 178 fdt_setprop_string(fdt, offset, "phy-connection-type",
175 179 "rgmii");
176 180 fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
177 181 }
178   - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
  182 + break;
  183 + case PHY_INTERFACE_MODE_SGMII:
179 184 if (port == FM1_DTSEC1) {
180 185 fdt_set_phy_handle(fdt, compat, addr,
181 186 "sgmii_vsc8234_phy_s5");
182 187  
... ... @@ -183,12 +188,14 @@
183 188 fdt_set_phy_handle(fdt, compat, addr,
184 189 "sgmii_vsc8234_phy_s4");
185 190 }
186   - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
  191 + break;
  192 + case PHY_INTERFACE_MODE_SGMII_2500:
187 193 if (port == FM1_DTSEC3) {
188 194 fdt_set_phy_handle(fdt, compat, addr,
189 195 "sgmii_aqr105_phy_s3");
190 196 }
191   - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
  197 + break;
  198 + case PHY_INTERFACE_MODE_QSGMII:
192 199 switch (port) {
193 200 case FM1_DTSEC1:
194 201 fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p1");
... ... @@ -209,7 +216,8 @@
209 216 fdt_setprop_string(fdt, offset, "phy-connection-type",
210 217 "qsgmii");
211 218 fdt_status_okay_by_alias(fdt, "emi1_slot2");
212   - } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
  219 + break;
  220 + case PHY_INTERFACE_MODE_XGMII:
213 221 /* XFI interface */
214 222 f_link.phy_id = port;
215 223 f_link.duplex = 1;
... ... @@ -220,6 +228,9 @@
220 228 fdt_delprop(fdt, offset, "phy-handle");
221 229 fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
222 230 fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
  231 + break;
  232 + default:
  233 + break;
223 234 }
224 235 }
225 236  
... ... @@ -408,6 +419,9 @@
408 419 }
409 420 break;
410 421 case PHY_INTERFACE_MODE_RGMII:
  422 + case PHY_INTERFACE_MODE_RGMII_TXID:
  423 + case PHY_INTERFACE_MODE_RGMII_RXID:
  424 + case PHY_INTERFACE_MODE_RGMII_ID:
411 425 if (i == FM1_DTSEC3)
412 426 mdio_mux[i] = EMI1_RGMII2;
413 427 else if (i == FM1_DTSEC4)
board/freescale/t102xrdb/eth_t102xrdb.c
Diff comments   View file @ ff2b924
... ... @@ -87,6 +87,9 @@
87 87 interface = fm_info_get_enet_if(i);
88 88 switch (interface) {
89 89 case PHY_INTERFACE_MODE_RGMII:
  90 + case PHY_INTERFACE_MODE_RGMII_TXID:
  91 + case PHY_INTERFACE_MODE_RGMII_RXID:
  92 + case PHY_INTERFACE_MODE_RGMII_ID:
90 93 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
91 94 fm_info_set_mdio(i, dev);
92 95 break;
board/freescale/t1040qds/eth.c
Diff comments   View file @ ff2b924
... ... @@ -288,14 +288,17 @@
288 288 phy_interface_t intf = fm_info_get_enet_if(port);
289 289 char phy[16];
290 290  
  291 + switch (intf) {
291 292 /* The RGMII PHY is identified by the MAC connected to it */
292   - if (intf == PHY_INTERFACE_MODE_RGMII) {
  293 + case PHY_INTERFACE_MODE_RGMII:
  294 + case PHY_INTERFACE_MODE_RGMII_TXID:
  295 + case PHY_INTERFACE_MODE_RGMII_RXID:
  296 + case PHY_INTERFACE_MODE_RGMII_ID:
293 297 sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2);
294 298 fdt_set_phy_handle(fdt, compat, addr, phy);
295   - }
296   -
  299 + break;
297 300 /* The SGMII PHY is identified by the MAC connected to it */
298   - if (intf == PHY_INTERFACE_MODE_SGMII) {
  301 + case PHY_INTERFACE_MODE_SGMII:
299 302 int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1
300 303 + port);
301 304 u8 slot;
... ... @@ -309,6 +312,9 @@
309 312 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1));
310 313 fdt_set_phy_handle(fdt, compat, addr, phy);
311 314 }
  315 + break;
  316 + default:
  317 + break;
312 318 }
313 319 }
314 320  
... ... @@ -341,6 +347,9 @@
341 347 }
342 348 break;
343 349 case PHY_INTERFACE_MODE_RGMII:
  350 + case PHY_INTERFACE_MODE_RGMII_TXID:
  351 + case PHY_INTERFACE_MODE_RGMII_RXID:
  352 + case PHY_INTERFACE_MODE_RGMII_ID:
344 353 if (i == FM1_DTSEC4)
345 354 fdt_status_okay_by_alias(fdt, "emi1_rgmii0");
346 355  
... ... @@ -491,6 +500,9 @@
491 500 break;
492 501  
493 502 case PHY_INTERFACE_MODE_RGMII:
  503 + case PHY_INTERFACE_MODE_RGMII_TXID:
  504 + case PHY_INTERFACE_MODE_RGMII_RXID:
  505 + case PHY_INTERFACE_MODE_RGMII_ID:
494 506 /* Only DTSEC4 and DTSEC5 can be routed to RGMII */
495 507 t1040_handle_phy_interface_rgmii(i);
496 508 break;
board/freescale/t104xrdb/eth.c
Diff comments   View file @ ff2b924
... ... @@ -76,6 +76,9 @@
76 76 break;
77 77 #endif
78 78 case PHY_INTERFACE_MODE_RGMII:
  79 + case PHY_INTERFACE_MODE_RGMII_TXID:
  80 + case PHY_INTERFACE_MODE_RGMII_RXID:
  81 + case PHY_INTERFACE_MODE_RGMII_ID:
79 82 if (FM1_DTSEC4 == i)
80 83 phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
81 84 if (FM1_DTSEC5 == i)
board/freescale/t208xqds/eth_t208xqds.c
Diff comments   View file @ ff2b924
... ... @@ -750,6 +750,9 @@
750 750 }
751 751 break;
752 752 case PHY_INTERFACE_MODE_RGMII:
  753 + case PHY_INTERFACE_MODE_RGMII_TXID:
  754 + case PHY_INTERFACE_MODE_RGMII_RXID:
  755 + case PHY_INTERFACE_MODE_RGMII_ID:
753 756 if (i == FM1_DTSEC3)
754 757 mdio_mux[i] = EMI1_RGMII1;
755 758 else if (i == FM1_DTSEC4 || FM1_DTSEC10)
board/freescale/t208xrdb/eth_t208xrdb.c
Diff comments   View file @ ff2b924
... ... @@ -74,6 +74,9 @@
74 74 interface = fm_info_get_enet_if(i);
75 75 switch (interface) {
76 76 case PHY_INTERFACE_MODE_RGMII:
  77 + case PHY_INTERFACE_MODE_RGMII_TXID:
  78 + case PHY_INTERFACE_MODE_RGMII_RXID:
  79 + case PHY_INTERFACE_MODE_RGMII_ID:
77 80 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
78 81 fm_info_set_mdio(i, dev);
79 82 break;
board/freescale/t4qds/eth.c
Diff comments   View file @ ff2b924
... ... @@ -638,6 +638,9 @@
638 638 };
639 639 break;
640 640 case PHY_INTERFACE_MODE_RGMII:
  641 + case PHY_INTERFACE_MODE_RGMII_TXID:
  642 + case PHY_INTERFACE_MODE_RGMII_RXID:
  643 + case PHY_INTERFACE_MODE_RGMII_ID:
641 644 /* FM1 DTSEC5 routes to RGMII with EC2 */
642 645 debug("FM1@DTSEC%u is RGMII at address %u\n",
643 646 idx + 1, 2);
... ... @@ -816,6 +819,9 @@
816 819 };
817 820 break;
818 821 case PHY_INTERFACE_MODE_RGMII:
  822 + case PHY_INTERFACE_MODE_RGMII_TXID:
  823 + case PHY_INTERFACE_MODE_RGMII_RXID:
  824 + case PHY_INTERFACE_MODE_RGMII_ID:
819 825 /*
820 826 * If DTSEC5 is RGMII, then it's routed via via EC1 to
821 827 * the first on-board RGMII port. If DTSEC6 is RGMII,
configs/ls1088aqds_defconfig
Diff comments   View file @ ff2b924
... ... @@ -42,8 +42,14 @@
42 42 CONFIG_SYS_FLASH_CFI=y
43 43 CONFIG_MTD_RAW_NAND=y
44 44 CONFIG_DM_SPI_FLASH=y
  45 +CONFIG_PHYLIB=y
  46 +CONFIG_PHY_AQUANTIA=y
  47 +CONFIG_PHY_REALTEK=y
  48 +CONFIG_PHY_TERANETICS=y
  49 +CONFIG_PHY_VITESSE=y
45 50 CONFIG_E1000=y
46 51 CONFIG_MII=y
  52 +CONFIG_NVME=y
47 53 CONFIG_PCI=y
48 54 CONFIG_DM_PCI=y
49 55 CONFIG_DM_PCI_COMPAT=y
... ... @@ -59,6 +65,4 @@
59 65 CONFIG_USB_DWC3=y
60 66 CONFIG_USB_STORAGE=y
61 67 CONFIG_USB_GADGET=y
62   -CONFIG_CMD_NVME=y
63   -CONFIG_NVME=y
configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
Diff comments   View file @ ff2b924
... ... @@ -39,8 +39,14 @@
39 39 # CONFIG_SPI_FLASH_BAR is not set
40 40 CONFIG_SPI_FLASH_SPANSION=y
41 41 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  42 +CONFIG_PHYLIB=y
  43 +CONFIG_PHY_AQUANTIA=y
  44 +CONFIG_PHY_REALTEK=y
  45 +CONFIG_PHY_TERANETICS=y
  46 +CONFIG_PHY_VITESSE=y
42 47 CONFIG_E1000=y
43 48 CONFIG_MII=y
  49 +CONFIG_NVME=y
44 50 CONFIG_PCI=y
45 51 CONFIG_DM_PCI=y
46 52 CONFIG_DM_PCI_COMPAT=y
... ... @@ -60,6 +66,4 @@
60 66 CONFIG_RSA=y
61 67 CONFIG_RSA_SOFTWARE_EXP=y
62 68 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
63   -CONFIG_CMD_NVME=y
64   -CONFIG_NVME=y
configs/ls1088aqds_qspi_defconfig
Diff comments   View file @ ff2b924
... ... @@ -42,8 +42,14 @@
42 42 # CONFIG_SPI_FLASH_BAR is not set
43 43 CONFIG_SPI_FLASH_SPANSION=y
44 44 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  45 +CONFIG_PHYLIB=y
  46 +CONFIG_PHY_AQUANTIA=y
  47 +CONFIG_PHY_REALTEK=y
  48 +CONFIG_PHY_TERANETICS=y
  49 +CONFIG_PHY_VITESSE=y
45 50 CONFIG_E1000=y
46 51 CONFIG_MII=y
  52 +CONFIG_NVME=y
47 53 CONFIG_PCI=y
48 54 CONFIG_DM_PCI=y
49 55 CONFIG_DM_PCI_COMPAT=y
... ... @@ -61,6 +67,4 @@
61 67 CONFIG_USB_DWC3=y
62 68 CONFIG_USB_GADGET=y
63 69 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
64   -CONFIG_CMD_NVME=y
65   -CONFIG_NVME=y
configs/ls1088aqds_sdcard_ifc_defconfig
Diff comments   View file @ ff2b924
... ... @@ -52,8 +52,14 @@
52 52 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
53 53 CONFIG_SYS_FLASH_CFI=y
54 54 CONFIG_MTD_RAW_NAND=y
  55 +CONFIG_PHYLIB=y
  56 +CONFIG_PHY_AQUANTIA=y
  57 +CONFIG_PHY_REALTEK=y
  58 +CONFIG_PHY_TERANETICS=y
  59 +CONFIG_PHY_VITESSE=y
55 60 CONFIG_E1000=y
56 61 CONFIG_MII=y
  62 +CONFIG_NVME=y
57 63 CONFIG_PCI=y
58 64 CONFIG_DM_PCI=y
59 65 CONFIG_DM_PCI_COMPAT=y
... ... @@ -67,6 +73,4 @@
67 73 CONFIG_USB_DWC3=y
68 74 CONFIG_USB_STORAGE=y
69 75 CONFIG_USB_GADGET=y
70   -CONFIG_CMD_NVME=y
71   -CONFIG_NVME=y
configs/ls1088aqds_sdcard_qspi_defconfig
Diff comments   View file @ ff2b924
... ... @@ -52,8 +52,14 @@
52 52 # CONFIG_SPI_FLASH_BAR is not set
53 53 CONFIG_SPI_FLASH_SPANSION=y
54 54 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  55 +CONFIG_PHYLIB=y
  56 +CONFIG_PHY_AQUANTIA=y
  57 +CONFIG_PHY_REALTEK=y
  58 +CONFIG_PHY_TERANETICS=y
  59 +CONFIG_PHY_VITESSE=y
55 60 CONFIG_E1000=y
56 61 CONFIG_MII=y
  62 +CONFIG_NVME=y
57 63 CONFIG_PCI=y
58 64 CONFIG_DM_PCI=y
59 65 CONFIG_DM_PCI_COMPAT=y
... ... @@ -70,6 +76,4 @@
70 76 CONFIG_USB_XHCI_DWC3=y
71 77 CONFIG_USB_DWC3=y
72 78 CONFIG_USB_GADGET=y
73   -CONFIG_CMD_NVME=y
74   -CONFIG_NVME=y
configs/ls1088aqds_tfa_defconfig
Diff comments   View file @ ff2b924
... ... @@ -57,8 +57,14 @@
57 57 # CONFIG_SPI_FLASH_BAR is not set
58 58 CONFIG_SPI_FLASH_SPANSION=y
59 59 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  60 +CONFIG_PHYLIB=y
  61 +CONFIG_PHY_AQUANTIA=y
  62 +CONFIG_PHY_REALTEK=y
  63 +CONFIG_PHY_TERANETICS=y
  64 +CONFIG_PHY_VITESSE=y
60 65 CONFIG_E1000=y
61 66 CONFIG_MII=y
  67 +CONFIG_NVME=y
62 68 CONFIG_PCI=y
63 69 CONFIG_DM_PCI=y
64 70 CONFIG_DM_PCI_COMPAT=y
... ... @@ -78,6 +84,4 @@
78 84 CONFIG_USB_DWC3=y
79 85 CONFIG_USB_GADGET=y
80 86 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
81   -CONFIG_CMD_NVME=y
82   -CONFIG_NVME=y
configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
Diff comments   View file @ ff2b924
... ... @@ -40,8 +40,14 @@
40 40 # CONFIG_SPI_FLASH_BAR is not set
41 41 CONFIG_SPI_FLASH_SPANSION=y
42 42 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  43 +CONFIG_PHYLIB=y
  44 +CONFIG_PHY_AQUANTIA=y
  45 +CONFIG_PHY_REALTEK=y
  46 +CONFIG_PHY_TERANETICS=y
  47 +CONFIG_PHY_VITESSE=y
43 48 CONFIG_E1000=y
44 49 CONFIG_MII=y
  50 +CONFIG_NVME=y
45 51 CONFIG_PCI=y
46 52 CONFIG_DM_PCI=y
47 53 CONFIG_DM_PCI_COMPAT=y
... ... @@ -61,6 +67,4 @@
61 67 CONFIG_RSA=y
62 68 CONFIG_RSA_SOFTWARE_EXP=y
63 69 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
64   -CONFIG_CMD_NVME=y
65   -CONFIG_NVME=y
configs/ls1088ardb_qspi_defconfig
Diff comments   View file @ ff2b924
... ... @@ -43,8 +43,14 @@
43 43 # CONFIG_SPI_FLASH_BAR is not set
44 44 CONFIG_SPI_FLASH_SPANSION=y
45 45 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  46 +CONFIG_PHYLIB=y
  47 +CONFIG_PHY_AQUANTIA=y
  48 +CONFIG_PHY_REALTEK=y
  49 +CONFIG_PHY_TERANETICS=y
  50 +CONFIG_PHY_VITESSE=y
46 51 CONFIG_E1000=y
47 52 CONFIG_MII=y
  53 +CONFIG_NVME=y
48 54 CONFIG_PCI=y
49 55 CONFIG_DM_PCI=y
50 56 CONFIG_DM_PCI_COMPAT=y
... ... @@ -62,6 +68,4 @@
62 68 CONFIG_USB_DWC3=y
63 69 CONFIG_USB_GADGET=y
64 70 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
65   -CONFIG_CMD_NVME=y
66   -CONFIG_NVME=y
configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
Diff comments   View file @ ff2b924
... ... @@ -52,6 +52,11 @@
52 52 # CONFIG_SPI_FLASH_BAR is not set
53 53 CONFIG_SPI_FLASH_SPANSION=y
54 54 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  55 +CONFIG_PHYLIB=y
  56 +CONFIG_PHY_AQUANTIA=y
  57 +CONFIG_PHY_REALTEK=y
  58 +CONFIG_PHY_TERANETICS=y
  59 +CONFIG_PHY_VITESSE=y
55 60 CONFIG_E1000=y
56 61 CONFIG_MII=y
57 62 CONFIG_PCI=y
... ... @@ -70,6 +75,4 @@
70 75 CONFIG_USB_DWC3=y
71 76 CONFIG_RSA=y
72 77 CONFIG_SPL_RSA=y
73   -CONFIG_CMD_NVME=y
74   -CONFIG_NVME=y
configs/ls1088ardb_sdcard_qspi_defconfig
Diff comments   View file @ ff2b924
... ... @@ -53,8 +53,14 @@
53 53 # CONFIG_SPI_FLASH_BAR is not set
54 54 CONFIG_SPI_FLASH_SPANSION=y
55 55 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  56 +CONFIG_PHYLIB=y
  57 +CONFIG_PHY_AQUANTIA=y
  58 +CONFIG_PHY_REALTEK=y
  59 +CONFIG_PHY_TERANETICS=y
  60 +CONFIG_PHY_VITESSE=y
56 61 CONFIG_E1000=y
57 62 CONFIG_MII=y
  63 +CONFIG_NVME=y
58 64 CONFIG_PCI=y
59 65 CONFIG_DM_PCI=y
60 66 CONFIG_DM_PCI_COMPAT=y
... ... @@ -71,6 +77,4 @@
71 77 CONFIG_USB_XHCI_DWC3=y
72 78 CONFIG_USB_DWC3=y
73 79 CONFIG_USB_GADGET=y
74   -CONFIG_CMD_NVME=y
75   -CONFIG_NVME=y
configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
Diff comments   View file @ ff2b924
... ... @@ -47,8 +47,12 @@
47 47 # CONFIG_SPI_FLASH_BAR is not set
48 48 CONFIG_SPI_FLASH_SPANSION=y
49 49 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  50 +CONFIG_PHYLIB=y
  51 +CONFIG_PHY_AQUANTIA=y
  52 +CONFIG_PHY_VITESSE=y
50 53 CONFIG_E1000=y
51 54 CONFIG_MII=y
  55 +CONFIG_NVME=y
52 56 CONFIG_PCI=y
53 57 CONFIG_DM_PCI=y
54 58 CONFIG_DM_PCI_COMPAT=y
... ... @@ -71,6 +75,4 @@
71 75 CONFIG_SPL_RSA=y
72 76 CONFIG_RSA_SOFTWARE_EXP=y
73 77 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
74   -CONFIG_CMD_NVME=y
75   -CONFIG_NVME=y
configs/ls1088ardb_tfa_defconfig
Diff comments   View file @ ff2b924
... ... @@ -52,8 +52,12 @@
52 52 # CONFIG_SPI_FLASH_BAR is not set
53 53 CONFIG_SPI_FLASH_SPANSION=y
54 54 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  55 +CONFIG_PHYLIB=y
  56 +CONFIG_PHY_AQUANTIA=y
  57 +CONFIG_PHY_VITESSE=y
55 58 CONFIG_E1000=y
56 59 CONFIG_MII=y
  60 +CONFIG_NVME=y
57 61 CONFIG_PCI=y
58 62 CONFIG_DM_PCI=y
59 63 CONFIG_DM_PCI_COMPAT=y
... ... @@ -77,6 +81,4 @@
77 81 CONFIG_USB_ETHER_ASIX88179=y
78 82 CONFIG_USB_ETHER_RTL8152=y
79 83 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
80   -CONFIG_CMD_NVME=y
81   -CONFIG_NVME=y
... ... @@ -2697,19 +2697,16 @@
2697 2697 {
2698 2698 int err;
2699 2699  
2700   - mmc->signal_voltage = MMC_SIGNAL_VOLTAGE_330;
2701   - mmc_select_mode(mmc, MMC_LEGACY);
2702   - mmc->bus_width = 1;
2703   - mmc->clock = 0;
2704   - mmc->clk_disable = MMC_CLK_ENABLE;
  2700 + /* First try to set 3.3V. If it fails set to 1.8V */
  2701 + err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
  2702 + if (err != 0)
  2703 + err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
  2704 + if (err != 0)
  2705 + pr_warn("mmc: failed to set signal voltage\n");
2705 2706  
2706   - err = mmc_set_ios(mmc);
2707   - if (err)
2708   - mmc->signal_voltage = MMC_SIGNAL_VOLTAGE_180;
2709   -
2710   - err = mmc_set_ios(mmc);
2711   - if (err)
2712   - pr_warn("mmc: failed to set initial state\n");
  2707 + mmc_select_mode(mmc, MMC_LEGACY);
  2708 + mmc_set_bus_width(mmc, 1);
  2709 + mmc_set_clock(mmc, 0, MMC_CLK_ENABLE);
2713 2710 }
2714 2711  
2715 2712 static int mmc_power_on(struct mmc *mmc)
... ... @@ -2781,6 +2778,21 @@
2781 2778 MMC_QUIRK_RETRY_APP_CMD;
2782 2779 #endif
2783 2780  
  2781 + err = mmc_power_cycle(mmc);
  2782 + if (err) {
  2783 + /*
  2784 + * if power cycling is not supported, we should not try
  2785 + * to use the UHS modes, because we wouldn't be able to
  2786 + * recover from an error during the UHS initialization.
  2787 + */
  2788 + pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
  2789 + uhs_en = false;
  2790 + mmc->host_caps &= ~UHS_CAPS;
  2791 + err = mmc_power_on(mmc);
  2792 + }
  2793 + if (err)
  2794 + return err;
  2795 +
2784 2796 #if CONFIG_IS_ENABLED(DM_MMC)
2785 2797 /*
2786 2798 * Re-initialization is needed to clear old configuration for
... ... @@ -2798,21 +2810,6 @@
2798 2810 retry:
2799 2811 mmc_set_initial_state(mmc);
2800 2812  
2801   - err = mmc_power_cycle(mmc);
2802   - if (err) {
2803   - /*
2804   - * if power cycling is not supported, we should not try
2805   - * to use the UHS modes, because we wouldn't be able to
2806   - * recover from an error during the UHS initialization.
2807   - */
2808   - pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
2809   - uhs_en = false;
2810   - mmc->host_caps &= ~UHS_CAPS;
2811   - err = mmc_power_on(mmc);
2812   - }
2813   - if (err)
2814   - return err;
2815   -
2816 2813 /* Reset the Card */
2817 2814 err = mmc_go_idle(mmc);
2818 2815  
... ... @@ -2829,6 +2826,7 @@
2829 2826 err = sd_send_op_cond(mmc, uhs_en);
2830 2827 if (err && uhs_en) {
2831 2828 uhs_en = false;
  2829 + mmc_power_cycle(mmc);
2832 2830 goto retry;
2833 2831 }
2834 2832  
drivers/net/pfe_eth/pfe_firmware.c
Diff comments   View file @ ff2b924
1 1 // SPDX-License-Identifier: GPL-2.0+
2 2 /*
3 3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
4   - * Copyright 2017 NXP
  4 + * Copyright 2017,2020 NXP
5 5 */
6 6  
7 7 /*
... ... @@ -10,6 +10,8 @@
10 10 * files.
11 11 */
12 12  
  13 +#include <dm.h>
  14 +#include <dm/device-internal.h>
13 15 #include <malloc.h>
14 16 #include <net/pfe_eth/pfe_eth.h>
15 17 #include <net/pfe_eth/pfe_firmware.h>
... ... @@ -21,6 +23,9 @@
21 23 #define PFE_FIRMWARE_FIT_CNF_NAME "config@1"
22 24  
23 25 static const void *pfe_fit_addr;
  26 +#ifdef CONFIG_CHAIN_OF_TRUST
  27 +static const void *pfe_esbc_hdr_addr;
  28 +#endif
24 29  
25 30 /*
26 31 * PFE elf firmware loader.
... ... @@ -165,7 +170,7 @@
165 170 {
166 171 struct spi_flash *pfe_flash;
167 172 int ret = 0;
168   - void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
  173 + void *addr = malloc(CONFIG_SYS_LS_PFE_FW_LENGTH);
169 174  
170 175 if (!addr)
171 176 return -ENOMEM;
... ... @@ -176,6 +181,12 @@
176 181 /* speed and mode will be read from DT */
177 182 ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS,
178 183 CONFIG_ENV_SPI_CS, 0, 0, &new);
  184 + if (ret) {
  185 + printf("SF: failed to probe spi\n");
  186 + free(addr);
  187 + device_remove(new, DM_REMOVE_NORMAL);
  188 + return ret;
  189 + }
179 190  
180 191 pfe_flash = dev_get_uclass_priv(new);
181 192 #else
182 193  
183 194  
184 195  
185 196  
... ... @@ -187,16 +198,47 @@
187 198 if (!pfe_flash) {
188 199 printf("SF: probe for pfe failed\n");
189 200 free(addr);
  201 +#ifdef CONFIG_DM_SPI_FLASH
  202 + device_remove(new, DM_REMOVE_NORMAL);
  203 +#endif
190 204 return -ENODEV;
191 205 }
192 206  
193 207 ret = spi_flash_read(pfe_flash,
194 208 CONFIG_SYS_LS_PFE_FW_ADDR,
195   - CONFIG_SYS_QE_FMAN_FW_LENGTH,
  209 + CONFIG_SYS_LS_PFE_FW_LENGTH,
196 210 addr);
197   - if (ret)
  211 + if (ret) {
198 212 printf("SF: read for pfe failed\n");
  213 + free(addr);
  214 + spi_flash_free(pfe_flash);
  215 + return ret;
  216 + }
199 217  
  218 +#ifdef CONFIG_CHAIN_OF_TRUST
  219 + void *hdr_addr = malloc(CONFIG_SYS_LS_PFE_ESBC_LENGTH);
  220 +
  221 + if (!hdr_addr) {
  222 + free(addr);
  223 + spi_flash_free(pfe_flash);
  224 + return -ENOMEM;
  225 + }
  226 +
  227 + ret = spi_flash_read(pfe_flash,
  228 + CONFIG_SYS_LS_PFE_ESBC_ADDR,
  229 + CONFIG_SYS_LS_PFE_ESBC_LENGTH,
  230 + hdr_addr);
  231 + if (ret) {
  232 + printf("SF: failed to read pfe esbc header\n");
  233 + free(addr);
  234 + free(hdr_addr);
  235 + spi_flash_free(pfe_flash);
  236 + return ret;
  237 + }
  238 +
  239 + pfe_esbc_hdr_addr = hdr_addr;
  240 +#endif
  241 +
200 242 pfe_fit_addr = addr;
201 243 spi_flash_free(pfe_flash);
202 244  
... ... @@ -237,7 +279,7 @@
237 279 goto err;
238 280  
239 281 #ifdef CONFIG_CHAIN_OF_TRUST
240   - pfe_esbc_hdr = CONFIG_SYS_LS_PFE_ESBC_ADDR;
  282 + pfe_esbc_hdr = (uintptr_t)pfe_esbc_hdr_addr;
241 283 pfe_img_addr = (uintptr_t)pfe_fit_addr;
242 284 if (fsl_check_boot_mode_secure() != 0) {
243 285 /*
include/configs/ls1043a_common.h
Diff comments   View file @ ff2b924
... ... @@ -261,12 +261,12 @@
261 261 "kernelheader_start=0x800000\0" \
262 262 "fdt_addr_r=0x90000000\0" \
263 263 "load_addr=0xa0000000\0" \
264   - "kernelheader_addr=0x6080000000000\0" \" \
  264 + "kernelheader_addr=0x6060000000000\0" \" \
265 265 "kernel_size=0x2800000\0" \
266 266 "kernelheader_size=0x40000\0" \
267 267 "kernel_addr_sd=0x8000\0" \
268 268 "kernel_size_sd=0x14000\0" \
269   - "kernelhdr_addr_sd=0x4000000\0" \" \
  269 + "kernelhdr_addr_sd=0x3000000\0" \" \
270 270 "kernelhdr_size_sd=0x10\0" \
271 271 "console=ttyS0,115200\0" \
272 272 "boot_os=y\0" \
include/configs/ls1088aqds.h
Diff comments   View file @ ff2b924
... ... @@ -541,11 +541,6 @@
541 541  
542 542 #ifdef CONFIG_FSL_MC_ENET
543 543 #define CONFIG_FSL_MEMAC
544   -#define CONFIG_PHYLIB
545   -#define CONFIG_PHYLIB_10G
546   -#define CONFIG_PHY_VITESSE
547   -#define CONFIG_PHY_REALTEK
548   -#define CONFIG_PHY_TERANETICS
549 544 #define RGMII_PHY1_ADDR 0x1
550 545 #define RGMII_PHY2_ADDR 0x2
551 546 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
... ... @@ -571,7 +566,6 @@
571 566 #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
572 567  
573 568 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
574   -#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
575 569  
576 570 #endif
577 571  
include/configs/ls1088ardb.h
Diff comments   View file @ ff2b924
... ... @@ -504,9 +504,7 @@
504 504  
505 505 /* MAC/PHY configuration */
506 506 #ifdef CONFIG_FSL_MC_ENET
507   -#define CONFIG_PHYLIB
508 507  
509   -#define CONFIG_PHY_VITESSE
510 508 #define AQ_PHY_ADDR1 0x00
511 509 #define AQR105_IRQ_MASK 0x00000004
512 510  
... ... @@ -520,7 +518,6 @@
520 518 #define QSGMII2_PORT4_PHY_ADDR 0x1f
521 519  
522 520 #define CONFIG_ETHPRIME "DPMAC1@xgmii"
523   -#define CONFIG_PHY_GIGE
524 521 #endif
525 522 #endif
526 523  
include/configs/lx2160a_common.h
Diff comments   View file @ ff2b924
... ... @@ -262,7 +262,7 @@
262 262 "kernel_size=0x2800000\0" \
263 263 "kernel_addr_sd=0x8000\0" \
264 264 "kernelhdr_addr_sd=0x3000\0" \
265   - "kernel_size_sd=0x1d000000\0" \" \
  265 + "kernel_size_sd=0x14000000\0" \" \
266 266 "kernelhdr_size_sd=0x20\0" \
267 267 "console=ttyAMA0,38400n8\0" \
268 268 BOOTENV \