21 Feb, 2014
1 commit
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With d6a320d we moved some clock externs out of blackfin_local.h and
into clock.h but now need to include in more drivers to
avoid warnings.Cc: Sonic Zhang
Signed-off-by: Tom Rini
18 Feb, 2014
1 commit
08 Feb, 2014
3 commits
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The open and close mmc sub-commands implement a hard-coded set of values
specific to the SMDK5250 platform. Remove these commands as what they
did can be done instead with a series of mmc dev / bootpart / bootbus
commands instead now.Cc: Amar
Cc: Minkyu Kang
Acked-by: Jaehoon Chung
Signed-off-by: Tom Rini
Signed-off-by: Pantelis Antoniou -
Add a bootbus sub-command to the mmc command to allow for setting
the boot_bus_width, reset_boot_bus_width and boot_mode fields of
BOOT_BUS_WIDTH (EXT_CSD[177]).Acked-by: Jaehoon Chung
Signed-off-by: Tom Rini
Signed-off-by: Pantelis Antoniou -
Add a partconf sub-command to the mmc command to allow for setting
the boot_ack, boot_partition and partition_access fields of
PARTITION_CONFIG (formerly BOOT_CONFIG, EXT_CSD[179]). Part of this
requires changing the check for 'part' from an strncmp to a strcmp, like
the rest of the sub-commands.Cc: Andy Fleming
Cc: Pantelis Antoniou
Acked-by: Jaehoon Chung
Signed-off-by: Tom Rini
Signed-off-by: Pantelis Antoniou
07 Feb, 2014
3 commits
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As per the below commit
"mmc: sdhci: add the quirk for broken r1b response"
(sha1: 3a6383207be3f71b39004e64464a6e99290b16fa)
need to add quirk SDHCI_QUIRK_BROKEN_R1B, when the
response type is R1b.Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
Acked-by: Jagannadha Sutradharudu Teki
Signed-off-by: Pantelis Antoniou -
This patch corrects the divider value written to CLKDIV register.
Since SDCLKIN is divided inside controller by the DIVRATIO value set
in the CLKSEL register, we need to use the same output clock value to
calculate the CLKDIV value.
as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1)Input parameter to mmc_clk is changed to dwmci_host, since
we need the same to read DWMCI_CLKSEL register.This improves the read timing values for channel 0 on SMDK5250
from 0.288sec to 0.144secSigned-off-by: Rajeshwari S Shinde
Acked-by: Jaehoon Chung
Signed-off-by: Pantelis Antoniou -
U-Boot currently sets MMC cards' RCA register to 0. This value is
reserved according to the specification. Use a value of 1 instead, just
like the Linux kernel.Signed-off-by: Stephen Warren
Acked-by: Jaehoon Chung
Signed-off-by: Pantelis Antoniou
04 Feb, 2014
1 commit
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Tegra124's MMC controller is very similar to earlier SoC generations,
and can be supported by the same driver.However, there are some non-backwards-compatible HW differences, and
hence a new DT compatible value must be used to describe the HW. This
patch updates the driver to support that new compatible value.That said, the HW differences are only relevant when enabling certain
high-performance transfer modes. Since the driver is currently very
simple and doesn't enable those modes, we don't actually need to address
any of these HW differences in the code yet, hence the simple nature of
this patch.Signed-off-by: Stephen Warren
Acked-by: Pantelis Antoniou
Tested-by: Thierry Reding
Acked-by: Simon Glass
Signed-off-by: Tom Warren
25 Jan, 2014
1 commit
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Signed-off-by: Masahiro Yamada
23 Jan, 2014
2 commits
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The upper 4 data signals of esdhc are shared with spi flash.
So detect if the upper 4 pins are assigned to esdhc before
enable sdhc 8 bit width.Signed-off-by: Haijun Zhang
Acked-by: Pantelis Antoniou
Reviewed-by: York Sun -
Card detection pin is ineffective on T4240QDS Rev1.0.
There are two cards can be connected to board.
1. eMMC card is built-in board, can not be removed. so
For eMMC card it is always there.
2. Card detecting pin is functional for SDHC card in Rev2.0.This workaround force sdhc driver scan and initialize the card
regardless of whether the card is inserted or not in case Rev1.0.Signed-off-by: Haijun Zhang
Acked-by: Pantelis Antoniou
Reviewed-by: York Sun
14 Jan, 2014
1 commit
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Don't know why but, file permission was changed
Signed-off-by: Minkyu Kang
09 Jan, 2014
5 commits
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To add the DesignWare MMC driver support for Altera SOCFPGA. It
required information such as clocks and bus width from platform
specific files (SOCFPGA handoff files)Signed-off-by: Chin Liang See
Cc: Rajeshwari Shinde
Cc: Jaehoon Chung
Cc: Pantelis Antoniou
Cc: Wolfgang Denk
Acked-by: Pantelis Antoniou -
The eMMC and the SD-Card specifications describe the optional SET_DSR command.
During measurements at our lab we found that some cards implementing this feature
having really strong driver strengts per default. This can lead to voltage peaks
above the specification of the host on signal edges for data sent from a card to
the host.Since availability of a given card type may be shorter than the time a certain
hardware will be produced it is useful to have support for this command (Alternative
would be changing termination resistors and adapting the driver strength of the
host to the used card.)Following proposal for an implementation:
- new field that reflects CSD field DSR_IMP in struct mmc
- new field for design specific DSR value in struct mmc
- board code can set DSR value in mmc struct just after registering an controller
- mmc_startup sends the the stored DSR value before selecting a card, if DSR_IMP is setAdditionally the mmc command is extended to make is possible to play around with different
DSR values.The concept was tested on a i.MX53 based platform using a Micron eMMC card where the default
DSR is 0x0400 (12mA) but in our design 0x0100 (0x0100) were enough. To use this feature for
instance on a mx53loco one have to add a call to mmc_set_dsr() in board_mmc_init() after
calling fsl_esdhc_initialize() for the eMMC.Signed-off-by: Markus Niebel
Acked-by: Pantelis Antoniou -
Fixup prints to show where the print is done from, and
a few minor formatting/grammar issues.Signed-off-by: Darwin Rambo
Acked-by: Pantelis Antoniou -
Bounce buffer implementation takes care of proper data buffer alignemt
and correct flush/invalidation of data cache at once so we no longer
depend on input data variety and make sure CPU and MMC controller deal
with expected data in case of enabled data cache.Bounce buffer requires to add its definition (CONFIG_BOUNCE_BUFFER) in
board configuration, otherwise corresponding library won't be compiled
and linker will fail to build resulting executable.Difference since v1 - fixed compile-time warning with type casting to
"void *":Slight edit to remove UTF8 characters in the commit message.
Acked-by: Jaehoon Chung
Tested-by: Jaehoon Chung
Acked-by: Pantelis Antoniou====
passing argument 2 of 'bounce_buffer_start' discards 'const' qualifier
from pointer target type
====Signed-off-by: Alexey Brodkin
Cc: Mischa Jonker
Cc: Alim Akhtar
Cc: Rajeshwari Shinde
Cc: Jaehoon Chung
Cc: Amar
Cc: Kyungmin Park
Cc: Minkyu Kang
Cc: Simon Glass
Cc: Pantelis Antoniou
Cc: Andy Fleming -
To enhance the SDMMC DesignWare driver to use calloc instead of
malloc. This will avoid the incident that uninitialized members
of mmc structure are later used for NULL comparison.Signed-off-by: Chin Liang See
Cc: Rajeshwari Shinde
Cc: Jaehoon Chung
Cc: Mischa Jonker
Cc: Alexey Brodkin
Cc: Andy Fleming
Cc: Pantelis Antoniou
Acked-by: Pantelis Antoniou
08 Dec, 2013
4 commits
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Faraday FTSDC021 is a controller which is compliant with
SDHCI v3.0, SDIO v2.0 and MMC v4.3.However this driver is only verified with SD memory cards.
Signed-off-by: Kuo-Jung Su
Acked-by: Pantelis Antoniou
CC: Andy Fleming -
Existing eSDHC SPL framework assumes booting from sd-image
with boot_format header which contains final u-boot Image
offset and size. No such header is present in case of
corenet devices like T1040 as corenet deivces use PBI-RCW
based intialization.So, for corenet deives, SPL bootloader use values provided
at compilation time. These values can be defined in board
specific config file.Signed-off-by: Priyanka Jain
Acked-by: Pantelis Antoniou -
If platform provides "host->fifoth_val" it will be used for
initialization of DWMCI_FIFOTH register. Otherwise default value will be
used.This implementation allows:
* escape unclear and recursive calculations that are currently in use
* use whatever custom value for DWMCI_FIFOTH initialization if any
particular SoC requires itSigned-off-by: Alexey Brodkin
Cc: Mischa Jonker
Cc: Alim Akhtar
Cc: Rajeshwari Shinde
Cc: Jaehoon Chung
Cc: Amar
Cc: Kyungmin Park
Cc: Minkyu Kang
Cc: Simon Glass
Cc: Pantelis Antoniou
Cc: Andy Fleming
Acked-by: Jaehoon Chung
Acked-by: Pantelis Antoniou -
dw-mmc.c is the general driver file.
So, remove the exynos specific code at dw-mmc.c.
Instead, exynos specific cod can be move into exynos-dw_mmc.c.Signed-off-by: Jaehoon Chung
Acked-by: Alexey Brodkin
Acked-by: Pantelis Antoniou
Acked-by: Minkyu Kang
01 Nov, 2013
1 commit
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Signed-off-by: Masahiro Yamada
31 Oct, 2013
8 commits
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T4240QDS eSDHC host capabilities reigster should have VS33 bit define.
Add quirk CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 to deal with capacity
missingSigned-off-by: Roy Zang
Signed-off-by: Haijun Zhang
Acked-by: Pantelis Antoniou -
struct mmc should be clear to all '0' after malloc to avoid
unexpect variable value.Like mmc->has_init = xxx.
In this case mmcinfo will believe the card had been initialized before
and skip the initialization.Test on P5040 and T4240,
Error Log:=> mmcinfo
Device: FSL_SDHC
Manufacturer ID: 0
OEM: 0
Name: Tran Speed: 0
Rd Block Len: 0
MMC version 0.0
High Capacity: No
Capacity: 0 Bytes
Bus Width: 0-bit
=>Signed-off-by: Haijun Zhang
Signed-off-by: Xie Shaohui-B21989
Tested-by: Ryan Barnett
Acked-by: Pantelis Antoniou -
Add some descriptions for esdhc register for easily using.
Signed-off-by: Haijun Zhang
Acked-by: Pantelis Antoniou -
eSDHC host controller has new register to support SD Spec 3.0.
And the according host controller version was Freescale eSDHC
Version 3.0.Signed-off-by: Haijun Zhang
Acked-by: Pantelis Antoniou -
SMDK5420 has a new Security Management Unit added
for dwmmc driver, hence, configuring the control
registers to support booting via eMMC.Signed-off-by: Alim Akhtar
Signed-off-by: Rajeshwari Shinde
Acked-by: Simon Glass
Acked-by: Jaehoon Chung
Acked-by: Pantelis Antoniou -
Old command timeout value was too small and it caused I/O errors which
led to uncompleted read/write/erase operations and filesystem errors.
Timeout adaptation fixes this issue.Changes in sdhci_send_command() function:
- change timeout variable to static
- increase default command timeout to 100 ms
- add definition of max command timeout value,
which can be redefined in each board config file
- wait for card ready state for max defined time
if it doesn't exceed defined maximum or return COMM_ERROnce successfully increased timeout value will be used in next function
call. This fix was tested on Goni, Trats, Trats2 boards by testing UMS
on MMC storage.Changes v2:
- move global variable cmd_timeout into function sdhci_send_command()
- change condition "==" to ">=" when comparing time with timeout
- print information about timeout increasing and card busy timeoutSigned-off-by: Przemyslaw Marczak
Cc: Pantelis Antoniou -
To prevent the confusion, use the get_mmc_clk() instead of mmc_clk().
get_mmc_clk() is more exactly name.Signed-off-by: Jaehoon Chung
Acked-by: Pantelis Antoniou -
EXT_CSD_ERASE_GROUP_DEF is lost every time after a reset or
power off. Set it if device has enhanced partitions.Signed-off-by: Oliver Metz
Acked-by: Pantelis Antoniou
02 Oct, 2013
1 commit
21 Sep, 2013
1 commit
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The patch fixes the improper read and write of sdhci
host control register for sdma transfer.The problem comes when reading and writing 1 byte long
host control register with the sdhci_readl() and
sdhci_writel(). The misuse of these functions overwrite
the value of the next registers which are in 4 bytes boundary.This patch replaces four byte register read/write functions
with one byte read/write ones. Beside, it eliminates
unnecessary bit operation. i.e. or-ing zero against a variable.Signed-off-by: Juhyun (Justin) Oh
20 Sep, 2013
4 commits
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This fixes two issues:
* a descriptor was allocated for every block, while a descriptor can
take 8 blocks
* there was an off-by-one error in the descriptor preparation: there
were two last descriptors, one with length==0Signed-off-by: Mischa Jonker
Cc: Alexey Brodkin
Cc: Jaehoon Chung
Cc: Andy Fleming -
In dwmci_prepare_data, the descriptors are allocated for DMA transfer.
These are allocated using the ALLOC_CACHE_ALIGN_BUFFER. This macro uses
the stack to allocate these descriptors. This becomes a problem if the
DMA transfer continues after the processor leaves the function in which
the descriptors were allocated.Therefore, I have moved the allocated of the buffers up one level, to
dwmci_send_cmd(). The DMA transfer should be complete when leaving this
function.Signed-off-by: Mischa Jonker
Cc: Alexey Brodkin
Cc: Jaehoon Chung
Cc: Andy Fleming
Acked-by: Jaehoon Chung
Acked-by: Pantelis Antoniou -
For SPL builds this is just dead code since we'll only need to read.
Eliminating it results in a significant size reduction for the SPL
binary, which may be critical for certain platforms where the binary
size is highly constrained.Signed-off-by: Paul Burton
Acked-by: Pantelis Antoniou -
malloc can fail, so we should better check its return value before using it.
Signed-off-by: Fabio Estevam
18 Sep, 2013
3 commits
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If we don't have CONFIG_SPL_LIBCOMMON_SUPPORT defined then stdio
& *printf functions are unavailable & calling them will cause a link
failure.Signed-off-by: Paul Burton
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Enable 8-bit host capability for HSMMC2 and/or HSMMC3. CONFIG_HSMMC2_8BIT
(for OMAP4/5/DRA7xx) and/or CONFIG_HSMMC3_8BIT (for DRA7xx only) must be
defined in the board header if an 8-bit eMMC device is connected to the
corresponding port.Fix the "No status update" error that appeared for eMMC devices by
inserting a 20 us delay between writing arguments and command. This
solution has been proposed by Michael Cashwell .A minor cosmetic fix in a comment as well.
Signed-off-by: Lubomir Popov
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"mmc_send_cmd: timeout: No status update" error sometimes happens in
omap_hsmmc driver func mmc_send_cmd() when the MMC controller card
identification and selection sequence is executed for eMMC on OMAP4
boards.It happens due to incorrect execution of CMD line reset procedure
for OMAP4. Because CMD(DAT) lines reset procedures are slightly
different for OMAP3 and OMAP4(AM335x,OMAP5,DRA7xx).According to OMAP3 TRM:
Set SRC(SRD) bit in MMCHS_SYSCTL register to 0x1 and wait until
it returns to 0x0.According to OMAP4(AM335x,OMAP5,DRA7xx) TRMs, CMD(DATA) lines reset
procedure steps must be as follows:
1. Initiate CMD(DAT) line reset by writing 0x1 to SRC(SRD) bit in
MMCHS_SYSCTL register (SD_SYSCTL for AM335x).
2. Poll the SRC(SRD) bit until it is set to 0x1.
3. Wait until the SRC(SRD) bit returns to 0x0
(reset procedure is completed).Unfortunately, at present omap_hsmmc driver has support only for
OMAP3. And as result step #2 is missing for OMAP4(AM335x,OMAP5,DRA7xx).
This sometimes leads to the fact that the waiting loop which is
required in step #3 does not executed, because SRC bit does not set
yet (at the moment of checking a condition of a loop execution).
And as a result this can cause to timeout error when sending a
next command.In the particular case (working with eMMC witch do not respond to
some SD specific command) due to incorrect reset sequence after
command SD_CMD_SEND_IF_COND which finished with CTO flag within
64 clock cycles, the next command MMC_CMD_APP_CMD leads to a
timeout error within 1s.So, extend CMD(DATA) lines reset procedure in func
mmc_reset_controller_fsm() by adding the missing step #2 for
OMAP4+/AM335x boards.Signed-off-by: Oleksandr Tyshchenko
Acked-by: Pantelis Antoniou
