18 Jan, 2008
2 commits
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This patch adds support for the SPI controller found on Freescale PowerPC
processors such as the MCP834x family. Additionally, a new config option,
CONFIG_HARD_SPI, is added for general purpose SPI controller use.Signed-off-by: Ben Warren
Signed-off-by: Kim Phillips -
The commit 9e89647889cd4b5ada5b5e7cad6cbe55737a08d7
will cause the mpc8315erdb board can't boot up.The patch fix that bug, and remove the duplicated #ifdef
CFG_SPCR_TSECEP code and clean the SCCR_TSEC2 for
MPC8313E processor.Signed-off-by: Dave Liu
Signed-off-by: Kim Phillips
17 Jan, 2008
18 commits
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Previous setting cause ips clock to be out of spec. This bug was found by John
Rigby from Freescale.Signed-off-by: Grzegorz Bernacki
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MPC837xERDB board support includes:
* DDR2 330MHz hardcoded (soldered on the board)
* Local Bus NOR Flash
* I2C, UART and RTC
* eTSEC RGMII (TSEC0 - RTL8211B with MII;
* TSEC1 - VSC7385 local bus, hardcoded, requires seperate firmware
* load)Signed-off-by: Kevin Lam
Signed-off-by: Joe D'Abbraccio
Signed-off-by: Kim Phillips -
System registers that are modified are the Arbiter Configuration
Register (ACR), the System Priority Control Register (SPCR), and the
System Clock Configuration Register (SCCR).Signed-off by: Michael F. Reiss
Signed-off by: Joe D'Abbraccio
Signed-off-by: Kim Phillips -
Before, the order of arguments to the pixis_reset
command needed to be supplied in a hard-coded order.
Generalize the command parsing to allow any order.Signed-off-by: James Yang
Acked-by: Jon Loeliger -
Convert the board/freescale/common/Makefile to use
CONFIG_* options to select which files to conditionally
compile into the board/freescale/common library rather
than conditionally compiling entire files.Now handles::
CONFIG_FSL_PIXIS
CONFIG_FSL_DIU_FB
CONFIG_PQ_MDS_PIBCONFIG_ID_EEPROM is introduced until CFG_ID_EEPROM is gone.
Signed-off-by: Jon Loeliger
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Use driver/net/uli526x.c as MPC8610HPCD default Ethernet driver.
Remove unused ethernet CONFIG_ options.Signed-off-by: Roy Zang
Acked-by: Jon Loeliger -
continuation of commit b96c83d4ae475a70ef2635cd0e748174c44c8601
Signed-off-by: Kim Phillips
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mpc8360emds.c: In function 'ft_board_setup':
mpc8360emds.c:327: warning: assignment makes pointer from integer without a cast
mpc8360emds.c:329: warning: passing argument 2 of 'fdt_getprop' makes integer from pointer without a cast
mpc8360emds.c:334: warning: passing argument 2 of 'fdt_setprop' makes integer from pointer without a cast
mpc8360emds.c:341: warning: assignment makes pointer from integer without a cast
mpc8360emds.c:343: warning: passing argument 2 of 'fdt_getprop' makes integer from pointer without a cast
mpc8360emds.c:348: warning: passing argument 2 of 'fdt_setprop' makes integer from pointer without a castSigned-off-by: Kim Phillips
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use tree passed to us in local blob, not global fdt.
Also use fdt_path_offset to convert to relative offset, since absolute
reference is needed to check for rgmii-id mode string value.Signed-off-by: Kim Phillips
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Signed-off-by: Kumar Gala
Signed-off-by: Kim Phillips -
These changes were identified by HighSmith Bill ,Mazzyar and Joseph for
DDR configuration in u-boot code. Some are related to performance, some
affect stability and some correct few basic errors in the current
configuration.The changes have been tested and found to give better memory latency
figures on MPC8313eRDB.LMBench figures prove it.The changes are:
- CS0_CONFIG[ AP_n_EN] is changed from 1 to 0
(this may improve performance for application with many read
or write to open pages).
- CS0_CONFIG[ODT_WR_CFG] is currently changed from 100 to
001 (activating all the CS when only one is used may cause
unwanted noise on the system)- TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 8clks (based on
Tras=45ns)
- TIMING_CFG_1[REFREC] changed from 21 clks to 18clks.- TIMING_CFG_2[AL] value changed from 0 setting to 1 clk to
comply with the 3 ODT clk requirements)
- TIMING_CFG_2[CPO] was set to a reserved value, changed to RL+3/4.
- TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 6clks.- DDR_SDRAM_MODE[AL]changed from 0 to 1.
- DDR_SDRAM_MODE[WRREC] changed from 1 clk to 3 clks.- DDR_SDRAM_INTERVAL[REFINT] is changed from 0x0320 to 0x0510.
- DDR_SDRAM_INTERVAL[BSTOPRE] is changed from 0x64 to 0x0500.The patch is based of git://www.denx.de/git/u-boot-mpc83xx.git
The last commit on this tree was 6775c68683a53c7abc778774641aac6f833a2cbfSigned-off-by: Poonam Aggrwal-b10812
Cc: Bill HighSmith
Cc: Razzaz Mazyar
Cc: Josep P J
Signed-off-by: Kim Phillips -
The isdram command prints out decoded information the "serial presence
detect" (SPD) chip on the SDRAM SIMMs. This can be very helpful when
debugging memory configuration problems.Signed-off-by: Gerald Van Baren
Signed-off-by: Kim Phillips -
The features list:
- Boot from NOR Flash
- DDR2 266MHz hardcoded configuration
- Local bus NOR Flash R/W operation
- I2C, UART, MII and RTC
- eTSEC0/1 support
- PCI hostSigned-off-by: Dave Liu
Signed-off-by: Kim Phillips -
The TSEC emergency priority definition of 831x/837x
is different than the definition of 834x in SPCR register.Add the other config of TSEC emergency priority into
cpu_init.cSigned-off-by: Dave Liu
Signed-off-by: Kim Phillips -
The MPC8360ERDK board support patch is added before
the commit 2c5b48fc205c3e2752910da8f39209ed075929e5
so, miss clean up it.The patch clean up the miss cache config.
Signed-off-by: Dave Liu
Signed-off-by: Kim Phillips
16 Jan, 2008
5 commits
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Signed-off-by: Anton Vorontsov
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OneNAND: Separate U-Boot dependent code from OneNAND
Signed-off-by: Kyungmin Park
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Signed-off-by: Wolfgang Denk
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Signed-off-by: Wolfgang Denk
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adjust default environment;
disable SCC ethernet (not used on this board).Signed-off-by: Wolfgang Denk
15 Jan, 2008
9 commits
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Signed-off-by: Nobuhiro Iwamatsu
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SH7710/SH7712 of SH3 CPU are supported.
SH771X is called SH-Ether, and has the Ether controller in CPU.
The driver of Ether is not included in this patch.Signed-off-by: Nobuhiro Iwamatsu
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This patch add the support of map_physmem() and unmap_physmem()
used with Common Flash Interface(CFI) driver.Signed-off-by: Nobuhiro Iwamatsu
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Signed-off-by: Nobuhiro Iwamatsu
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Signed-off-by: Nobuhiro Iwamatsu
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Signed-off-by: Nobuhiro Iwamatsu
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Signed-off-by: Yoshihiro Shimoda
CC: Nobuhiro Iwamatsu
Acked-by: Nobuhiro Iwamatsu -
Signed-off-by: Yoshihiro Shimoda
CC: Nobuhiro Iwamatsu
Acked-by: Nobuhiro Iwamatsu -
Signed-off-by: Yoshihiro Shimoda
CC: Nobuhiro Iwamatsu
Acked-by: Nobuhiro Iwamatsu
14 Jan, 2008
6 commits
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qe.c: In function 'qe_upload_firmware':
qe.c:390: warning: pointer targets in passing argument 2
uec.c: In function 'uec_initialize':
uec.c:1236: warning: 'uec_info' may be used uninitializedSigned-off-by: Dave Liu
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Now that bit 29 is the USB PHY reset bit, update the Kilauea port
to remove the USB PHY reset after powerup. The CPLD will keep the
USB PHY in reset (active low) until the bit is set to 1 in
board_early_init_f().Signed-off-by: Stefan Roese
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Signed-off-by: Wolfgang Denk
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Signed-off-by: Wolfgang Denk
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Signed-off-by: John Rigby
