05 Feb, 2021
2 commits
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The GIC redistributor tables initialization depends on RESV_RAM config,
so select RESV_RAM if GIC_V3_ITS is enabled.Signed-off-by: Hou Zhiqiang
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The initialization of gd->arch.resv_ram pointer should depend on if the
RESV_RAM config is enabled.Signed-off-by: Hou Zhiqiang
28 Jan, 2021
1 commit
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Includes DT definition for the following serdes protocols using various
PHY cards: 85xx, 13xx, 65xx, 9999, 7777.Note that the default device tree for QDS now uses 85xx.
Enabling any of the others requires patching the fsl-ls1028a-qds.dtsi
file (the includes at the bottom of the file).Signed-off-by: Alex Marginean
Signed-off-by: Vladimir Oltean
27 Jan, 2021
1 commit
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Multiple LX2(LX2160A/LX2162A SoC) personality variants
exists based on CAN-FD and security bit in SVR.Currenly SVR_SOC_VER mask only security bit.
Update SVR_SOC_VER to mask CAN_FD and security bit
for LX2 products.Signed-off-by: Wasim Khan
13 Jan, 2021
1 commit
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When A-050382 errata is enabled, ECAM and EDMA have
conflicting stream id 40. This patch fixes the same.Signed-off-by: Nipun Gupta
03 Nov, 2020
2 commits
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Check for NULL return value from fdt_getprop() in fdt_fixup_remove_jr()
Signed-off-by: Priyanka Singh
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The sdhc peripheral clock support for lx2162aqds was missed.
Fixes: 1f9ecf088930 ("armv8: lx2162a: Add Soc changes to support LX2162A")
Signed-off-by: Yangbo Lu
29 Oct, 2020
8 commits
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Add gpio node for SoC LS208xA
Signed-off-by: Biwen Li
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Add gpio node for SoC LS1088A
Signed-off-by: Biwen Li
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Add gpio node for SoC LS1046A
Signed-off-by: Biwen Li
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Add gpio node for SoC LS1043A
Signed-off-by: Biwen Li
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Add gpio node for SoC LS1028A
Signed-off-by: Biwen Li
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Add gpio node for SoC LS1012A
Signed-off-by: Biwen Li
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Add gpio node for SoC LS1021A
Signed-off-by: Biwen Li
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Fix a bug as belows,
=> gpio status -a
"Synchronous Abort" handler, esr 0x96000061
elr: 0000000082047964 lr : 0000000082047960 (reloc)
elr: 00000000fbd72964 lr : 00000000fbd72960
x0 : 00000000ffffffff x1 : 000000000000000a
x2 : 0000000000000020 x3 : 0000000000000001
x4 : 0000000000000000 x5 : 0000000000000030
x6 : 0000000000000020 x7 : 0000000000000002
x8 : 00000000ffffffe0 x9 : 0000000000000008
x10: 0000000000000010 x11: 0000000000000006
x12: 000000000001869f x13: 0000000000000230
x14: 00000000fbc23e9c x15: 00000000ffffffff
...
resetingSigned-off-by: Biwen Li
19 Oct, 2020
2 commits
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Rename fsl-ls1028a-qds.dts to fsl-ls1028a-qds.dtsi so that
it can be used as common device tree for lpuart and duart.
Add lpuart device tree and duart device tree respectively
for qds which are used with duart and lpuart console.Signed-off-by: Vabhav Sharma
Signed-off-by: Yuantian Tang -
Add lpuart nodes to enable lpuart feature
Signed-off-by: Vabhav Sharma
Signed-off-by: Yuantian Tang
09 Oct, 2020
2 commits
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add alias for dspi
Signed-off-by: Zhao Qiang
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As per hardware documentation, ECx_PMUX has precedence
over SerDes protocol.
For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII
through SerDes protocol but ECx_PMUX configured them as RGMII,
then the ports will be configured as RGMII and not SGMII.Signed-off-by: Razvan Ionut Cirjan
29 Sep, 2020
9 commits
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P2020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII switch VSC7385
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY AR8021Signed-off-by: Hou Zhiqiang
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P1010RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII PHY AR8033
eTSEC2: Connected to SGMII PHY AR8033
eTSEC3: Connected to SGMII PHY AR8033Signed-off-by: Hou Zhiqiang
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P1020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII switch VSC7385
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY AR8021Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean -
The cpu_eth_init() is only used by the legacy ethernet driver framework.
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean -
Add i2c node of p1010
Signed-off-by: Biwen Li
Reviewed-by: Priyanka Jain
Signed-off-by: Hou Zhiqiang -
Add device tree for P1010RDB boards and enable CONFIG_OF_CONTROL
so that device tree can be compiled.Signed-off-by: Hou Zhiqiang
Reviewed-by: Priyanka Jain -
Add dspi node into lx2162aqds device tree
Signed-off-by: Zhao Qiang
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Enable the gpio feature on fsl-layerscape platform.
Signed-off-by: hui.song
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disable non existing pcie controllers on lx2162aqds
Signed-off-by: Wasim Khan
28 Sep, 2020
1 commit
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Add OPTEE node in lx2 device tree to enable access of
OPTEE TA's from u-boot.Signed-off-by: Ruchika Gupta
18 Sep, 2020
4 commits
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This patch moves the SVR definitiones to a new svr.h for
Layerscape armv7 and armv8 platforms respectively, so that
the PCIe driver can reuse them.Signed-off-by: Hou Zhiqiang
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add one struct mpc8xxx_gpio_plat to enable gpio feature.
Signed-off-by: hui.song
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add gpio0 gpio1 gpio3 DT nodes to fsl-lx21600.dtsi
Signed-off-by: hui.song
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Add properties related to eMMC HS400 mode.
Signed-off-by: Yangbo Lu
10 Sep, 2020
1 commit
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Make sure that SW_RST_REQ and RST_REQ_MSK are cleared
before triggering hardware reset request.Signed-off-by: Thirupathaiah Annapureddy
Signed-off-by: Meenakshi Aggarwal
08 Sep, 2020
2 commits
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This patch add base support for LX2162AQDS board.
LX2162AQDS board supports LX2162A family SoCs.
This patch add basic support of platform.Signed-off-by: Ioana Ciornei
Signed-off-by: Zhao Qiang
Signed-off-by: hui.song
Signed-off-by: Manish Tomar
Signed-off-by: Vikas Singh
Signed-off-by: Meenakshi Aggarwal
Signed-off-by: Priyanka Jain -
LX2162 is LX2160 based SoC, it has same die as of LX2160
with different packaging.LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module,
microSD card, eMMC support, serial console, qspi nor flash, qsgmii,
sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes
interface to support three PCIe gen3 interface.Signed-off-by: Meenakshi Aggarwal
07 Sep, 2020
1 commit
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Add IO range property to fix below error on uboot
PCI: Failed autoconfig bar 18
Signed-off-by: Wasim Khan
02 Sep, 2020
1 commit
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Configure DWC3's cache type to 'cacheable' for better
performance. Actually related register definition and values are SoC
specific, which means this setting is only applicable to Layerscape SoC,
not generic for all platforms which have integrated DWC3 IP.Signed-off-by: Ran Wang
27 Aug, 2020
2 commits
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The sdhc_adapter of global data has not been used, and we
do not have to use it as global data even we may need it
in the future.Signed-off-by: Yangbo Lu
Reviewed-by: Peng Fan
Reviewed-by: Priyanka Jain -
This patch is to define esdhc_status_fixup function for ls1028a to disable
SDHC1/SDHC2 status in device tree node if not selected.Signed-off-by: Yinbo Zhu
Signed-off-by: Xiaowei Bao
Signed-off-by: Yangbo Lu
Reviewed-by: Priyanka Jain
