27 Jan, 2021
1 commit
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We have encountered circumstances when a board design does not include
pull-up resistors on the external MDIO buses which are not used. This
leads to the MDIO data line not being pulled-up, thus the MDIO controller
will always see the line as busy.Without a timeout in the MDIO bus driver, the execution is stuck in an
infinite loop when any access is initiated on that external bus.Add a timeout in the driver so that we are protected in this
circumstance. This is similar to what is being done in the Linux
xgmac_mdio driver.Signed-off-by: Ioana Ciornei
10 Dec, 2020
2 commits
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timeout should be in "millisecond" instead of second,
so divided it by 1000 when calculate the load value.Signed-off-by: Zhao Qiang
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drivers/usb/host/xhci-ring.c: In function 'xhci_bulk_tx':
drivers/usb/host/xhci-ring.c:726:6: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
726 | if ((void *)le64_to_cpu(event->trans_event.buffer) != last_transfer_trb_addr) {
| ^Signed-off-by: Ran Wang
19 Nov, 2020
2 commits
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This reverts commit db5e48bab9ef90b05da8c4ad396a9a959506b2fe.
The changes needs rework to work on i.mx devices
LFU-40Signed-off-by: Priyanka Jain
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This reverts commit ef959d695523c391a68093550a3bfb8714ab7ac9.
The changes needs rework to work on i.mx devices
LFU-40Signed-off-by: Priyanka Jain
09 Nov, 2020
1 commit
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Read PFE ESBC header flash with spi_flash_read API
- logs as follows,
Net: SF: Detected s25fs512s with page size 256 Bytes, erase size 256
KiB, total 64 MiB
"Synchronous Abort" handler, esr 0x96000210
elr: 000000008206db44 lr : 0000000082004ea0 (reloc)
elr: 00000000b7ba6b44 lr : 00000000b7b3dea0
x0 : 00000000b79407e8 x1 : 0000000040640000
x2 : 0000000000000050 x3 : 0000000000000000
x4 : 000000000000000a x5 : 0000000000000050
x6 : 0000000000000366 x7 : 00000000b7942308
x8 : 00000000b76407c0 x9 : 0000000000000008
x10: 0000000000000044 x11: 00000000b7634d1c
x12: 000000000000004f x13: 0000000000000044
x14: 00000000b7634d98 x15: 00000000b76407c0
x16: 0000000000000000 x17: 0000000000000000
x18: 00000000b7636dd8 x19: 0000000000000000
x20: 00000000b79407d0 x21: 00000000b79407e8
x22: 0000000040640000 x23: 00000000b7634e58
x24: 0000000000000000 x25: 0000000003800000
x26: 00000000b7bdd000 x27: 0000000000000000
x28: 0000000000000000 x29: 00000000b7634d10Code: d2800003 eb03005f 54000101 d65f03c0 (f8636826)
Resetting CPU ...Signed-off-by: Biwen Li
29 Oct, 2020
1 commit
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Fix a bug as belows,
=> gpio status -a
"Synchronous Abort" handler, esr 0x96000061
elr: 0000000082047964 lr : 0000000082047960 (reloc)
elr: 00000000fbd72964 lr : 00000000fbd72960
x0 : 00000000ffffffff x1 : 000000000000000a
x2 : 0000000000000020 x3 : 0000000000000001
x4 : 0000000000000000 x5 : 0000000000000030
x6 : 0000000000000020 x7 : 0000000000000002
x8 : 00000000ffffffe0 x9 : 0000000000000008
x10: 0000000000000010 x11: 0000000000000006
x12: 000000000001869f x13: 0000000000000230
x14: 00000000fbc23e9c x15: 00000000ffffffff
...
resetingSigned-off-by: Biwen Li
19 Oct, 2020
2 commits
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Since the HDP will be shared with i.MX. Move the common HDP library
codes to "driver/video/nxp/hdp" directory.
And use platform specified directory "driver/video/nxp/layerscape"
for LS driver codes and configurations.Signed-off-by: Ye Li
Reviewed-by: Alison Wang -
The register to enable/disable the write-permission of DBI RO
registers should be accessed via the CFG_ADDR/CFG_DATA registers
instead of accessing directly.Signed-off-by: Hou Zhiqiang
09 Oct, 2020
1 commit
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As per hardware documentation, ECx_PMUX has precedence
over SerDes protocol.
For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII
through SerDes protocol but ECx_PMUX configured them as RGMII,
then the ports will be configured as RGMII and not SGMII.Signed-off-by: Razvan Ionut Cirjan
05 Oct, 2020
1 commit
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Variable 'compat' is never NULL so drop the check.
Signed-off-by: Laurentiu Tudor
29 Sep, 2020
12 commits
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Add compatible string "gianfar" support and update the
device-tree-bindings doc.Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean -
The info of fixed-link PHY is described in DT node instead of
getting from MII, so detect the fixed-link PHY DT node first,
if it doesn't exist then probe the MII.Signed-off-by: Vladimir Oltean
Signed-off-by: Hou Zhiqiang -
For the platforms on which the eTSEC driver uses DM_ETH, convert its
MDIO controller code to also use DM_MDIO.Note that for handling the TBI PHY (the MAC PCS for SGMII), we still
don't register a udevice for it, since we can drive it locally and there
is no point in doing otherwise.Signed-off-by: Vladimir Oltean
Signed-off-by: Hou Zhiqiang -
The MII management register block offset is different between
gianfar and etsec2 compatible devices, this patch is to fix
this issue by adding driver data for different compatible
string.Fixes: 2932c5a802a9 ("net: tsec: fsl_mdio: add DM MDIO support")
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean -
Use virtual address to access the MII block registers instead
of physical address.Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean -
It is utterly pointless to require an MDIO bus pointer for a fixed PHY
device. The fixed.c implementation does not require it, only
phy_device_create. Fix that.Signed-off-by: Vladimir Oltean
Signed-off-by: Hou Zhiqiang
Reviewed-by: Hou Zhiqiang -
When an eTSEC is configured to use TBI, configuration of the
TBI is done through the MIIM registers for that eTSEC.
For example, if a TBI interface is required on eTSEC2, then
the MIIM registers starting at offset 0x2_5520 are used to
configure it.Fixes: 9a1d6af55ecd ("net: tsec: Add driver model ethernet support")
Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
Tested-by: Vladimir Oltean
Reviewed-by: Priyanka Jain -
The current code accesses eTSEC registers using physical
address directly, it's not correct, though no problem on
current platforms. It won't work on platforms, which does
not support 1:1 virtual-physical address map.Signed-off-by: Hou Zhiqiang
Reviewed-by: Vladimir Oltean
Tested-by: Vladimir Oltean
Reviewed-by: Priyanka Jain -
Allow the MDIO devices to be probed based on the device tree.
Signed-off-by: Madalin Bucur
Signed-off-by: Priyanka Jain -
The commit 003f779184dc added the PCIe EP nodes fixup of LX2160A, but it
didn't update the condition value when there isn't a property 'apio-wins'.Fixes: 003f779184dc ("pci: layerscape: Fixup PCIe EP mode DT nodes for LX2160A rev2")
Signed-off-by: Hou Zhiqiang -
Make the MPC8XXX gpio driver to support the fsl-layerscape.
Signed-off-by: hui.song
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This patch adds a command to load the HDP firmware and supporting
libraries.Signed-off-by: Oliver Brown
Signed-off-by: Alison Wang
28 Sep, 2020
2 commits
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In functiion xhci_bulk_tx(), when buffer cross 64KB boundary, it will
send request in more than 1 Transfer TRB by chaining them, but then handle
only 1 event TRB to mark request completed.However, on Layerscape platforms (LS1028A, LS1088A, etc), we observe xhci
controller will generated more than 1 event TRB sometimes, this cause that
function mishandle event TRB in next round call, then system hang due to
BUG() checking.This patch adds a loop to make sure the event TRB for last Transfer TRB has
to be handled in time.Signed-off-by: Ran Wang
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The fdt_size_t has different byte width on arm64 and arm32 platforms.
Fix the following warning by converting the type of 'cfg_size' to
'u64' forcedly.
drivers/pci/pcie_layerscape.c: In function ‘ls_pcie_probe’:
drivers/pci/pcie_layerscape.c:573:40: warning: format ‘%llx’ expects argument of type ‘long long unsigned int’, but argument 4 has type ‘fdt_size_t’ {aka ‘long unsigned int’} [-Wformat=]
573 | printf("PCIe%d: %s Invalid size(0x%llx) for resource \"config\",expected minimum 0x%x\n",
| ~~~^
| |
| long long unsigned int
| %lx
574 | PCIE_SRDS_PRTCL(pcie->idx), dev->name, cfg_size, SZ_8K);
| ~~~~~~~~
| |
| fdt_size_t {aka long unsigned int}Fixes: c481b5c86b2c ("pci: layerscape: Add size check for config resource")
Signed-off-by: Hou Zhiqiang
18 Sep, 2020
5 commits
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This patch moves the SVR definitiones to a new svr.h for
Layerscape armv7 and armv8 platforms respectively, so that
the PCIe driver can reuse them.Signed-off-by: Hou Zhiqiang
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LX2160A rev2 uses different PCIe controller, so EP mode DT
nodes also need to be fixed up.Signed-off-by: Hou Zhiqiang
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Fix Coverity issue: RESOURCE_LEAK.
leaked_storage: Variable addr going out of scope leaks the storage it
points to.Fixes: 171b3932a6c5 ("net: pfe_eth: Use spi_flash_read API to access
flash memory")
Signed-off-by: Kuldeep Singh -
LX2162A is not like LX2160A which has different PCIe controller
in rev1 and rev2 silicon. It supports only one configuration of
PCIe controller, which is same as LS2088A. So update PCIe
compatible string same as LS2088A.Signed-off-by: Hou Zhiqiang
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This reverts commit d959fbe5d74506447f4a9ea9feda1b02e1889179.
The workaround of A-011451 of LX2160A rev1 PCIe results in i.MX
boot crash in Linux factory uboot tree. And the LX2160A rev1
won't supported anymore in LSDK release. So, revert the WA patch.Signed-off-by: Hou Zhiqiang
11 Sep, 2020
2 commits
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The next DPMAC was always verified if it is enabled. In case of
DPMAC@6, the DPMAC@7 is verified. As DPMAC@7 is disabled, DPMAC@6 will
be considered disabled and not detected by uboot.Signed-off-by: Grigore Popescu
Signed-off-by: Ioana Ciornei -
correction in delay implementation before we exit out of tx timeout.
Signed-off-by: Chaitanya Sakinam
08 Sep, 2020
2 commits
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LX2162 is LX2160 based SoC, it has same die as of LX2160
with different packaging.LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module,
microSD card, eMMC support, serial console, qspi nor flash, qsgmii,
sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes
interface to support three PCIe gen3 interface.Signed-off-by: Meenakshi Aggarwal
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Fix this link error showing up on chips that are not layerscape
chassis v2 or v3 based. Error message (trimmed) below:drivers/built-in.o: in function `ft_pcie_rc_fix':
pcie_layerscape_fixup.c:543: undefined reference to
`fdt_pcie_get_nodeoffset`Signed-off-by: Laurentiu Tudor
02 Sep, 2020
1 commit
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PFE DDR addresses are now stored on to a stack varaiable rather
dynamic allocation.Signed-off-by: Chaitanya Sakinam
27 Aug, 2020
5 commits
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Erratum A-011334: Limited clock dividers for HS400 mode
Description: Due to this erratum, the division ratio options
are limited for HS400 mode. The divider value
(value of SYSCTL[DVS] * value of SYSCTL[SDCLKFS] ) can only be
4, 8, or 12.Workaround: Select the divider value to be 4, 8, or 12.
Signed-off-by: Yangbo Lu
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Each of below functions called by mmc_set_initial_state() will
configure voltage, clock, bus width, and mode through mmc_set_ios(),
before initialize these parameters properly. The right method
should be initialize these parameters properly and set them by
mmc_set_ios() once.- mmc_set_signal_voltage
- mmc_set_clock
- mmc_set_bus_widthSigned-off-by: Yangbo Lu
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The mmc_power_cycle() should be put after controller initialization
because the mmc_power_off() would call mmc_set_clock() which will
configure the controller through mmc_set_ios().Signed-off-by: Yangbo Lu
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The initial clock setting should be through sysctl register only,
while the mmc_set_clock() will call mmc_set_ios() introduce other
configurations like bus width, mode, and so on.Signed-off-by: Yangbo Lu
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If the controller is in HS400 mode, it should exit HS400 mode
properly before switching to any other mode.Signed-off-by: Yangbo Lu
