03 May, 2016
7 commits
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I'll switch my mails to my own server, so drop all gmail references.
Signed-off-by: Andreas Bießmann
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The getopt(3) optstring '-' is a GNU extension which is not available on BSD
systems like OS X.Remove this dependency by implementing argument parsing in another way. This
will also change the lately introduced '-b' switch behaviour.Signed-off-by: Andreas Bießmann
Reviewed-by: Simon Glass -
We need to be passing -T firmware here and aren't.
Signed-off-by: Tom Rini
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The function ext4fs_read_symlink was unable to handle a symlink
which had target name of exactly 60 characters.Signed-off-by: Ronald Zachariah
Signed-off-by: Stefan Roese
Reviewed-by: Stephen Warren
Cc: Tom Rini -
This reverts commit b5788dc0dd9570e98552833767f4373db965985d.
Ram size is incorrectly reported as 512MB on a firefly-rk3288 board
with 2GB of ram. Reverting this patch displays the full amount of ram.Signed-off-by: Vagrant Cascadian
Acked-by: Simon Glass -
Unfortunately with this change we now are unable to do FS mode boots
from MMC1 as with the way the code works today we will always load and
assume that the hard-coded raw location contains U-Boot. Further, we
cannot fix this by just changing other logic to try FS-then-RAW as it
would also make us have to ignore what order the ROM is telling us to
try.This reverts commit 22d90d560a2b01c47f180e196e6c6485eb8e65db.
Signed-off-by: Tom Rini
02 May, 2016
1 commit
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We cannot change the long standing hard-coded offset for raw boot mode
for everyone to accommodate how Android expects things to be done here.This reverts commit ef5ebe951bec72631cdbc7cef9079e6c684e5d0b.
Signed-off-by: Tom Rini
01 May, 2016
4 commits
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The code in uniphier_sld3_sbc_init() is pin-muxing, so it would
be a better fit in uniphier_sld3_early_pin_init().Signed-off-by: Masahiro Yamada
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The System Bus is not available by default on the ROM boot mode of
PH1-LD20. To use devices connected to the System Bus, such as the
Micro Support Card, it is necessary to set up pin-muxing and some
System Bus Controller register.Signed-off-by: Masahiro Yamada
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This is needed to use UART on SPL.
Signed-off-by: Masahiro Yamada
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PH1-LD20 does not have the dedicated boot swap select latch.
Instead, it is controlled from the boot mode select.Signed-off-by: Masahiro Yamada
29 Apr, 2016
2 commits
28 Apr, 2016
5 commits
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The DMA was outputting the palette on the screen because the base
for the DMA was not after the palette. In addition to that, the ceiling was
also too high, this led that the output on the screen was shifted.NOTE: According to the TRM, even in 16/24bit mode a palette is required
in the first 32 bytes of the framebuffer.See also:
https://e2e.ti.com/support/arm/sitara_arm/f/791/p/234967/834483#834483"In this mode, the LCDC will assume all information is data and thus you
need to ensure that the DMA points to the first pixel of data and not the
first entry in the frame buffer which is the beginning of the 512 byte
palette."Signed-off-by: Martin Pietryka
Reviewed-by: Hannes Schmelzer
Tested-by: Hannes Schmelzer -
To support 16bpp we just need to change the raster_ctrl register
accordingly. Also 32bpp mode should work as well, but was not tested.
According to the TRM the uppermost byte will be ignored when
LCD_TFT_24BPP_UNPACK is set.The switch logic is based on the Linux kernel tilcdc driver:
drivers/gpu/drm/tilcdc/tilcdc_crtc.c: lines 407 through 419
(kernel was checked out at commit: bcc981e9ed8)Signed-off-by: Martin Pietryka
Reviewed-by: Hannes Schmelzer
Tested-by: Hannes Schmelzer -
While the OMAP3 has 64KiB of SRAM, per the TRM the download area is only
from 0x40200000 to 0x4020F000 and exceeding that will cause failure to
boot. Further, we need to make sure that we don't run into
SRAM_SCRATCH_SPACE_ADDR as once SPL is running we will write values
there and would corrupt our running image.Cc: Adam Ford
Cc: Steve Sakoman
Signed-off-by: Tom Rini -
LDO3 is used for the VGA output, this fixes a regression where the VGA
output on these boards would no longer work.Signed-off-by: Hans de Goede
Acked-by: Ian Campbell -
We are running with the caches disabled when mctl_mem_matches gets called,
but the cpu's write buffer is still there and can still get in the way,
add a memory barrier to fix this.This avoids mctl_mem_matches always returning false in some cases, which
was resulting in:U-Boot SPL 2015.07 (Apr 14 2016 - 18:47:26)
DRAM: 1024 MiBU-Boot 2015.07 (Apr 14 2016 - 18:47:26 +0200) Allwinner Technology
CPU: Allwinner A23 (SUN8I)
DRAM: 512 MiBWhere 512 MiB is the right amount, but the DRAM controller would be
initialized for 1024 MiB.Signed-off-by: Hans de Goede
Acked-by: Ian Campbell
26 Apr, 2016
21 commits
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The patch:
"configs: Re-sync almost all of cmd/Kconfig"
(sha1: 78d1e1d0a157c8b48ea19be6170b992745d30f38)
doesn't remove empty if-endif. This patch is fixing it.Signed-off-by: Michal Simek
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The recently added uniphier_ld20_defconfig missed the tree-wide
re-sync by commit 89cb2b5f8be4 ("configs: Re-sync with cmd/Kconfig").Signed-off-by: Masahiro Yamada
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Signed-off-by: Tom Rini
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The defconfig/config.h file were merged but were already out of sync
with mainline. This brings them further into line now.Cc: Richard Hu
Cc: Fabio Estevam
Signed-off-by: Tom Rini -
According to the TRM you have to set bits [21:20] to 0b10 for RAW mode, so
(0x10 << 20) is obviously wrong here.Signed-off-by: Martin Pietryka
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The terminal condition in the area where a PCI device is scanned is wrong,
and 1f.7 isn't scanned.Signed-off-by: Yoshinori Sato
Reviewed-by: Bin Meng -
This allows to drop annoying (char *) casts when setting the host
name of struct sdhci_host.Signed-off-by: Masahiro Yamada
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ABB should be initialized for all required domains voltage domain
for DRA7: IVA, GPU, EVE in addition to the existing MPU domain. If
we do not do this, kernel configuring just the frequency using the
default boot loader configured voltage can fail on many corner lot
units and has been hard to debug. This specifically is a concern with
DRA7 generation of SoCs since other than VDD_MPU, all other domains
are only permitted to setup the voltages to required OPP only at boot.Reported-by: Richard Woodruff
Signed-off-by: Nishanth Menon -
Since we setup the voltage and frequency for the MM domain, we *must*
setup the ABB configuration needed for the domain as well. If we do not
do this, kernel configuring just the frequency using the default boot
loader configured voltage can fail on many corner lot units.Reported-by: Richard Woodruff
Signed-off-by: Nishanth Menon -
ABB TX_DONE mask will vary depending on ABB module. For example,
3630 never had ABB on IVA domain, while OMAP5 does use ABB on MM domain,
DRA7 has it on all domains with the exception of CORE, RTC.Hence, move the txdone mask definition over to structure describing
voltage domain.Signed-off-by: Nishanth Menon
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This information is already available under vcores->volts.efuse.reg.
There is no reason for duplicating the information since AVS Class 0
definitions are common for OMAP5 and DRA7 and defined with
STD_FUSE_OPP_* macros. This allows a central location of defining
the ABB and voltage definitions especially since they are reused.This also makes it simpler to prevent mistakes involved when changing
the boot OPP for the device.Signed-off-by: Nishanth Menon
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Remove several hundred lines of content surrounded by:
#if 0 /* Moved to malloc.h */
... moved stuff ...
#endif /* 0 */ /* Moved to malloc.h */Signed-off-by: Robert P. J. Day
Reviewed-by: Tom Rini -
The error message "spl: mmc block read error" may come from two
different functions, so we should better annotate the function name
where the error comes from to help debugging.Signed-off-by: Fabio Estevam
Reviewed-by: Tom Rini -
This patch updates and simplifies the hikey README. The old
instructions were hard to follow, and convoluted.This patch also updates the link to the mcuimage.bin which was outdated.
Using an outdated mcuimage.bin results in the additional a53 cores
not coming online when the kernel issues PSCI requests to
arm trusted firmware (ATF).Signed-off-by: Peter Griffin
Reviewed-by: Tom Rini -
The memory node gets automatically generated by U-Boot
in arch_fixup_fdt(), before passing control to the kernel
using U-Boots representation of the dram banks.However the upstream kernel uses the memory node to carve-out
regions of RAM for various purposes. To make this work without
changing arch_fixup_fdt() which will effect many platforms
we replicate the upstream memory node layout using the dram
banks.Signed-off-by: Peter Griffin
Reviewed-by: Tom Rini -
This is a binding which only exists in U-Boot, but is
required to get working serial in U-Boot.Signed-off-by: Peter Griffin
Reviewed-by: Tom Rini -
This allows the reset command to reset the board from
u-boot.=> reset
resetting ...
INFO: BL1: 0xf9810000 - 0xf9818000 [size = 32768]
NOTICE: Booting Trusted Firmware
NOTICE: BL1: v1.1(debug):7fb9b0e
NOTICE: BL1: Built : 17:06:41, Apr 19 2016Signed-off-by: Peter Griffin
Reviewed-by: Tom Rini -
Currently only the serial pl01x driver is using DT,
and the other drivers still use platform data but
as more DT lands in the upstream kernel the aim is
to migrate the other drivers over to DT as well to
have a fully DT configured hikey u-boot.Signed-off-by: Peter Griffin
Reviewed-by: Tom Rini -
This patch adds myself as maintainer for the hikey
U-Boot port.Signed-off-by: Peter Griffin
Reviewed-by: Tom Rini
