27 Apr, 2020
3 commits
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Secure Storage service in Trusty OS will compute
the encrypted mmc frame and the rpmb proxy inject the frame
to driver directly. So that need to export RPMB related
interface for Secure Storage proxy use.Change-Id: I7f69831a20a440f597d323b610fa615fd4344d05
Signed-off-by: Haoran.Wang
(cherry picked from commit 4d2c1873ce8221e35874265e41dc42a6df169659)
(cherry picked from commit ce4e9dc35ff89a2429224ae6d0ffb4109cb42e28)
(cherry picked from commit 412ece12209e2f916616053ad65b421e95c07955) -
Add the fuse checking in drivers, when the module is disabled in fuse,
the driver will not work.Changed drivers: BEE, GPMI, APBH-DMA, ESDHC, FEC, QSPI, ECSPI, I2C,
USB-EHCI, GIS, LCDIF and EPDC.Signed-off-by: Ye Li
(cherry picked from commit 1704e116f9b39aeb99201919a18bc2b1e19a980e)
(cherry picked from commit 2d3b5df8530cd5ef883750378838dea7c40259af)
(cherry picked from commit 6e8c9ae136bee8ec0121c1db4b935510caad09db)
(cherry picked from commit 99b54a6965904a879afdb6883a519de726cb4e96) -
Should use CONFIG_IS_ENABLED not IS_ENABLED for CLK driver, so it will
check the CONFIG_SPL_CLK when building SPLMove init_clk_usdhc to non-clk driver case, since assigned-clocks properties
will initialize the clocks by clk driver.Signed-off-by: Ye Li
(cherry picked from commit be51cba531a985f6bde70213856ee957b80562dd)
23 Apr, 2020
1 commit
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When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode,
the actual clock rate is just half of the expected clock.This patch set the DDR_EN bit first for DDR mode, hardware divide
the usdhc clock automatically, then follow the original sdr clock
setting method.Signed-off-by: Haibo Chen
Signed-off-by: Ye Li
(cherry picked from commit 2a8a0cf0f5d2fcb06d217e3d026219532fed5eb7)
(cherry picked from commit c340cddc28f7a314ae52add5d934c7194a83404c)
03 Apr, 2020
2 commits
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According to the HW team, for some reason the normal clock select code
picks what appears to be a perfectly valid 375KHz SD card clock, based
on the CAR clock source and SDMMC1 controller register settings (CAR =
408MHz PLLP0 divided by 68 for 6MHz, then a SD Clock Control register
divisor of 16 = 375KHz). But the resulting SD card clock, as measured by
the HW team, is 700KHz, which is out-of-spec. So the WAR is to use the
values given in the TRM PLLP table to generate a 400KHz SD-clock (CAR
clock of 24.7MHz, SD Clock Control divisor of 62) only for SDMMC1 on
T210 when the requested clock is
Reviewed-by: Jaehoon Chung -
As per the T210 TRM, when running at 3.3v, the SDMMC1 tap/trim and
autocal values need to be set to condition the signals correctly before
talking to the SD-card. This is the same as what's being done in CBoot,
but it gets reset when the SDMMC1 HW is soft-reset during SD driver
init, so needs to be repeated here. Also set autocal and tap/trim for
SDMMC3, although no T210 boards use it for SD-card at this time.Signed-off-by: Tom Warren
Reviewed-by: Jaehoon Chung
09 Mar, 2020
6 commits
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The 4 bit MMC controllers have an internal debounce for the SDCD line
with a debounce delay of 1 second. Therefore, after clocks to the IP are
enabled, software has to wait for this time before it can power on the
controller.Add a deferred_probe() callback which polls on sdcd for a maximum of 2 seconds
before switching on power to the controller or (in the case of no card)
returning a ENOMEDIUM. This pushes the 1 second wait time to when the
card is actually needed rather than at every probe() making sure that
users who don't insert an SD card in the slot don't have to wait such a
long time.Signed-off-by: Faiz Abbas
Signed-off-by: Lokesh Vutla -
With the latest RIOT, there is a different otap delay value for each
speed mode. Add a new binding with every supported speed mode. Also
disable a given speed mode in the host caps if its corresponding
otap-del-sel is not present.Signed-off-by: Faiz Abbas
Signed-off-by: Lokesh Vutla -
MMC_LEGACY & SD_LEGACY are not differentiated timings in the spec and
don't have any meaningful differences. Therefore, get rid of all
references to SD_LEGACY and use MMC_LEGACY to mean both of them.Signed-off-by: Faiz Abbas
Signed-off-by: Lokesh Vutla -
Add the sdhci_deferred_probe() function to register as the
deferred_probe() callback to the mmc core. It will in turn call the
deferred_probe() callback of the platform drivers as declared in the
sdhci_ops.Signed-off-by: Faiz Abbas
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Add a deferred_probe() API for platforms that want to do some
configurations just before starting to enumerate the device.Signed-off-by: Faiz Abbas
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Initial DesignWare based DM support for Cortina Access CAxxxx SoCs.
Signed-off-by: Arthur Li
Signed-off-by: Alex Nemirovsky
20 Feb, 2020
6 commits
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This driver currently performs cache operation before the DMA start,
but does nothing after the DMA completion.When reading data by DMA, the cache invalidation is needed also after
finishing the DMA transfer. Otherwise, the CPU might read data from
the cache instead of from the main memory when speculative memory read
or memory prefetch occurs.Instead of calling the cache operation directly, this commit adds
dma_unmap_single(), which performs cache invalidation internally,
but drivers do not need which operation is being run.Signed-off-by: Masahiro Yamada
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Currently, sdhci_prepare_dma() calls flush_cache() regardless of the
DMA direction.Actually, cache invalidation is enough when reading data from the device.
This is correctly handled by dma_map_single(), which mimics the DMA-API
in Linux kernel. Drivers can be agnostic which cache operation occurs
behind the scene.This commit also sanitizes the difference between the virtual address
and the dma address.Signed-off-by: Masahiro Yamada
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host->mmc is already (struct mmc *).
memalign() returns an opaque pointer, so there is no need for casting.
Signed-off-by: Masahiro Yamada
Reviewed-by: Jaehoon Chung -
Use {lower,upper}_32_bits() instead of the combination of cast
and shift.Signed-off-by: Masahiro Yamada
Reviewed-by: Jaehoon Chung -
The same code is run for both SDHCI_QUIRK_32BIT_DMA_ADDR and
define(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER).Unify the code.
Signed-off-by: Masahiro Yamada
Reviewed-by: Jaehoon Chung -
Using the global variable does not look nice.
Add a new field sthci::align_buffer to point to the bounce buffer.
Signed-off-by: Masahiro Yamada
Reviewed-by: Jaehoon Chung
19 Feb, 2020
3 commits
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The implementation of dma_map_single() and dma_unmap_single() is
exactly the same for all the architectures that support them.Factor them out to , and make all drivers to
include instead of .If we need to differentiate them for some architectures, we can
move the generic definitions to .Add some comments to the helpers. The concept is quite similar to
the DMA-API of Linux kernel. Drivers are agnostic about what is
going on behind the scene. Just call dma_map_single() before the
DMA, and dma_unmap_single() after it.Signed-off-by: Masahiro Yamada
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dma_unmap_single() takes the dma address, not virtual address.
Signed-off-by: Masahiro Yamada
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The reference manuals for MPC8308 and MPC8309 both say that the
esdhcctl aka DMA Control Register "is implemented as SDHCCR" in the
System configuration registers. Unfortunately, that doesn't mean that
the registers are just mirrors of each other - any write to esdhcctl
is simply ignored. So to actually enable cache snooping, we
unfortunately have to add a little ifdeffery.There is, naturally, no description of the bit fields of esdhcctl in
the MPC8309 manual, but comparing the description of esdhcctl from the
LS1021A reference manual to the description of the sdhccr in MPC8309,
one also finds that the fields are bit-reversed, so the bit to set is
0x02000000 rather than 0x00000040 - this is also what board_mmc_init()
uses in the two gdsys/mpc8308/ boards.Signed-off-by: Rasmus Villemoes
Reviewed-by: Yangbo Lu
17 Feb, 2020
5 commits
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These functions are defined before the callers.
Signed-off-by: Masahiro Yamada
Reviewed-by: Peng Fan -
Since commit 01298da31d92 ("mmc: Change mode when switching to a boot
partition"), errors in mmc_select_mode_and_width() are ignored.
The return value should be checked.Fixes: 01298da31d92 ("mmc: Change mode when switching to a boot partition")
Signed-off-by: Masahiro Yamada
Reviewed-by: Jaehoon Chung -
Cadence sent out an errata report to their customers of this IP.
This errata is not so severe, but the tune request should be sent
twice to avoid the potential issue.Quote from the report:
Problem Summary
---------------
The IP6116 SD/eMMC PHY design has a timing issue on receive data path.
This issue may lead to an incorrect values of read/write pointers of
the synchronization FIFO. Such a situation can happen at the SDR104
and HS200 tuning procedure when the PHY is requested to change a phase
of sampling clock when moving to the next tuning iteration.Workarounds
-----------
The following are valid workarounds to resolve the issue:1. In eMMC mode, software sends tune request twice instead of once at
each iteration. This means that the clock phase is not changed on
the second request so there is no potential for clock instability.
2. In SD mode, software must not use the hardware tuning and instead
perform an almost identical procedure to eMMC, using the HRS34 Tune
Force register.Signed-off-by: Masahiro Yamada
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erase_grp_size is used, when MMC_WRITE is enabled.
- error: ‘struct mmc’ has no member named ‘erase_grp_size’Signed-off-by: Jaehoon Chung
Reviewed-by: Peng Fan -
If the host has Broken R1B, use only R1 response type.
Signed-off-by: Bharat Kumar Reddy Gooty
Signed-off-by: Vladimir Olovyannikov
06 Feb, 2020
2 commits
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At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.Move the compatibility features into a separate header file.
Signed-off-by: Simon Glass
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At present devres.h is included in all files that include dm.h but few
make use of it. Also this pulls in linux/compat which adds several more
headers. Drop the automatic inclusion and require files to include devres
themselves. This provides a good indication of which files use devres.Signed-off-by: Simon Glass
Reviewed-by: Anatolij Gustschin
29 Jan, 2020
1 commit
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- Various exynos fixes
26 Jan, 2020
1 commit
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Drop local dma_map_single() and dma_unmap_single() and use arch specific
common implementationSigned-off-by: Vignesh Raghavendra
Acked-by: Masahiro Yamada
23 Jan, 2020
1 commit
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Read generic MMC properties from device-tree. This allows to specify for
example cd-inverted property and let MMC core to properly handle such
case.Signed-off-by: Marek Szyprowski
Reviewed-by: Anand Moon
Signed-off-by: Minkyu Kang
21 Jan, 2020
1 commit
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K3 J721E:
* DMA support.
* MMC and ADMA support.
* EEPROM support.
* J721e High Security EVM support.
* USB DT nodesK3 AM654:
* Fixed boot due to pmic probe error.
* USB support and DT nodes.
* ADMA supportDRA7xx/AM57xx:
* BBAI board support
* Clean up of net platform code under board/tiAM33/AM43/Davinci:
* Reduce SPL size for omap3 boards.
* SPL DT support for da850-lcdk
* PLL divider fix for AM335x
20 Jan, 2020
2 commits
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Add Support for writing to PHY registers for J721e. There are number of
differences between the J721e 8 bit PHY, J721e 4 bit PHY and AM654 PHY.
Create a driver_data structure with an ops and flags field and use the
flags field to indicate these differences. The differences are as
follows:1. The J721e 4 bit instance PHY does not have a DLL. Introduce a
DLL_PRESENT flag to make sure that DLL related registers are accessed
only where they are present. Also add a separate set_ios_post()
callback.2. The J721e 8 bit instance is not muxed with anything else inside the
SoC and hence the IOMUX_ENABLE filed does not exist. Add a flag which is
used to indicate the presence of this field.3. The register field used to select DLL frequency is 3 bit wide in
J721e as compared to 2 bits in AM65x. Add another flag that
distinguishes these fields.4. The strobe select field is 8 bit wide as compared to 4 bit wide for
AM65x. Add yet another flag to indicate this difference. Strobe select
is used only for HS400 speed mode, support for which has not been added
in AM65x.Signed-off-by: Faiz Abbas
Signed-off-by: Lokesh Vutla -
Get clk_xin by name instead of by index to avoid having to put clocks in
the same order in all devices.Signed-off-by: Faiz Abbas
Signed-off-by: Lokesh Vutla
18 Jan, 2020
1 commit
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At present panic() is in the vsprintf.h header file. That does not seem
like an obvious choice for hang(), even though it relates to panic(). So
let's put hang() in its own header.Signed-off-by: Simon Glass
[trini: Migrate a few more files]
Signed-off-by: Tom Rini
17 Jan, 2020
1 commit
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- Cleanup of fsl_esdhc driver together with arch/defconfig change
- Add quirk for APP_CMD retry
16 Jan, 2020
4 commits
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This patch add mmc and sd support for Mediatek MT7622 SoCs
Signed-off-by: Sam Shih
Reviewed-by: Ryder Lee -
For CMD21 tuning data, the 128/64 bytes data may coming in very
short time, before msdc_start_data(), the read data has already
come, in this case, clear MSDC_INT will cause the interrupt disappear
and lead to the thread hang.the solution is just clear all interrupts before command was sent.
Signed-off-by: mingming lee
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This patch adds mmc support for MediaTek MT8512/MT8110 SoCs.
MT8512/MT8110 SoCs puts the tune register at top layer, so
need add new code to support it.Signed-off-by: mingming lee
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Fix typo in description of MMC_QUIRKS config option.
Signed-off-by: Joel Johnson
