18 Dec, 2014
7 commits
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Implement a feature to allow fastboot to write the downloaded image
to the space reserved for the Protective MBR and the Primary GUID
Partition Table.
Additionally, prepare and write the Backup GUID Partition Table.Signed-off-by: Steve Rae
Tested-by: Lukasz Majewski
[Test HW: Exynos4412 - Trats2] -
Signed-off-by: Steve Rae
Tested-by: Lukasz Majewski
[Test HW: Exynos4412 - Trats2] -
In function dfu_get_buf(), the size of allocated buffer could
be defined by the env variable. The size from this variable
was passed for memalign() without checking its value.
And the the memalign will return non null pointer for size 0.This could possibly cause data abort, so now the value of var
is checked before use. And if this variable is set to 0 then
the default size will be used.This commit also changes the base passed to simple_strtoul()
to 0. Now decimal and hex values can be used for the variable
dfu_bufsiz.Signed-off-by: Przemyslaw Marczak
Tested-by: Lukasz Majewski
[TestHW: Exynos4412-Trats2] -
Some pointers in function download_tail() were not checked
before the use. This could possibly cause the data abort.
To avoid this, check if the pointers are not null is added.Signed-off-by: Przemyslaw Marczak
Tested-by: Lukasz Majewski
[TestHW: Exynos4412-Trats2] -
The function mmc_block_op() is the last function before
the physicall data write, but the mmc device pointer is not
checked. If mmc device not exists, then data abort will occur.
To avoid this, first the mmc device pointer is checked.Signed-off-by: Przemyslaw Marczak
Tested-by: Lukasz Majewski
[TestHW: Exynos4412-Trats2] -
The fastboot continue command is defined to exit fastboot and continue
autoboot. This commit implements the continue command and the exiting of
fastboot only. Subsequent u-boot commands can be processed after exiting
fastboot. Autoboot should implement a boot script such as "fastboot; mmc
read ; bootm" to fully implement the fastboot continue function.Signed-off-by: Rob Herring
Tested-by: Lukasz Majewski
[TestHW: Exynos4412-Trats2] -
In order to add detach functions for fastboot, make the DFU detach related
functions common so they can be shared.Signed-off-by: Rob Herring
Tested-by: Lukasz Majewski
[TestHW: Exynos4412-Trats2]
16 Dec, 2014
2 commits
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When receive data, the RXRDY in status register set by hardware
after a new packet has been stored in the endpoint FIFO. After,
we copy from FIFO, we clear it, make the FIFO can be accessed
again.
In the receive_data() function, this bit RXRDY has been cleared.
So, after the receive_data() function return, this bit should
not be cleared again, or else it will cause the accessing FIFO
corrupt, which will make the data loss.Signed-off-by: Bo Shen
15 Dec, 2014
2 commits
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Use asmlinkage defined in include/linux/linkage.h if necessary.
Actually no ARM board uses asmlinkage, so this commit has no impact.Signed-off-by: Masahiro Yamada
Cc: Albert ARIBAUD -
Commit 65dd74a674d6 (x86: ivybridge: Implement SDRAM init) introduced
x86-specific asmlinkage into arch/x86/include/asm/config.h.Commit ed0a2fbf14f7 (x86: Add a definition of asmlinkage) added the
same macro define again, this time, into include/common.h.
(Please do not add arch-specific stuff to include/common.h any more;
it is already too cluttered.)The generic asmlinkage is defined in . If you want
to override it with an arch-specific one, the best way is to add it
to like Linux Kernel.Signed-off-by: Masahiro Yamada
Cc: Simon Glass
Tested-by: Simon Glass
14 Dec, 2014
24 commits
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FSP builds a series of data structures called the Hand-Off-Blocks
(HOBs) as it progresses through initializing the silicon. These data
structures conform to the HOB format as described in the Platform
Initialization (PI) specification Volume 3 Shared Architectual
Elements specification, which is part of the UEFI specification.Create a simple command to parse the HOB list to display the HOB
address, type and length in bytes.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Per Intel FSP architecture specification, FSP provides 3 routines
for bootloader to call. The first one is the TempRamInit (aka
Cache-As-Ram initialization) and the second one is the FspInit
which does the memory bring up (like MRC for other x86 targets)
and chipset initialization. Those two routines have to be called
before U-Boot jumping to board_init_f in start.S.The FspInit() will return several memory blocks called Hand Off
Blocks (HOBs) whose format is described in Platform Initialization
(PI) specification (part of the UEFI specication) to the bootloader.
Save this HOB address to the U-Boot global data for later use.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Use inline assembly codes to call FspNotify() to make sure parameters
are passed on the stack as required by the FSP calling convention.Signed-off-by: Bin Meng
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This is the initial import from Intel FSP release for Queensbay
platform (Tunnel Creek processor and Topcliff Platform Controller
Hub), which can be downloaded from Intel website.For more details, check http://www.intel.com/fsp.
Note: U-Boot coding convention was applied to these codes, so it
looks completely different from the original Intel release.
Also update FSP support codes license header to use SPDX ID.Signed-off-by: Bin Meng
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Add Intel Tunnel Creek SPI controller support which is an ICH7
compatible device.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Movie setup_pch_gpios() in the ich6-gpio driver to the board support
codes, so that the driver does not need to know any platform specific
stuff (ie: include the platform specifc chipset header file).Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Move GD_BIST from lib/asm-offsets.c to arch/x86/lib/asm-offsets.c
as it is x86 arch specific stuff. Also remove GENERATED_GD_RELOC_OFF
which is not referenced anymore.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Refactor u-boot.rom build rules by utilizing quiet_cmd_ and cmd_
macros. Also make writing mrc.bin and pci option rom to u-boot.rom
optional and remove mrc.bin from its dependent file list as not
every x86 board port needs mrc binary blob.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
To allow these options to be specified together, separate them out.
Change-Id: Ib93f11cd51eb3302127f4c82936ff2b44c88d5a2
Signed-off-by: Simon Glass -
Currently ifdtool only supports writing one file (-w) at a time.
This looks verbose when generating u-boot.rom for x86 targets.
This change allows at most 16 files to be written simultaneously.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This
will not be the case when adding additional board support. Hence we
make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the
board Kconfig file select the default ROM_SIZE.Signed-off-by: Bin Meng
Acked-by: Simon Glass -
ICH 7 SPI controller only supports byte program (02h) for SST flash.
Word program (ADh) is not supported.Signed-off-by: Bin Meng
Reviewed-by: Jagannadha Sutradharudu Teki -
ICH 7 SPI controller only supports array read command (03h).
Fast array read command (0Bh) is not supported.Signed-off-by: Bin Meng
Acked-by: Simon Glass
Tested-by: Simon Glass
Reviewed-by: Jagannadha Sutradharudu Teki -
Enabled byte program support for sst flashes in sf.
Few controllers will only support BP, so this patch gives
a tx transfer flag to set the BP so-that sf will operate
on byte program transfer.A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI
controller to use byte program op for SST flash.Signed-off-by: Jagannadha Sutradharudu Teki
Tested-by: Bin Meng -
Currently if SST flash advertises SST_WP flag in the params table
the word program command (ADh) with auto address increment will be
used for the flash write op. However some SPI controllers do not
support the word program command (like the Intel ICH 7), the byte
programm command (02h) has to be used.Signed-off-by: Bin Meng
Acked-by: Simon Glass
Tested-by: Simon Glass
Reviewed-by: Jagannadha Sutradharudu Teki -
At present SECT_4K is the same as SST_WP so we cannot tell these apart. Fix
this so that the table in sf_params.c can be used correctly.Reported-by: Jens Rottmann
Signed-off-by: Simon Glass
Reviewed-by: Jagannadha Sutradharudu Teki -
Few of the spi controllers are only supports array slow
read which is quite different behaviour compared to others.So this fix on sf will correctly handle the slow read supported
controllers.Signed-off-by: Jagannadha Sutradharudu Teki
Tested-by: Bin Meng -
We should include common.h before other includes. This actually causes
a build error on chromebook_link.Signed-off-by: Simon Glass
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Current code does not set gpio output value in ich6_gpio_direction_output(),
fix it.Signed-off-by: Axel Lin
Acked-by: Simon Glass -
The ich spi controller driver spi_xfer() tries to align reading
address to 64 bytes when doing spi data in, which causes a bug of
either infinite loop or a huge size memcpy().Actually the ich spi controller does not have such requirement of
64 bytes alignment when reading data from spi slave devices.Signed-off-by: Bin Meng
Acked-by: Simon Glass
Tested-by: Simon Glass
13 Dec, 2014
5 commits
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The card_caps bit should denote the card capability to use DDR mode,
but we need the flag indicating that the DDR mode is active.Signed-off-by: Andrew Gabbasov
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Block length for write and read commands is fixed to 512 bytes
when the card is in Dual Data Rate mode. If block length read from CSD
is different, make sure the driver will use correct length
in all further calculations and settings.Signed-off-by: Andrew Gabbasov
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Since the driver doesn't work in 1.2V or 1.8V signaling level modes,
Dual Data Rate mode can be supported by the driver only if it is supported
by the card in regular 3.3V mode. So, check for a particular single
bit in card type field.Signed-off-by: Andrew Gabbasov
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If the MMC_MODE_DDR_52MHz flag is set in card capabilities bitmask,
it is never cleared, even if switching to DDR mode fails, and if
the controller driver uses this flag to check the DDR mode, it can
take incorrect actions.Also, DDR related checks in mmc_startup() incorrectly handle the case
when the host controller does not support some bus widths (e.g. can't
support 8 bits), since the host_caps is checked for DDR bit, but not
bus width bits.This fix clearly separates using of card_caps bitmask, having there
the flags for the capabilities, that the card can support, and actual
operation mode, described outside of card_caps (i.e. bus_width and
ddr_mode fields in mmc structure). Separate host controller drivers
may need to be updated to use the actual flags. Respectively,
the capabilities checks in mmc_startup are made more correct and clear.Also, some clean up is made with errors handling and code syntax layout.
Signed-off-by: Andrew Gabbasov
