20 Jan, 2017
2 commits
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commit: 65f83802b7a5b "serial: 16550: Add getfcr accessor"
breaks u-boot commandline working with long commands
sending to the board.Since the above patch, you have to setup the fcr register.
For board/archs which enable OF_PLATDATA, the new field
fcr in struct ns16550_platdata is not filled with a
default value ...This leads in not setting up the uarts fifo, which ends
in problems, when you send long commands to u-boots
commandline.Detected this issue with automated tbot tests on am335x
based shc board.The error does not popup, if you type commands. You need
to copy&paste a long command to u-boots commandshell
(or send a long command with tbot)Possible boards/plattforms with problems:
./arch/arm/cpu/arm926ejs/lpc32xx/devices.c
./arch/arm/mach-tegra/board.c
./board/overo/overo.c
./board/quipos/cairo/cairo.c
./board/logicpd/omap3som/omap3logic.c
./board/logicpd/zoom1/zoom1.c
./board/timll/devkit8000/devkit8000.c
./board/lg/sniper/sniper.c
./board/ti/beagle/beagle.c
./drivers/serial/serial_rockchip.cSigned-off-by: Heiko Schocher
Signed-off-by: Ladislav Michl
Tested-by: Adam Ford
Reviewed-by: Tom Rini
19 Jan, 2017
38 commits
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On LS1012ARDB board, three dual 1:4 mux/demux devices drive the SDHC2
signals to eMMC, SDIO wifi, SPI and Ardiuno shield. Only when we select
eMMC and SDIO wifi, the SDHC2 could be used. Otherwise, the command
inhibit bits of eSDHC2_PRSSTAT register will never release. This would
cause below continious error messages in linux since it uses polling
mode to detect card.
"mmc1: Controller never released inhibit bit(s)."
"mmc1: Controller never released inhibit bit(s)."
"mmc1: Controller never released inhibit bit(s)."
This patch is to define esdhc_status_fixup function for RDB to disable
SDHC2 status if no SDIO wifi or eMMC is selected.Signed-off-by: Yangbo Lu
Reviewed-by: York Sun -
The LS1012AQDS board has a hardware issue. When there is no eMMC
adapter card inserted in SDHC2 adapter slot, the command inhibit
bits of eSDHC2_PRSSTAT register will never release. This would cause
below continious error messages in linux since it uses polling mode
to detect card.
"mmc1: Controller never released inhibit bit(s)."
"mmc1: Controller never released inhibit bit(s)."
"mmc1: Controller never released inhibit bit(s)."
This patch is to define esdhc_status_fixup function for QDS to
disable SDHC2 status if no eMMC adapter card is detected.Signed-off-by: Yangbo Lu
Reviewed-by: York Sun -
Move fdt fixup of 'status' property into a weak function. This allows
board to define 'status' fdt fixup by themselves.Signed-off-by: Yangbo Lu
Reviewed-by: York Sun -
Enable PPA for ls1043ardb NOR boot and ls1046ardb QSPI boot.
Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun -
Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun -
Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to
Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI.Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun -
Signed-off-by: Hou Zhiqiang
[York S: clean up scripts/config_whitelist.txt]
Reviewed-by: York Sun -
For 64-bit kernel, there is a warning about x1-x3 nonzero in violation
of boot protocol. To fix this issue, input argument 4 is added for
armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will
be set to the right value, such as zero.Signed-off-by: Alison Wang
Reviewed-by: Alexander Graf
Tested-by: Ryan Harkin
Tested-by: Michal Simek
Reviewed-by: York Sun -
The default MSI node in kernel tree is for LS1043A rev1.0 silicon, if
rev1.1 silicon used, need to fixup the MSI node to match it.Signed-off-by: Wenbin Song
Signed-off-by: Mingkai Hu
Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun -
The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT]
is used to choose which offset will be used.The LS1043A rev1.0 silicon only supports the CIG offset with 4K
alignment.If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment
is used. 64K alignment is the default setting.Overriding the weak smp_kick_all_cpus, the new impletment is able to
detect GIC offset.The default GIC offset in kernel device tree is using 4K alignment, it
need to be fixed if 64K alignment is detected.Signed-off-by: Wenbin Song
Signed-off-by: Mingkai Hu
Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun -
By default the SATA IP on the ls208Xa SoCs does not generating
coherent/snoopable transactions. This patch enable it in the
sata axicc register.Signed-off-by: Tang Yuantian
Reviewed-by: York Sun -
Add the chip power supply voltage initialization on LS1046ARDB.
Add function power_init_board(), and it will initialize the
PMIC and call the chip power initialization function.Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun -
Set up chip power supply voltage according to voltage ID.
The fuse status register provides the values from on-chip
voltage ID fuses programmed at the factory. These values
define the voltage requirements for the chip.Main operations:
1. Set up the core voltage
2. Set up the SERDES voltage and reset SERDES lanes
3. Enable/disable DDR controller support 0.9V if neededSigned-off-by: Hou Zhiqiang
Reviewed-by: York Sun -
Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun -
Signed-off-by: Hou Zhiqiang
Reviewed-by: Jaehoon Chung
Reviewed-by: York Sun -
This patch adds a simple pmic driver for the mc34vr500 pmic which
is used in conjunction with the fsl T1 and LS1 series SoC.Signed-off-by: Hou Zhiqiang
Reviewed-by: Jaehoon Chung
Reviewed-by: York Sun -
Without a prompt in Kconfig, SECURE_BOOT cannot be selected by
defconfig. The option was dropped unintentionally when defconfig
files were cleaned up. Three targets were impacted
ls1043ardb_SECURE_BOOT, ls2080ardb_SECURE_BOOT,
ls2080aqds_SECURE_BOOT.Signed-off-by: York Sun
Reviewed-by: Simon Glass -
Add secure boot validation of MC, DPC images using
esbc_validate command.Signed-off-by: Sumit Garg
Signed-off-by: Udit Agarwal
Reviewed-by: York Sun -
Update bootscript and its hdr addresses for Layerscape Chasis 3
based platforms instead of individual SoCs.Signed-off-by: Sumit Garg
Signed-off-by: Udit Agarwal
Reviewed-by: York Sun -
Enable driver model for eSDHC on ls1012a rdb and qds boards.
Signed-off-by: Yangbo Lu
Reviewed-by: York Sun -
This patch is to add eSDHC nodes for ls1012a.
Signed-off-by: Yangbo Lu
Reviewed-by: York Sun -
This patch is to add 'fsl,esdhc' into of_match table to support
driver model for QorIQ eSDHC.Signed-off-by: Yangbo Lu
Reviewed-by: York Sun -
There would be compiling error as below when enable driver model for esdhc.
undefined reference to `dm_gpio_get_value'
undefined reference to `gpio_request_by_name_nodev'
This patch is to make GPIO support optional with CONFIG_DM_GPIO. Because
all boards of QorIQ platform don't need it and they just check register for
CD/WP status, only some boards of i.MX platform require this.Signed-off-by: Yangbo Lu
Acked-by: Jaehoon Chung
Reviewed-by: York Sun -
This patch binds the sys_info->freq_systembus to Platform PLL, and
implements the IPs' clock function individually.Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun -
Up to now, there are 3 kind of SoCs under Layerscape Chassis 2,
like LS1043A, LS1046A and LS1012A. But the clocks tree has a
lot of differences, for instance, the IP modules have different
dividers to derive its clock from Platform PLL. And the core
cluster PLL and platform PLL maybe have different reference
clocks, such as LS1012A. Another problem is which clock/PLL
should be described by sys_info->freq_systembus, it is confused
in Layerscape Chissis 2.This patch is to bind the sys_info->freq_systembus to the Platform
PLL, and handle the different divider of IP modules separately
between different SoCs, and separate reference clocks of core
cluster PLL and platform PLL.Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun -
Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun -
For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.For A57/A72, SMPEN bit enables the processor to receive instruction
cache and TLB maintenance operations broadcast from other processors
in the cluster. This bit should be set before enabling the caches and
MMU, or performing any cache and TLB maintenance operations.Signed-off-by: Mingkai Hu
Signed-off-by: Gong Qianyu
Signed-off-by: Mateusz Kulikowski
Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun -
Enable UUID and GPT partition support for NXP's ARM based SoCs
i.e. LS1012A, LS1021A, LS1043A, LS1046A and LS2080A.Also enable DOS partition for LS1012AFRDM boards.
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Enables driver model flag CONFIG_DM_USB for LS1012A platform
in defconfigs.Signed-off-by: Tang Yuantian
Reviewed-by: York Sun -
The LS1012A processor has two integrated USB controllers.
One is USB2.0 controller, the other is USB3.0 controller that
allow direct connection to the USB ports with appropriate
protection circuitry and power supplies.Signed-off-by: Tang Yuantian
Reviewed-by: York Sun -
Clear the content to zero and the ECC error bit of OCRAM1/2.
The OCRAM must be initialized to ZERO by the unit of 8-Byte before
accessing it, or else it will generate ECC error. And the IBR has
accessed the OCRAM before this initialization, so the ECC error
status bit should to be cleared.Signed-off-by: Hou Zhiqiang
Signed-off-by: Pratiyush Srivastava
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
The real size of OCRAM is 128KiB, so correct the size of OCRAM.
And OCRAM reserved 2MiB space, then add a new macro to describe
it, which is used for MMU setup.Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun -
Signed-off-by: Hou Zhiqiang
Reviewed-by: Simon Glass
Reviewed-by: York Sun -
All Layerscape SoCs have supported new PCIe driver based on DM.
The lagecy PCIe driver code is unused and can be removed.Signed-off-by: Minghuan Lian
Signed-off-by: Hou Zhiqiang
Reviewed-by: Simon Glass
Reviewed-by: York Sun -
The patch enables PCIe in ls2080a defconfigs and
removes unused PCIe related macro defines.Signed-off-by: Minghuan Lian
Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun -
The patch enables PCIe and E1000 in ls1046a related defconfigs.
Signed-off-by: Minghuan Lian
Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun -
The patch enables PCIe and E1000 in ls1043a defconfigs and
removes unused PCIe related macro defines.Signed-off-by: Minghuan Lian
Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun -
The patch enables PCIe and E1000 in ls1012a defconfigs and
removes unused PCIe related macro definesSigned-off-by: Minghuan Lian
Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun
