24 Jul, 2019
1 commit
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Add configs to support evk_imx8mm 4GB DDR board. The 4GB DDR will
be split into two banks, one is 3GB (0x4000_0000~0xffff_0000) and
another is 1GB(0x1_0000_0000~0x1_4000_0000).Test: build and boot with or without trusty.
Change-Id: I02f6465fc5709b15fd76820edb846452d011dd56
Signed-off-by: Ji Luo
09 Jul, 2019
1 commit
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There is no DDR_SS_GPR0 exits on i.MX8MN, so skip setting
this register on i.MX8MN.Signed-off-by: Jacky Bai
(cherry picked from commit a8040bc4524687ca026b9960fda18eb19606dade)
24 May, 2019
4 commits
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On, i.MX8MQ, the PLL config must be done when ddrmix
isolation is released. So move the dram pll init after
iso config done. For other i.MX8M SOC, either init pll
before or after isolation is ok.Signed-off-by: Jacky Bai
(cherry picked from commit c5dcc21c214badd5b48b48dfaa62d17ba13c6b17) -
Refine the ddr init driver to make it more reusable for different
DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant
code.Signed-off-by: Jacky Bai
Reviewed-by: Ye Li
(cherry picked from commit 3c0b1b346a891fef7a81856e3ee9019e2b81602d) -
Update the ddrc Qos setting for B1 to align with B0'ssetting.
Correct the initial clock for dram_pll. This setting will be
overwrite before ddr phy training. Although there is no impact
on the dram init, we still need to correct it to eliminate
confusion.Signed-off-by: Bai Ping
Reviewed-by: Ye Li
Tested-by: Robby Cai
(cherry picked from commit 566b798213ab9690966f163de2765acdbfe647a7) -
Since the parameter of dram_pll_init is changed, update to use new.
Also remove non-existed header file.Signed-off-by: Ye Li
19 Mar, 2019
2 commits
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Inactive chip-selects will give invalid values for read_sample so don't
consider them when trying to determine the overall min/max read sample.Signed-off-by: Chris Packham
[https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/18]
Signed-off-by: Chris Packham
Signed-off-by: Stefan Roese -
Based on the JEDEC standard JESD79-3F. The tRAS timings should include
the highest speed bins at a given frequency. This is similar to commit
683c67b ("mv_ddr: ddr3: fix tfaw timimg parameter") where the wrong
comparison was used in the initial implementation.Signed-off-by: Chris Packham
[https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/15]
Signed-off-by: Chris Packham
Signed-off-by: Stefan Roese
10 Mar, 2019
5 commits
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Replace the current rather convoluted code using ad-hoc polling
mechanism with a more straightforward code. Use wait_for_bit_le32()
to poll the DDRCALSTAT register instead of local reimplementation.
It makes no sense to pull for 5 seconds before giving up and trying
to restart the EMIF, so instead wait 500 mSec for the calibration to
complete and if this fails, restart the EMIF and try again. Perform
this 32 times instead of 3 times as the original code did.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Simon Goldschmidt
Cc: Tien Fong Chee -
The EMIF reset code can well use wait_for_bit_le32() instead of all that
convoluted polling code. Reduce the timeout from 100 seconds to 1 second,
since if the EMIF fails to reset itself in 1 second, it's unlikely longer
wait would help. Make sure to clear the EMIF reset request even if the
SEQ2CORE_INT_RESP_BIT isn't asserted.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Simon Goldschmidt
Cc: Tien Fong Chee -
The current EMIF clear timeout handling code was applying bitwise
operations to signed data types and as it was, was extremely hard
to read. Replace it with simple wait_for_bit(). Expand the error
handling to make it more readable too.This patch also changes the timeout for emif_clear() from 14 hours
to 1 second.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Simon Goldschmidt
Cc: Tien Fong Chee -
The debug print is missing a newline, add it.
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Simon Goldschmidt
Cc: Tien Fong Chee -
The Altera Arria10 DDR driver was using constants in a few places
instead of reading registers associated with those constants, fix
this.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen
Cc: Simon Goldschmidt
Cc: Tien Fong Chee
03 Mar, 2019
1 commit
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Moves below DDR specific defines to Kconfig:
CONFIG_FSL_DDR_BIST
CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
CONFIG_FSL_DDR_INTERACTIVE
CONFIG_FSL_DDR_SYNC_REFRESHSigned-off-by: Rajesh Bhagat
Reviewed-by: York Sun
Reviewed-by: Prabhakar Kushwaha
19 Feb, 2019
1 commit
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fsl_ddr_board_options is generally defined in board
board's ddr.c, but some boards like lx2160ardb board
does not need this function.
Defining fsl_ddr_board_options as weak function to
resolve compilation errors for such boards.Signed-off-by: Priyanka Jain
[PK: Fix checkpatch warnings]
Signed-off-by: Prabhakar Kushwaha
01 Jan, 2019
1 commit
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Introduce DDR driver for i.MX8M. The driver will be used by SPL to
initialze DDR PHY and DDR Controller.Signed-off-by: Peng Fan
11 Dec, 2018
1 commit
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Add TFA boot flow for some Layerscape platforms
Add support for lx2160a SoC[trini: Add a bunch of missing MAINTAINERS entries]
Signed-off-by: Tom Rini
10 Dec, 2018
1 commit
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This was unintentionally removed when syncing with upstream.
Signed-off-by: Chris Packham
08 Dec, 2018
1 commit
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This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-18.09 branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.
Specifically this syncs with commit 99d772547314 ("Bump mv_ddr to
release armada-18.09.2").The complete log of changes is best obtained from the mv-ddr-marvell.git
repository but some relevant highlights are:ddr3: add missing txsdll parameter
ddr3: fix tfaw timimg parameter
ddr3: fix trrd timimg parameter
merge ddr3 topology header file with mv_ddr_topology one
mv_ddr: a38x: fix zero memory size scrubbing issueThe upstream code is incorporated omitting the portions not relevant to
Armada-38x and DDR3. After that a semi-automated step is used to drop
unused features with unifdeffind drivers/ddr/marvell/a38x/ -name '*.[ch]' | \
xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \
-UCONFIG_APN806 -UCONFIG_MC_STATIC \
-UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
-UCONFIG_64BIT -UCONFIG_A3700 -UA3900 -UA80X0 \
-UA70X0Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
Tested-by: Baruch Siach
Signed-off-by: Stefan Roese
07 Dec, 2018
1 commit
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LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
4 TZASC instances, etc.SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUsSigned-off-by: Bao Xiaowei
Signed-off-by: Hou Zhiqiang
Signed-off-by: Meenakshi Aggarwal
Signed-off-by: Vabhav Sharma
Signed-off-by: Sriram Dash
Signed-off-by: Priyanka Jain
Reviewed-by: York Sun
15 Sep, 2018
1 commit
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Incorrect type of size variable results in 0 being
returned for sdram sizes greater than or equal to
4GB.Signed-off-by: Dalon Westergreen
27 Jul, 2018
1 commit
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Pass an empty buffer instead of NULL if the hwconfig environment
variable isn't set.Signed-off-by: Jeremy Gebben
Cc: Stefano Babic
Cc: York Sun
Reviewed-by: York Sun
12 Jul, 2018
3 commits
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The SDRAM must first be rewritten by zeroes if ECC is used to initialize
the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a
case. This scrubbing implementation turns the caches on temporarily, then
overwrites the whole RAM with zeroes, flushes the caches and turns them
off again. This provides satisfactory performance.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen -
This function was never used in SPL and the default implementation of
dram_bank_mmu_setup() does the same thing. The only difference is the
part which configures OCRAM as cachable, which doesn't really work as
it covers more than the OCRAM.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dinh Nguyen -
Add DDR support for Stratix SoC
Signed-off-by: Chin Liang See
Signed-off-by: Ley Foon Tan
20 May, 2018
1 commit
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Signed-off-by: Tom Rini
18 May, 2018
3 commits
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This patch enables DDR Kconfig support for Arria 10.
Signed-off-by: Tien Fong Chee
Reviewed-by: Dinh Nguyen -
Add DDR driver support for Arria 10.
Signed-off-by: Tien Fong Chee
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Current sdram driver is only applied to gen5 device, hence it is better
to rename sdram driver to more specific name which is related to gen5
device.Signed-off-by: Tien Fong Chee
15 May, 2018
1 commit
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mv_ddr_build_message.c is generated in Marvell's standalone mv_ddr code.
When imported into u-boot we need to add the appropriate SPDX tag and
re-format it slightly.Signed-off-by: Chris Packham
14 May, 2018
6 commits
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Make ddr3_calc_mem_cs_size() global scope and use it in
ddr3_new_tip_ecc_scrub to correctly initialize all of DDR memory.Signed-off-by: Chris Packham
Signed-off-by: Stefan Roese -
This restores support for configuring the timing mode based on the
ddr_topology. This was originally implemented in commit 90bcc3d38d2b
("driver/ddr: Add support for setting timing in hws_topology_map") but
was removed as part of the upstream sync.Signed-off-by: Chris Packham
Signed-off-by: Stefan Roese -
This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-17.10 branch
of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git.The upstream code is incorporated omitting the ddr4 and apn806 and
folding the nested a38x directory up one level. After that a
semi-automated step is used to drop unused features with unifdeffind drivers/ddr/marvell/a38x/ -name '*.[ch]' | \
xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \
-UCONFIG_APN806 -UCONFIG_MC_STATIC \
-UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
-UCONFIG_64BITINTER_REGS_BASE is updated to be defined as SOC_REGS_PHY_BASE.
Some now empty files are removed and the ternary license is replaced
with a SPDX GPL-2.0+ identifier.Signed-off-by: Chris Packham
Signed-off-by: Stefan Roese -
No in-tree code defines SUPPORT_STATIC_DUNIT_CONFIG or
STATIC_ALGO_SUPPORT. Remove ddr3_a38x_mc_static.h and use unifdef to
remove unused sections in the rest of the ddr/marvell/a38x code.Signed-off-by: Chris Packham
Signed-off-by: Stefan Roese -
Move sys_env_device_rev_get() from the ddr training code to
sys_env_lib.c (which currently resides with the serdes code). This
brings sys_env_device_rev_get() into line with sys_env_device_id_get()
and sys_env_model_get().Signed-off-by: Chris Packham
Signed-off-by: Stefan Roese -
PEX_CFG_DIRECT_ACCESS was defined in ddr3_hws_hw_training_def.h despite
only being used in the serdes code. Move this definition to ctrl_pex.h
where all the other PEX defines are. Also remove the duplicate
definition of PEX_DEVICE_AND_VENDOR_ID which is already defined in
ctrl_pex.h.Signed-off-by: Chris Packham
Signed-off-by: Stefan Roese
07 May, 2018
1 commit
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When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.Signed-off-by: Tom Rini
28 Apr, 2018
1 commit
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We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.Signed-off-by: Tom Rini
15 Feb, 2018
1 commit
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Upon further review, not all code authors are in favour of this change.
This reverts commit ee3556bcafbb05e59aabdc31368984e76acaabc4.Signed-off-by: Tom Rini
10 Feb, 2018
1 commit
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To make this driver easier to be reused, dual-license DDR driver.
Signed-off-by: York Sun
CC: Simon Glass
CC: Tom Rini
CC: Heinrich Schuchardt
CC: Thomas Schaefer
CC: Masahiro Yamada
CC: Robert P. J. Day
CC: Alexander Merkle
CC: Joakim Tjernlund
CC: Curt Brune
CC: Valentin Longchamp
CC: Wolfgang Denk
CC: Anatolij Gustschin
CC: Ira W. Snyder
CC: Marek Vasut
CC: Kyle Moffett
CC: Sebastien Carlier
CC: Stefan Roese
CC: Peter Tyser
CC: Paul Gortmaker
CC: Peter Tyser
CC: Jean-Christophe PLAGNIOL-VILLARD
