24 May, 2019
3 commits
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Currently the driver gets value from PSR register, but this register
is only for input mode. For output mode, it always return 0 not the
value we set for output.This patch changes to use DR register, which returns the DR value for
output mode, and PSR value for input mode.Signed-off-by: Ye Li
(cherry picked from commit 4afc3f90943c6b117f79b66d2cd04e64f437b0c2)
(cherry picked from commit 8cca3efba0d508b2c267f8a32b302970dd05244d) -
For GPIO group which shared by multiple masters, it may set in RDC
to shared and semaphore required. Before access the GPIO register,
the GPIO driver must get the RDC semaphore, and release the semaphore
after the GPIO register access.When CONFIG_MXC_RDC is set, the features related to RDC semaphores
is enabled in mxc_gpio driver.Signed-off-by: Ye.Li
(cherry picked from commit 84d63e2e2ce12f714e88baad8b2325684614a7c1)
Signed-off-by: Peng FanConflicts:
drivers/gpio/mxc_gpio.c(cherry picked from commit c9943b9c8a78bb2c9886bfe582e82978387d8dee)
Signed-off-by: Peng Fan
(cherry picked from commit faf94726cac8316c4342e19936f1e03ef283ace3)
(cherry picked from commit 6c0474fe0e4fc543c62b22c05c2702a881f56418)
(cherry picked from commit 7cd5fec7ce6a9ecfdaa1a9c1aaaa0d0ac18a4f86)
(cherry picked from commit 74d68c1b9f098c44992d591616372f0ec5ff13dd) -
Since the i.MX8 GPIO banks are indexed from 0 not 1 on other i.MX platforms,
so we have to adjust the index accordingly.Signed-off-by: Adrian Alonso
Signed-off-by: Ye Li
25 Feb, 2019
1 commit
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gpio_get_value should return 0 or 1, not the value of bit & (1 << pin)
Acked-by: Marek Vasut
Signed-off-by: Julien Beraud
01 Feb, 2019
1 commit
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Allow rockchip boards to use GPIOs before driver model is ready. This is
really only useful for setting GPIOs to enable the early debug console, if
needed on some platforms.Signed-off-by: Simon Glass
Reviewed-by: Philipp Tomsich
29 Jan, 2019
1 commit
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Introduce CONFIG_SPL_DM_PCA953X for SPL usage.
Signed-off-by: Peng Fan
16 Jan, 2019
2 commits
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With the new mscc_bb_spi.c driver, there is no longer use for the
gpio-mscc-bitbang-spi.c driver.Signed-off-by: Lars Povlsen
Reviewed-by: Daniel Schwierzeck -
This add support for the the MSCC serial GPIO driver in MSCC
VCoreIII-based SOCs.By using a serial interface, the SIO controller significantly extends
the number of available GPIOs with a minimum number of additional pins
on the device. The primary purpose of the SIO controller is to connect
control signals from SFP modules and to act as an LED controller.This adds the base driver.
Signed-off-by: Lars Povlsen
09 Jan, 2019
2 commits
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In order to keep SPL code size below the 32Kb limit,
put under CONFIG_SPL_BUILD flag all unused code in SPL.
This is needed for stm32f7xx board which are using SPL.Signed-off-by: Patrice Chotard
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In case "gpio-ranges" property is not present in device tree,
use default value for gpio_count and gpio_range.
This fixes an issue on stm32 F7 and H7 boards where "pinmux status -a"
command didn't return any pin status due to the fact that both stm32 F7
and H7 board DT doesn't use the gpio-ranges property.Fixes: dbf928dd2634a6("gpio: stm32f7: Add gpio bank holes management")
Signed-off-by: Patrice Chotard
01 Jan, 2019
2 commits
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imx for 2019.01
- introduce support for i.MX8M
- fix size limit for Vhybrid / pico boards
- several board fixes
- w1 driver for MX2x / MX5x -
Rename mx8m,MX8M to imx8m,IMX8M
Signed-off-by: Peng Fan
Signed-off-by: Jon Nettleton
19 Dec, 2018
1 commit
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The VCore III SoCs such as the Luton but also the Ocelot can remap an SPI
flash directly in memory. However, for writing in the flash the
communication has to be done by software.Each of the signal used for the SPI are exposed in a single register. In
order to be able to use the soft-spi driver, the management of this pin
is done through this simple gpio driver.Even if the main purpose of this driver is to be used by soft-spi, it can
still be used as a normal gpio driver but with limitation: for example
the first pin can't be used as output.Signed-off-by: Gregory CLEMENT
Reviewed-by: Daniel Schwierzeck
07 Dec, 2018
3 commits
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As all STM32 SoCs supports CONFIG_CLK flag,
it becomes useless in this driver, remove it.Signed-off-by: Patrice Chotard
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To allow access to this define by other driver, move
it into gpio.hSigned-off-by: Patrice Chotard
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In some STM32 SoC packages, GPIO bank has not always 16 gpios.
Several cases can occur, gpio hole can be located at the beginning,
middle or end of the gpio bank or a combination of these 3
configurations.For that, gpio bindings offer the gpio-ranges DT property which
described the gpio bank mapping.Signed-off-by: Patrice Chotard
29 Nov, 2018
1 commit
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As a preparation for merging the socfpga gen5 devicetree files
from Linux, this patch makes the dwapb gpio driver work correctly
without the 'bank-name' property on the gpio-controller nodes.This property is not present in the Linux drivers and thus is not
present in the Linux devicetrees. It is only used to access pins
via bank name.This fallback is necessary since without it, the driver will
return an error code which will lead to an error in U-Boot
startup.The bank names will still be added to the default board device
trees in follow-up patch, but other boards using this driver and
not including the bank name should also work with the socfpga.dtsi
without adding the bank-name property.Signed-off-by: Simon Goldschmidt
18 Nov, 2018
1 commit
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This patch adds GPIO support for the Mediatek MT7621 SoC, tested on
MT7688 (Gardena smart-gateway). The driver is loosly based on the
Linux kernel version.Signed-off-by: Stefan Roese
Cc: Daniel Schwierzeck
Reviewed-by: Daniel Schwierzeck
[fixed checkpatch.pl warnings: Prefer 'unsigned int' to bare use of 'unsigned']
Signed-off-by: Daniel Schwierzeck
17 Nov, 2018
2 commits
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This patch adds gpio get_function ops support.
This function reports the state of a gpio.Signed-off-by: Christophe Kerello
Reviewed-by: Simon Glass
Signed-off-by: Patrice Chotard -
The pca953x_gpio driver uses default value of polarity inversion
register. For some devices like PCA9557 and MAX7310, their polarity
inversion register default value is 0xf0. So for high 4 ports, when
reading their values, the values are inverted as the actual level.This patch clears the polarity inversion register to 0 at init, so
that the port read and write values are aligned.Signed-off-by: Ye Li
Acked-by: Fugang Duan
Acked-by: Peng Fan
Signed-off-by: Anatolij Gustschin
15 Nov, 2018
1 commit
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When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be
bound before relocation. However due to a bug in the DM core,
the flag only takes effect when devices are statically declared
via U_BOOT_DEVICE(). This bug has been fixed recently by commit
"dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in
lists_bind_fdt()", but with the fix, it has a side effect that
all existing drivers that declared DM_FLAG_PRE_RELOC flag will
be bound before relocation now. This may expose potential boot
failure on some boards due to insufficient memory during the
pre-relocation stage.To mitigate this potential impact, the following changes are
implemented:- Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver
only supports configuration from device tree (OF_CONTROL)
- Keep DM_FLAG_PRE_RELOC flag in the driver only if the device
is statically declared via U_BOOT_DEVICE()
- Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for
drivers that support both statically declared devices and
configuration from device treeSigned-off-by: Bin Meng
Reviewed-by: Simon Glass
Reviewed-by: Patrick Delaunay
14 Nov, 2018
1 commit
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Commit fb01e07a95 accidentally broke initialisation of GPIO
descriptor flags from device tree: currently the active low
flag from gpio-specifier is always ignored. Fix it.Signed-off-by: Anatolij Gustschin
Cc: Mario Six
25 Oct, 2018
1 commit
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Merged imx8 architecture, fix build for imx8 + warnings
22 Oct, 2018
1 commit
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Add i.MX8 support, there are 8 GPIO banks.
Signed-off-by: Peng Fan
Reviewed-by: Anatolij Gustschin
Cc: Stefano Babic
11 Oct, 2018
2 commits
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Push generic defines of gpio.h out of mach-davinci to drivers/gpio
now that non-davinci architectures are beginning to use this IP.Signed-off-by: Keerthy
Reviewed-by: Tom Rini
[trini: Fix calimain build]
Signed-off-by: Tom Rini -
Add k2g compatible so that k3 SoCs can be supported
Signed-off-by: Keerthy
Reviewed-by: Tom Rini
03 Oct, 2018
1 commit
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Change to use managed resource function devm_kcalloc(),
so it will auto free memory when driver is removed.Signed-off-by: Ley Foon Tan
15 Sep, 2018
3 commits
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This changes the driver to use dev_read_addr() which is safe both for
flat trees and live trees.Signed-off-by: Ley Foon Tan
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Add code to reset all reset signals as in gpio DT node. A reset property
is an optional feature, so only print out a warning and do not fail if a
reset property is not present.If a reset property is discovered, then use it to deassert, thus
bringing the IP out of reset.Signed-off-by: Ley Foon Tan
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Enabled get_function support for dwapb where the function will
return the state of GPIO port.Signed-off-by: Chin Liang See
Signed-off-by: Ley Foon Tan
12 Sep, 2018
4 commits
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Platforms with limited resources in SPL may enable OF_PLATDATA,
this limits some of the library functions and cannot extract data
from the device tree. This patch adds additional wrappers around
these functions to only allow them when OF_CONTROL is enabled and
OF_PLATDATA is not.Signed-off-by: Adam Ford
Reviewed-by: Simon Glass -
The GPIO bank numbers do not appear in the device tree, so this
patch makes the gpio name based on the address
(ie gpio@49054000_31 vs gpio4_31)adam
Signed-off-by: Adam Ford
Tested-by: Derald D. Woods -
With DM and device tree support, let's use the GPIO_ACTIVE_HIGH
and GPIO_ACTIVE_LOW from the device tree as they are intended.Signed-off-by: Adam Ford
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The GPIO banks are broken up into two 16-bit registers for each
bank set. Unfortunately, the math that determines how to shift
blindly shifted by the number of the gpio. This worked for gpio
numbers under 32, but higher gpio's are broken. This fixes the
gpio index, so the bank is passed and the shift amount within
the register is passed now instead of the gpio number.Fixes: 8e51c0f25406("dm: gpio: Add DM compatibility to
GPIO driver for Davinci")Signed-off-by: Adam Ford
11 Sep, 2018
1 commit
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Replace clrsetbits on ODR register (2 operations: one read + one write)
by writing on the correct bit (SET or RESET) of the BSRR register
(only 1 write operation).Moreover this register if safe for simultaneous access by 2 master on
the bus.Signed-off-by: Patrick Delaunay
Signed-off-by: Patrice Chotard
07 Aug, 2018
5 commits
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Add support for reading label property from DT and set up bank name
based on that. If label property is not present full device node name is
used.Signed-off-by: Michal Simek
Reviewed-by: Stefan Herbrechtsmeier -
.set_value functions have no specified return value and gpio_uclass is
not working with it too. But this patch is returning 0 to be in sync
with others DM gpio drivers.Reported-by: Stefan Herbrechtsmeier
Signed-off-by: Michal Simek
Reviewed-by: Stefan Herbrechtsmeier -
Reading registers for finding out output value is not working because
input value is read instead in case of tristate.Reported-by: Stefan Herbrechtsmeier
Signed-off-by: Michal Simek
Reviewed-by: Stefan Herbrechtsmeier -
There is no reason to do read/write for if/else separately.
Reported-by: Stefan Herbrechtsmeier
Signed-off-by: Michal Simek
Reviewed-by: Stefan Herbrechtsmeier -
Set a value before changing gpio direction. This will ensure that the
old value is not propagated when direction has changed but new value is
not written yet.Reported-by: Stefan Herbrechtsmeier
Signed-off-by: Michal Simek
Reviewed-by: Stefan Herbrechtsmeier
