03 Apr, 2019
1 commit
-
The MESON_GXL_USB_PHY is also used on the Amlogic Meson GXM SoCs.
Fixes: 2960e27e38 ("phy: Add Amlogic Meson USB2 & USB3 Generic PHY drivers")
Signed-off-by: Neil Armstrong
19 Jan, 2019
1 commit
-
Now clock and reset drivers are available for respective
SoC's so use clk and reset ops on phy driver.Signed-off-by: Jagan Teki
Acked-by: Maxime Ripard
Reviewed-by: Marek Vasut
15 Dec, 2018
2 commits
-
Signed-off-by: Jean-Jacques Hiblot
Reviewed-by: Tom Rini -
Signed-off-by: Jean-Jacques Hiblot
Reviewed-by: Tom Rini
07 Dec, 2018
2 commits
-
This drivers supports the USB2 PHY found on omap5 and dra7 SOCs.
Signed-off-by: Jean-Jacques Hiblot
-
Add support to handle USB3 PHYs present on AM57xx/DRA7xx SoCs. This is
needed to move AM57xx to DM_USB.Signed-off-by: Vignesh R
Signed-off-by: Jean-Jacques Hiblot
28 Oct, 2018
1 commit
-
Complete in the drivers directory the work started with
commit 83d290c56fab ("SPDX: Convert all of our single
license tags to Linux Kernel style").Reviewed-by: Simon Glass
Signed-off-by: Patrick Delaunay
03 Oct, 2018
1 commit
-
Add a PHY driver for the R-Car Gen3 which allows configuring
USB OTG PHY on Gen3 into host mode and toggles VBUS in case a
dedicated regulator is present.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
01 Oct, 2018
1 commit
-
Add a PHY driver for the Qualcomm dragonboard 410c which
allows switching on/off and resetting the phy connected
to the EHCI controllers and USBHS controller.Signed-off-by: Ramon Fried
19 Sep, 2018
2 commits
-
This patch adds support to Armada 7k/8k comphy RX/TX lane swap. The
'phy-invert' DT property defines the inverted signals.Signed-off-by: Rabeeh Khoury
Signed-off-by: Baruch Siach
Signed-off-by: Stefan Roese -
This adds a weak definition of comphy_update_map to comphy_core,
which does nothing. If this function is defined elsewhere, for example
in board file, the board file can change some parameters of SERDES
configuration.This is needed on Turris Mox, where the SERDES speed on lane 1 has to
be set differently when SFP module is connected and when Topaz Switch
module is connected.This is a temporary solution. When the comphy driver for armada-3720
will be added to the kernel, the comphy driver in u-boot shall also be
updated and this should be done differently then.Signed-off-by: Marek Behun
Signed-off-by: Stefan Roese
14 Aug, 2018
2 commits
-
Add a PHY driver for the R-Car Gen2 which allows configuring the mux
connected to the EHCI controllers and USBHS controller.Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu -
The code fails to copy the last PHY phandle argument, so it is
missing from the adjusted phandle args and the consumer cannot
use it to determine what the PHY should do.Signed-off-by: Marek Vasut
Cc: Patrice Chotard
31 Jul, 2018
3 commits
-
Only H3 and H5 have 4 PHYS so restrict rst_mask only for them
by checking PHY id as 3 and update the proper bits.Signed-off-by: Jagan Teki
Tested-by: Jagan Teki -
usb_clk_cfg is setting CTRL_PHYGATE bit value in probe
which is BIT 0 for sun4i, 6i and 8 for a83t but all
these were handling in phy ops init exit calls.Signed-off-by: Jagan Teki
Tested-by: Jagan Teki -
On newer Allwinner SoC, there is a pair of EHCI/OHCI USB hosts
for OTG host mode. USB PHY passby must be configured for its
corresponding PHY. so we can call for PHY#0. on the other hand
in past usb-phy code the same thing can be restricted for
Lower SoC's, other than H3/H5/A64.Now there is no need to restrict usb passby since the phy driver
is DT enabled, and the respective phy calls will trigger based
DT information initiated by the drivers.Signed-off-by: Jagan Teki
Tested-by: Jagan Teki
20 Jul, 2018
1 commit
-
In case of phy are provided from a PHY provider nodes as following:
usbphyc: usb-phy@5a006000 {
compatible = "st,stm32mp1-usbphyc";
reg = ;
clocks = ;
resets = ;
#address-cells = ;
#size-cells = ;usbphyc_port0: usb-phy@0 {
reg = ;
phy-supply = ;
vdda1v1-supply = ;
vdda1v8-supply =
#phy-cells = ;
};usbphyc_port1: usb-phy@1 {
reg = ;
phy-supply = ;
vdda1v1-supply = ;
vdda1v8-supply =
#phy-cells = ;
};
};and PHY are called as following:
usbh_ehci: usbh-ehci@5800d000 {
compatible = "generic-ehci";
reg = ;
clocks = ;
resets = ;
interrupts = ;
companion = ;
phys = ;
phy-names = "usb";
status = "okay";
};generic_phy_get_by_index() must be updated to first look for
PHY phandle as previously and in case of error looks for PHY
provider by finding the parent's current node which is the PHY
provider.
args (ofnode_phandle_args struct) must also be updated by inserting
the phy index into the PHY provider as args[0].Signed-off-by: Patrice Chotard
04 Jun, 2018
1 commit
01 Jun, 2018
4 commits
-
Also fix bad accents in my name.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Daniel Schwierzeck -
Also fix bad accents in my name.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Daniel Schwierzeck -
Also fix bad accents in my name.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Daniel Schwierzeck -
Also fix bad accents in my name.
Signed-off-by: Álvaro Fernández Rojas
Reviewed-by: Daniel Schwierzeck
28 May, 2018
10 commits
-
The sunxi otg phy has a bug where it wrongly detects a high speed squelch
when reset on the root port gets de-asserted with a lo-speed device.The workaround for this is to disable squelch detect before de-asserting
reset, and re-enabling it after the reset de-assert is done. Add a sunxi
specific phy function to allow the sunxi-musb glue to do this.Signed-off-by: Jagan Teki
Acked-by: Jun Nie -
Allwinner A23 has 2 USB PHY's and 0x04 has phy ctrl offset.
Signed-off-by: Jagan Teki
Acked-by: Jun Nie -
Allwinner A33 has 2 USB PHY's and 0x10 has phy ctrl offset.
Signed-off-by: Jagan Teki
Acked-by: Jun Nie -
Allwinner A31 has 3 USB PHY's and rest similar to A10.
Signed-off-by: Jagan Teki
Acked-by: Jun Nie -
Add PHY configs for Allwinner A10/A13/A20 which are SUN4I.
Signed-off-by: Jagan Teki
Acked-by: Jun Nie -
Unlike, other Allwinner SUN4I Phy supporting SOC, A83T has
2 USB PHY's and second one is HSIC. So phy control need to
configure to handle these HSIC and SIDDQ requirement.Signed-off-by: Jagan Teki
Acked-by: Jun Nie -
V3S has 1 USB PHY, rest are similar to A64.
Signed-off-by: Jagan Teki
Acked-by: Jun Nie -
H3/H5 has 4 USB PHY, rest are similar to A64.
Signed-off-by: Jagan Teki
Acked-by: Jun Nie -
ID and VBUS detection code require when musb changing
between Host and/or Peripheral modes.Signed-off-by: Jagan Teki
Acked-by: Jun Nie -
USB PHY implementation for Allwinner SOC's can be handling
in to single driver with different phy configs.This driver handle all Allwinner USB PHY's start from 4I to
50I(except 9I). Currently added A64 compatibility more will
add in next coming patches.Current implementation is unable to get pinctrl, clock and reset
details from DT since the dm code on these will add it future.Driver named as phy-sun4i-usb.c since the same PHY logic
work for all Allwinner SOC's start from 4I to A64 except 9I
with different phy configurations.Signed-off-by: Jagan Teki
Acked-by: Jun Nie
20 May, 2018
1 commit
-
Signed-off-by: Tom Rini
18 May, 2018
1 commit
-
This patch adds phy tranceiver driver for STM32 USB PHY
Controller (usbphyc) that provides dual port High-Speed
phy for OTG (single port) and EHCI/OHCI host controller
(two ports).
One port of the phy is shared between the two USB controllers
through a UTMI+ switch.Signed-off-by: Christophe Kerello
Signed-off-by: Amelie Delaunay
Signed-off-by: Patrice Chotard
14 May, 2018
6 commits
-
The DTS file for armada-37xx uses the string "marvell,armada3700-ehci",
but the code searched for "marvell,armada-3700-ehci".Signed-off-by: Marek Behun
Signed-off-by: Stefan Roese -
Move the reg_set* functions into comphy.h as static inline functions.
Change return type of get_*_string to const char *.Signed-off-by: Marek Behun
Reviewed-by: Stefan Roese
Signed-off-by: Stefan Roese -
In SGMII initialization PIN_PIPE_SEL has to be zero when resetting
the PHY. Since comphy_mux already set the selector register to
correct values, we have to store it's value before setting it to 0
and restore it after SGMII init.Signed-off-by: Marek Behun
Reviewed-by: Stefan Roese
Signed-off-by: Stefan Roese -
Lane 0 supports SGMII1 and USB3.
Lane 1 supports SGMII0 and PEX0.
Lane 2 supports SATA0 and USB3.This is needed for Armada 37xx.
This introduces new device tree bindings. AFAIK there is currently no
driver for Armada 37xx comphy in Linux. When such a driver will be
pushed into Linux, this will need to be rewritten accordingly.Signed-off-by: Marek Behun
Signed-off-by: Stefan Roese -
The register addresses on lanes 0 and 1 are switched, first comes 1 and
then 0.Signed-off-by: Marek Behun
Signed-off-by: Stefan Roese -
Currently comphy_mux supports only trivial order of nodes in pin
selector register, that is lane N on position N*bitcount.Add support for nontrivial order, with map stored in device tree
property mux-lane-order.This is needed for Armada 37xx.
As far as I know, there is no driver for Armada 37xx comphy in the
kernel. When such a driver comes, this will need to be rewritten to
support the device tree bindings from the kernel.Signed-off-by: Marek Behun
Signed-off-by: Stefan Roese