22 Jan, 2018
2 commits
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During the tuning, drivers repeat data transfer, changing timing
parameters in the controller hardware. So, the tuning commands
(CMD19 for SD, CMD21 for eMMC) fail, and this is not a problem
at all.Showing "Error detected..." in normal operation just make users
upset. This should not be shown.Signed-off-by: Masahiro Yamada
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This line overwrites host_cap that has been set by drivers and/or
helpers like mmc_of_parse(). Accumulate capabilities flags.Signed-off-by: Masahiro Yamada
12 Jan, 2018
2 commits
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data is defined as struct mmc_data *data.
So it should not be compared to 0.Problem identified with Coccinelle.
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Bin Meng -
Fixes emmc initialization regression on the db410c platform.
Clearing this register while SDHCI_PRESENT_STATE reports
SDHCI_CMD_INHIBIT leads to undefined behaviour on the db410c.When commit 7dde50 was merged (mmc: sdhci: Wait for SDHCI_INT_DATA_END
when transferring), SDHCI transfers transitioned to wait for bit
SDHCI_INT_DATA_END before flagging transfers done.Without this patch, the db410 platform fails to initialize its eMMC
due to all of its transfers timing out (SDHCI_INT_DATA_END is never
raised after all the blocks have been transferred).Signed-off-by: Jorge Ramirez-Ortiz
17 Aug, 2017
1 commit
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All boards which use DM_MMC have now been converted to use DM_MMC_OPS.
Drop the option and good riddance.Signed-off-by: Simon Glass
15 May, 2017
1 commit
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In the programmable clock mode, the SDCLK frequency is incorrectly
assigned when the maximum clock has been assigned during probe,
this causes the SDHCI not work well.In the programmable clock mode, when calculating the SDCLK Frequency
Select, when the maximum clock has been assigned, it is the actual
value, should not be multiplied by host->clk_mul. Otherwise, the
maximum clock is multiplied host->clk_mul by the base clock achieved
from the BASECLKF field of the Capabilities 0 Register.Signed-off-by: Wenyou Yang
14 Apr, 2017
1 commit
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sdhci_transfer_data() function transfers the blocks passed up to the
number of blocks defined in mmc_data, but returns immediately once all
the blocks are transferred, even if the loop exit condition is not met
(bit SDHCI_INT_DATA_END set in the STATUS word).When doing multiple writes to mmc, returning right after the last block
is transferred can cause the write to fail when sending the
MMC_CMD_STOP_TRANSMISSION command right after the
MMC_CMD_WRITE_MULTIPLE_BLOCK command, leaving the mmc driver in an
unconsistent state until reboot. This error was observed in the rpi3
board.This patch waits for the SDHCI_INT_DATA_END bit to be set even after
sending all the blocks.Test: Reliably wrote 2GiB of data to mmc in a rpi3.
Signed-off-by: Alex Deymo
Reviewed-by: Simon Glass
21 Mar, 2017
1 commit
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No need to flush cache for command without data.
Signed-off-by: Kevin Liu
25 Jan, 2017
2 commits
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Some SDHCI drivers might need to do some special controller configuration
after the common clock set_ios() function has been called (speed / width
configuration). This patch adds a call to the newly created function
set_ios_port() when its configured in the host driver.This will be used by the Xenon SDHCI controller driver used on the
Marvell Armada 3700 and 7k/8k ARM64 SoCs.Signed-off-by: Stefan Roese
Cc: Jaehoon Chung
Cc: Simon Glass
Reviewed-by: Jaehoon Chung -
This patch completely clears the SDHCI_CLOCK_CONTROL register before the
new value is configured instead of just clearing the 2 bits
SDHCI_CLOCK_CARD_EN and SDHCI_CLOCK_INT_EN. Without this change, some
clock configurations will lead to the "Internal clock never stabilised."
error message on the Xenon SDHCI controller used on the Marvell Armada
3700 and 7k/8k ARM64 SoCs.The Linux SDHCI core driver also writes 0 to this register before
the new value is configured. So this patch simplifies the driver a bit
and brings the U-Boot driver more in-line with the Linux one.Signed-off-by: Stefan Roese
Cc: Jaehoon Chung
Cc: Siva Durga Prasad Paladugu
Cc: Michal Simek
Reviewed-by: Jaehoon Chung
23 Jan, 2017
1 commit
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The sdhci controller assumes that the base clock frequency is fully supported by
the peripheral and doesn't support hardware limitations. The Linux kernel
distinguishes between base clock (max_clk) of the host controller and maximum
frequency (f_max) of the card interface. Use the same differentiation and allow
the platform to constrain the peripheral interface.Signed-off-by: Stefan Herbrechtsmeier
13 Jan, 2017
1 commit
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Until recently, sdhci_ops was used only for overriding IO accessors.
(so, host->ops was not set by any drivers except bcm2835_sdhci.c)Now, we have more optional callbacks, get_cd, set_control_reg, and
set_clock. However, the codeif (host->ops->get_cd)
host->ops->get_cd(host);... expects host->ops is set for all drivers.
Commit 5e96217f0434 ("mmc: pic32_sdhci: move the code to
pic32_sdhci.c") and commit 62226b68631b ("mmc: sdhci: move the
callback function into sdhci_ops") added sdhci_ops for pic32_sdhci.c
and s5p_sdhci.c, but the other drivers still do not (need not) set
host->ops because all callbacks in sdhci_ops are optional.host->ops must be checked to avoid the system crash caused by NULL
pointer access.Signed-off-by: Masahiro Yamada
11 Jan, 2017
8 commits
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It doesn't need to seperate the condition.
Signed-off-by: Jaehoon Chung
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Ther is no usage anywhere. It doesn't need to maintain this bit.
Signed-off-by: Jaehoon Chung
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callback function should be moved into sdhci_ops struct.
Other controller can use these ops for controlling clock or their own
specific register.Signed-off-by: Jaehoon Chung
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To maintain consistency, set_ios type of legacy mmc_ops changed to int.
Signed-off-by: Jaehoon Chung
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This quirk doesn't need anymore.
It's replaced to get_cd callback function.Signed-off-by: Jaehoon Chung
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This code is used for only pic32_sdhci controller.
To remove the "#ifdef", moves to pic32_sdhci.c.
And use the get_cd callback function.Signed-off-by: Jaehoon Chung
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This code is dead code..There is no usage anywhere.
Signed-off-by: Jaehoon Chung
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Buswidth is depeneded on Hardware schematic.
Evne though host can support the 8bit buswidth, if hardware doesn't
support 8bit mode, it doesn't work fine.
So the buswidth mode selection leaves a matter in each SoC drivers.On the contrary to this, hardware supports 8bit mode, but host doesn't
support it. then controller has to disable the MMC_MODE_8BIT.
(Host can check whether 8bit mode is supported or not, since V3.0)Signed-off-by: Jaehoon Chung
30 Dec, 2016
1 commit
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While I moved the options, I also renamed them so that they are all
prefixed with MMC_SDHCI_.This commit was created in the following steps.
[1] Rename with the following command
find . -name .git -prune -o ! -path ./scripts/config_whitelist.txt \
-type f -print | xargs sed -i -e '
s/CONFIG_MMC_SDMA/CONFIG_MMC_SDHCI_SDMA/g
s/CONFIG_BCM2835_SDHCI/CONFIG_MMC_SDHCI_BCM2835/g
s/CONFIG_KONA_SDHCI/CONFIG_MMC_SDHCI_KONA/g
s/CONFIG_MV_SDHCI/CONFIG_MMC_SDHCI_MV/g
s/CONFIG_S5P_SDHCI/CONFIG_MMC_SDHCI_S5P/g
s/CONFIG_SPEAR_SDHCI/CONFIG_MMC_SDHCI_SPEAR/g
'[2] create the Kconfig entries in drivers/mmc/Kconfig
[3] Move the options by the following command
tools/moveconfig.py -y MMC_SDHCI_SDMA MMC_SDHCI_BCM2835 \
MMC_SDHCI_KONA MMC_SDHCI_MV MMC_SDHCI_S5P MMC_SDHCI_SPEAR[4] Sort drivers/mmc/Makefile for readability
Signed-off-by: Masahiro Yamada
Reviewed-by: Tom Rini
Reviewed-by: Jaehoon Chung
28 Oct, 2016
2 commits
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To prevent the wrong value check the SD version.
Signed-off-by: Jaehoon Chung
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This pathc is fixed the below thing.
If misaligned the cache range, Just flush to CACHLINE_SIZE.
"CACHE: Misaligned operation at range [7ae55b00, 7ae55b08]"Signed-off-by: Jaehoon Chung
10 Oct, 2016
2 commits
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Use the generic error number instead of meaningless value.
Signed-off-by: Jaehoon Chung
Reviewed-by: Simon Glass -
"host->version" isn't a SoC specific value.
It doesn't need to get in each SoC drivers.Signed-off-by: Jaehoon Chung
Reviewed-by: Minkyu Kang
20 Sep, 2016
7 commits
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Add the programmable clock mode for the clock generator.
Signed-off-by: Wenyou Yang
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No need for per-SoC adjustment for this parameter. It should be
determined by the slowest hardware. Currently, no board overrides
this CONFIG, so 3.2 sec is large enough. (If not, we can make it
even larger.)Signed-off-by: Masahiro Yamada
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This CONFIG is not configurable since it is not guarded by #ifndef.
Nobody has complained about that, so there is no need to keep it as
a CONFIG option.Signed-off-by: Masahiro Yamada
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If CONFIG_BLK is enabled, add_sdhci() is never called. Move this
quirk handling to sdhci_setup_cfg(), which is now the central place
for hardware capability checks.Signed-off-by: Masahiro Yamada
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If CONFIG_BLK is enabled, add_sdhci() is never called. Move this
quirk handling to sdhci_setup_cfg(), which is now the central place
for hardware capability checks.Signed-off-by: Masahiro Yamada
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"Hardware doesn't specify base clock frequency" may not be only the
error case of sdhci_setup_cfg(). It is better to print this where
the corresponding error is triggered.Signed-off-by: Masahiro Yamada
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If CONFIG_BLK is enabled, add_sdhci() is never called.
So, sdhci_reset() is not called, either. This is a problem for
my board as it needs the reset to start from a sane state.Move the add_sdhci() call to sdhci_init(), which is visited
by both of the with/without CONFIG_BLK cases.Signed-off-by: Masahiro Yamada
05 Aug, 2016
7 commits
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When disabled CONFIG_MMC_SDMA, variable caps didn't use.
This patch fixes the compiler error for -Wunused-but-set-variableSigned-off-by: Jaehoon Chung
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Some arguments don't need to pass to sdhci_setup_cfg.
Generic variable can be used in sdhci_setup_cfg, and some arguments are
already included in sdhci_host struct.It's enough that just pass the board specific things to sdhci_setup_cfg().
After removing the unnecessary arguments, it's more simpler than before.
It doesn't consider "Version" and "Capabilities" anymore in each SoC
driver.Signed-off-by: Jaehoon Chung
Reviewed-by: Simon Glass -
buswidth isn't used anywhere in sdhci_setup_cfg.
Signed-off-by: Jaehoon Chung
Reviewed-by: Minkyu Kang
Reviewed-by: Simon Glass -
This "commit 429790026021d522d51617217d4b86218cca5750" is wrong.
SDHCI_QUIRK_NO_HISPD_BIT is for skipping to set CTRL_HISPD bit.For example, Exynos didn't have CTRL_HISPD. But Highspeed mode
is supported.
(This quirks doesn't mean that driver didn't support the Highseepd mode.)Note: If driver didn't support the Highspeed Mode, use or add the other
quirks.After applied this patch, all Exynos SoCs are just running with 25MHz.
Signed-off-by: Jaehoon Chung
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Use the generic error number instead of specific error number.
If use the generic error number, it can debug more easier.Signed-off-by: Jaehoon Chung
Reviewed-by: Simon Glass
Reviewed-by: Minkyu Kang -
There is no data, it doesn't needs to wait for completing data transfer.
(It seems that it can be removed.)
Almost all timeout error is occured from stop command without data.
After applied this patch, I hope that we don't need to increase timeout value anymore.Signed-off-by: Jaehoon Chung
Acked-by: Lukasz Majewski
Tested-by: Lukasz Majewski
Acked-by: Minkyu Kang -
The current timeout detection logic is not very nice; it calls
get_timer(start) in the while() loop, and then calls it again after
the loop to check if a timeout error happened.Because of the time difference between the two calls of get_timer(),
the timeout detected after the loop may not be true.Signed-off-by: Masahiro Yamada
Acked-by: Jaehoon Chung
Signed-off-by: Jaehoon Chung
22 Jul, 2016
1 commit
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Disable internal clock by clearing the internal
clock enable bit. This bit needs to be cleared too
when we stop the SDCLK for changing the frequency
divisor. This bit should be set to zero when the
device is not using the Host controller.Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
