07 Dec, 2017

1 commit

• 316f0d0f8   powerpc: mpc85xx: Fix static TLB table for SDRAM ... Browse Code »

  2

  Most predefined TLB tables don't have memory coherence bit set for
  SDRAM. This wasn't an issue before invalidate_dcache_range() function
  was enabled. Without the coherence bit, dcache invalidation doesn't
  automatically flush the cache. The coherence bit is already set when
  dynamic TLB table is used. For some boards with different SPL boot
  method, or with legacy fixed setting, this bit needs to be set in
  TLB files.

  Signed-off-by: York Sun

  York Sun

  2017-12-07 06:54:12 +0800  

03 Jan, 2014

1 commit

• fbe76ae4e   board/freescale:Remove use of CONFIG_SPL_NAND_MINIMAL ... Browse Code »

  CONFIG_SPL_NAND_MINIMAL should not be used as it was defined for temporary
  review purpose.

  So, use CONFIG_SPL_NAND_BOOT config.

  Signed-off-by: Prabhakar Kushwaha

  Prabhakar Kushwaha

  2014-01-03 06:10:13 +0800  

24 Jul, 2013

1 commit

• 1a4596601   Add GPL-2.0+ SPDX-License-Identifier to source files ... Browse Code »

  83

  Signed-off-by: Wolfgang Denk
  [trini: Fixup common/cmd_io.c]
  Signed-off-by: Tom Rini

  Wolfgang Denk

  2013-07-24 21:44:38 +0800  

21 Jun, 2013

3 commits

• f64bd7c03   powerpc/mpc85xx:Fix "boot page TLB" entry size for NAND SPL ... Browse Code »

  e500v2 processor does not support 8K page size TLB entries.

  So create new TLB entry only during NAND SPL boot.

  Signed-off-by: Prabhakar Kushwaha
  Signed-off-by: Andy Fleming

  Prabhakar Kushwaha

  2013-06-21 06:08:47 +0800  
• 765b0bdb8   board/bsc9131rdb: Add DSP side tlb and laws ... Browse Code »

  BSC9131RDB is a Freescale Reference Design Board for
  BSC9131 SoC which is a integrated device that contains
  one powerpc e500v2 core and one DSP starcore.

  To support DSP starcore
  -Creating LAW and TLB for DSP-CCSR space.
  -Creating LAW for DSP-core subsystem M2 memory

  Signed-off-by: Priyanka Jain
  Signed-off-by: Poonam Aggrwal
  Signed-off-by: Prabhakar Kushwaha
  Signed-off-by: Andy Fleming

  Priyanka Jain

  2013-06-21 05:09:08 +0800  
• f15932692   board/bsc9131rdb:Add NAND boot support using new SPL format ... Browse Code »

  - Add NAND boot target
  - defines constants
  - Add spl_minimal.c to initialise DDR
  - update TLB entries as per NAND boot

  Signed-off-by: Prabhakar Kushwaha
  Signed-off-by: Andy Fleming

  Prabhakar Kushwaha

  2013-06-21 05:09:07 +0800  

07 Jul, 2012

1 commit

• 7530d341c   powerpc/mpc85xx:Add BSC9131 RDB Support ... Browse Code »

  BSC9131RDB is a Freescale reference design board for BSC9131 SoC. BSC9131 SOC
  is an integrated device that targets Femto base station market. It combines
  Power Architecture e500v2 and DSP StarCore SC3850 core technologies with
  MAPLE-B2F baseband acceleration processing elements

  BSC9131RDB Overview
  -----------------
  -1Gbyte DDR3 (on board DDR)
  -128Mbyte 2K page size NAND Flash
  -256 Kbit M24256 I2C EEPROM
  -128 Mbit SPI Flash memory
  -USB-ULPI
  -eTSEC1: Connected to RGMII PHY
  -eTSEC2: Connected to RGMII PHY
  -DUART interface: supports one UARTs up to 115200 bps for console display
  Apart from the above it also consists various peripherals to support DSP
  functionalities.

  This patch adds support for mainly Power side functionalities and peripherals

  Signed-off-by: Ramneek Mehresh
  Signed-off-by: Priyanka Jain
  Signed-off-by: Akhil Goyal
  Signed-off-by: Rajan Srivastava
  Signed-off-by: Poonam Aggrwal
  Signed-off-by: Prabhakar Kushwaha

  Prabhakar Kushwaha

  2012-07-07 06:30:29 +0800