11 Sep, 2018
40 commits
-
FPGA changes for v2018.11
- add fpga tests to cover fpga commands
- fpga Kconfig cleanup
- fix cmd/fpga.c
- add support for missing fpga loadmk commands
- add fpga fragment to MAINTAINERS -
AM654 has an arasan sdhci controller and a mmc phy attached to it.
Add basic support for K3 specific arasan sdhci controller.Cc: Jaehoon Chung
Reviewed-by: Tom Rini
Signed-off-by: Lokesh Vutla -
Add an option for building remoteproc drivers within SPL.
Reviewed-by: Tom Rini
Signed-off-by: Lokesh Vutla -
Add support for K3 based remoteproc driver that
communicates with TISCI to start start a remote processor.Reviewed-by: Tom Rini
Signed-off-by: Lokesh Vutla -
K3 specific SoCs have a dedicated microcontroller for doing
resource management. Any HLOS/firmware on compute clusters should
load a firmware to this microcontroller before accessing any resource.
Adding support for loading this firmware.After the K3 system controller got loaded with firmware and started
up it sends out a boot notification message through the secure proxy
facility using the TI SCI protocol. Intercept and receive this message
through the rproc start operation which will need to get invoked
explicitly after the firmware got loaded.Signed-off-by: Lokesh Vutla
Signed-off-by: Andreas Dannenberg
Reviewed-by: Tom Rini -
Existing rproc_init() api tries to initialize all available
remoteproc devices. This will fail when there is dependency
among available remoteprocs. So introduce a separate api
that allows to initialize remoteprocs individually based
on id.Reviewed-by: Tom Rini
Signed-off-by: Lokesh Vutla -
Add an option for building mailbox drivers within SPL.
Reviewed-by: Tom Rini
Signed-off-by: Lokesh Vutla -
Secure Proxy module manages hardware threads that are meant
for communication between the processor entities. Adding
support for this driver.Reviewed-by: Tom Rini
Signed-off-by: Lokesh Vutla
Signed-off-by: Andreas Dannenberg -
Devices from the TI K3 family of SoCs like the AM654x contain a Device
Management and Security Controller (SYSFW) that manages the low-level
device control (like clocks, resets etc) for the various hardware
modules present on the SoC. These device control operations are provided
to the host processor OS through a communication protocol called the TI
System Control Interface (TI SCI) protocol.This patch adds a system reset driver that communicates to the system
controller over the TI SCI protocol for allowing to perform a system-
wide SoC reset.Reviewed-by: Tom Rini
Signed-off-by: Andreas Dannenberg
Signed-off-by: Lokesh Vutla -
Some TI Keystone 2 and K3 family of SoCs contain a system controller
(like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and
the Device Management and Security Controller on AM65x SoCs) that manage
the low-level device control (like clocks, resets etc) for the various
hardware modules present on the SoC. These device control operations are
provided to the host processor OS through a communication protocol
called the TI System Control Interface (TI SCI) protocol.This patch adds a power domain driver that communicates to the system
controller over the TI SCI protocol for performing power management of
various devices present on the SoC. Various power domain functionalities
are achieved by the means of different TI SCI device operations provided
by the TI SCI framework.This code is loosely based on the drivers/soc/ti/ti_sci_pm_domains.c
driver of the Linux kernel.Reviewed-by: Tom Rini
Signed-off-by: Andreas Dannenberg
Signed-off-by: Lokesh Vutla -
There are cases where there are more than one power domain
attached to the device inorder to get the device functional.
So add support for enabling power domain based on the index.Reviewed-by: Tom Rini
Signed-off-by: Lokesh Vutla -
Some TI Keystone 2 and K3 family of SoCs contain a system controller
(like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and
the Device Management and Security Controller on AM65x SoCs) that manage
the low-level device control (like clocks, resets etc) for the various
hardware modules present on the SoC. These device control operations are
provided to the host processor OS through a communication protocol
called the TI System Control Interface (TI SCI) protocol.This patch adds a clock driver that communicates to the system
controller over the TI SCI protocol for performing clock management of
various devices present on the SoC. Various clock functionality is
achieved by the means of different TI SCI device operations provided by
the TI SCI framework.This code is loosely based on the drivers/clk/keystone/sci-clk.c driver
of the Linux kernel.Reviewed-by: Tom Rini
Signed-off-by: Andreas Dannenberg
Signed-off-by: Vignesh R
Signed-off-by: Lokesh Vutla -
Some TI Keystone 2 and K3 family of SoCs contain a system controller
(like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and
the Device Management and Security Controller on AM65x SoCs) that manage
the low-level device control (like clocks, resets etc) for the various
hardware modules present on the SoC. These device control operations are
provided to the host processor OS through a communication protocol
called the TI System Control Interface (TI SCI) protocol.This patch adds a reset driver that communicates to the system
controller over the TI SCI protocol for performing reset management of
various devices present on the SoC. Various reset functionalities are
achieved by the means of different TI SCI device operations provided by
the TI SCI framework.This code is loosely based on the drivers/reset/reset-ti-sci.c driver of
the Linux kernel.Reviewed-by: Tom Rini
Signed-off-by: Andreas Dannenberg
Signed-off-by: Lokesh Vutla -
Add a reset operations function pointer to support querying the current
status of a reset control.Reviewed-by: Tom Rini
Signed-off-by: Andreas Dannenberg
Signed-off-by: Lokesh Vutla -
To support scenarios where a firmware device node has subnodes that
have their own drivers automatically scan the DT and bind those when
the firmware device gets bound.Reviewed-by: Tom Rini
Signed-off-by: Andreas Dannenberg
Signed-off-by: Lokesh Vutla -
TI-SCI message protocol provides support for controlling of various
physical cores available in SoC. In order to control which host is
capable of controlling a physical processor core, there is a processor
access control list that needs to be populated as part of the board
configuration data.Introduce support for the set of TI-SCI message protocol apis that
provide us with this capability of controlling physical cores.Reviewed-by: Tom Rini
Signed-off-by: Lokesh Vutla -
Since system controller now has control over SoC power management, it
needs to be explicitly requested to reboot the SoC. Add support for
it.Reviewed-by: Tom Rini
Signed-off-by: Andreas Dannenberg
Signed-off-by: Lokesh Vutla
Signed-off-by: Nishanth Menon -
In general, we expect to function at a device level of abstraction,
however, for proper operation of hardware blocks, many clocks directly
supplying the hardware block needs to be queried or configured.Introduce support for the set of SCI message protocol support that
provide us with this capability.Reviewed-by: Tom Rini
Signed-off-by: Lokesh Vutla
Signed-off-by: Nishanth Menon -
TI-SCI message protocol provides support for management of various
hardware entitites within the SoC. Introduce the fundamental
device management capability support to the driver protocol
as part of this change.Reviewed-by: Tom Rini
Signed-off-by: Lokesh Vutla
Signed-off-by: Nishanth Menon -
TI-SCI message protocol provides support for board configuration
to assign resources and other board related operations.
Introduce the board configuration capability support to the driver protocol
as part of this change.Reviewed-by: Tom Rini
Signed-off-by: Andreas Dannenberg
Signed-off-by: Lokesh Vutla -
Texas Instrument's System Control Interface (TI SCI) message protocol is
used in Texas Instrument's System on Chip (SoC) such as those in the K3
family AM654 SoC to communicate between various compute processors with
a central system controller entity.The TI SCI message protocol provides support for management of various
hardware entities within the SoC. Add support driver to allow
communication with system controller entity within the SoC using the
mailbox client.This is mostly derived from the TI SCI driver in Linux located at
drivers/firmware/ti_sci.c.Reviewed-by: Tom Rini
Signed-off-by: Lokesh Vutla
Signed-off-by: Nishanth Menon
Signed-off-by: Andreas Dannenberg -
Add support for Texas Instruments' K3 Generation Processor
families.Signed-off-by: Lokesh Vutla
Reviewed-by: Tom Rini -
Sync with the driver code and the binding recently merged in Linux.
Signed-off-by: Masahiro Yamada
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Trivial Kconfig cleanup. Use tabs instead of spaces.
Signed-off-by: Michal Simek
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Add driver model support for OMAP_SERIAL while reusing
the functions in ns16550.cSigned-off-by: Lokesh Vutla
Reviewed-by: Tom Rini
Tested-by: Derald D. Woods -
DCC is supported on Cortex R series as well. Enable DCC support
for V7R.Signed-off-by: Lokesh Vutla
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Following build warning appears when pinctrl-single is built for ARM64:
In file included from drivers/pinctrl/pinctrl-single.c:10:0:
drivers/pinctrl/pinctrl-single.c: In function ‘single_configure_pins’:
./arch/arm/include/asm/io.h:43:28: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
#define __arch_getw(a) (*(volatile unsigned short *)(a))Fix this by using phys_addr_t for variable reg instead of u32
Signed-off-by: Lokesh Vutla
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timer_pre_probe() tries to populate the clock rate from DT. omap
timer driver tries to overwrite this value irrespective of the value
populated fro DT. So update this value only when DT doesn't populate
the clock rate.Signed-off-by: Lokesh Vutla
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In order to handle counter overflows use 64 bit values for counter.
Also load the initial value during probe.Signed-off-by: Lokesh Vutla
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The strobe dll code is ported from Linux Kernel:
drivers/mmc/host/sdhci-esdhc-imx.c
The comments are from the above file,
"For HS400 eMMC, there is a data_strobe line. This signal is generated
by the device and used for data output and CRC status response output
in HS400 mode. The frequency of this signal follows the frequency of
CLK generated by host. The host receives the data which is aligned to the
edge of data_strobe line. Due to the time delay between CLK line and
data_strobe line, if the delay time is larger than one clock cycle,
then CLK and data_strobe line will be misaligned, read error shows up.
So when the CLK is higher than 100MHz, each clock cycle is short enough,
host should configure the delay target. "Signed-off-by: Peng Fan
Cc: Jaehoon Chung
Cc: Stefano Babic -
Add HS400 support.
Selecting HS400 needs first select HS200 according to spec, so use
a dedicated function for HS400.
Add HS400 related macros.
Remove the restriction of only using the low 6 bits of
EXT_CSD_CARD_TYPE, using all the 8 bits.Signed-off-by: Peng Fan
Cc: Jaehoon Chung
Cc: Jean-Jacques Hiblot
Cc: Stefano Babic
Cc: Kishon Vijay Abraham I
Cc: Faiz Abbas
Cc: Marek Vasut
Signed-off-by: Peng Fan -
Replace clrsetbits on ODR register (2 operations: one read + one write)
by writing on the correct bit (SET or RESET) of the BSRR register
(only 1 write operation).Moreover this register if safe for simultaneous access by 2 master on
the bus.Signed-off-by: Patrick Delaunay
Signed-off-by: Patrice Chotard -
This patch adds support for :
- Rate calculation through muxes and generic dividers
- Basic gate setting propagation
- Reparenting for muxes
- Clock rate setting through generic dividers without reparentingSupport is only added to the Composite VPU and VAPB clocks in order
to support the Video Processing Unit Power Domain clock setup.Reviewed-by: Simon Glass
Signed-off-by: Neil Armstrong -
The Amlogic Meson SoCs embeds a specific Power Domain dedicated to the
Video Processing Unit.
This patch implements support for this power domain in preparation of the
future support for the Video display support in U-Boot.This driver will depend on changes in the clock driver to handle the setup
of the VPU and VAPB clocks configured from DT using assigned-clocks entries.Reviewed-by: Simon Glass
Signed-off-by: Neil Armstrong -
In int-ll64.h, we always use the following typedefs:
typedef unsigned int u32;
typedef unsigned long uintptr_t;
typedef unsigned long long u64;This does not need to match to the compiler's .
Do not include it.The use of PRI* makes the code super-ugly. You can simply use
"l" for printing uintptr_t, "ll" for u64, and no modifier for u32.Signed-off-by: Masahiro Yamada
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Signed-off-by: Patrice Chotard
Reviewed-by: Simon Glass -
Replace stm32_serial_setparity by stm32_serial_setconfig
which allows to set serial bits number, parity and stop
bits number.
Only parity setting is implemented.Signed-off-by: Patrick Delaunay
Signed-off-by: Patrice Chotard
Reviewed-by: Simon Glass -
Replace setparity by more generic setconfig ops
to allow uart parity, bits word length and stop bits
number change.Adds SERIAL_GET_PARITY/BITS/STOP macros.
Signed-off-by: Patrick Delaunay
Signed-off-by: Patrice Chotard
Reviewed-by: Simon Glass -
Add test to avoid access to rx buffer when this buffer is empty.
In this case directly call getc() function to avoid issue when tstc()
is not called.Signed-off-by: Patrick Delaunay
Reviewed-by: Simon Glass
