22 Nov, 2013
10 commits
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This patch adds new CONFIG_NAND_OMAP_ECCSCHEME, replacing other distributed
CONFIG_xx used for selecting NAND ecc-schemes.
This patch aims at solving following issues.1) Currently ecc-scheme is tied to SoC platform, which prevents user to select
other ecc-schemes also supported in hardware. like;
- most of OMAP3 SoC platforms use only 1-bit Hamming ecc-scheme, inspite
the fact that they can use higher ecc-schemes like 8-bit ecc-schemes with
software based error detection (OMAP_ECC_BCH4_CODE_HW_DETECTION_SW).
- most of AM33xx SoC plaforms use 8-bit BCH ecc-scheme for now, but hardware
supports BCH16 ecc-scheme also.2) Different platforms use different CONFIG_xx to select ecc-schemes, which
adds confusion for user while migrating platforms.
- *CONFIG_NAND_OMAP_ELM* which enables ELM hardware engine, selects only
8-bit BCH ecc-scheme with h/w based error-correction (OMAP_ECC_BCH8_CODE_HW)
whereas ELM hardware engine supports other ecc-schemes also like; BCH4,
and BCH16 (in future).
- *CONFIG_NAND_OMAP_BCH8* selects 8-bit BCH ecc-scheme with s/w based error
correction (OMAP_ECC_BCH8_CODE_HW_DETECTION_SW).
- *CONFIG_SPL_NAND_SOFTECC* selects 1-bit Hamming ecc-scheme using s/w libraryThus adding new *CONFIG_NAND_OMAP_ECCSCHEME* de-couples ecc-scheme dependency
on SoC platform and NAND driver. And user can select ecc-scheme independently
foreach board.
However, selection some hardware based ecc-schemes (OMAP_ECC_BCHx_CODE_HW) still
depends on presence of ELM hardware engine on SoC. (Refer doc/README.nand)Signed-off-by: Pekon Gupta
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BCH8_ECC scheme implemented in omap_gpmc.c driver has following favours
+-----------------------------------+-----------------+-----------------+
|ECC Scheme | ECC Calculation | Error Detection |
+-----------------------------------+-----------------+-----------------+
|OMAP_ECC_BCH8_CODE_HW |GPMC |ELM H/W engine |
|OMAP_ECC_BCH8_CODE_HW_DETECTION_SW |GPMC |S/W BCH library |
+-----------------------------------+-----------------+-----------------+Current implementation limits the BCH8_CODE_HW only for AM33xx device family.
(using CONFIG_AM33XX). However, other SoC families (like TI81xx) also have
ELM hardware module, and can support ECC error detection using ELM.This patch
- removes CONFIG_AM33xx
Thus this driver can be reused by all devices having ELM h/w engine.
- adds omap_select_ecc_scheme()
A common function to handle ecc-scheme related configurations. This
can be used both during device-probe and via user-space u-boot commads
to change ecc-scheme. During device probe ecc-scheme is selected based
on CONFIG_NAND_OMAP_ELM or CONFIG_NAND_OMAP_BCH8
- enables CONFIG_BCH
S/W library (lib/bch.c) required by OMAP_ECC_BCHx_CODE_HW_DETECTION_SW
is enabled by CONFIG_BCH.
- enables CONFIG_SYS_NAND_ONFI_DETECTION
for auto-detection of ONFI compliant NAND devices
- updates following README doc
doc/README.nand
board/ti/am335x/README
doc/README.omap3Signed-off-by: Pekon Gupta
[scottwood@freescale.com: fixed unused variable warning]
Signed-off-by: Scott Wood -
ELM hardware engine which is used for ECC error detection, is present on all
latest OMAP SoC (like OMAP4xxx, OMAP5xxx, DRA7xxx, AM33xx, AM43xx). Thus ELM
driver should be moved to common drivers/mtd/nand/ folder so that all SoC
having on-chip ELM hardware engine can re-use it.
This patch has following changes:
- mv arch/arm/include/asm/arch-am33xx/elm.h arch/arm/include/asm/omap_elm.h
- mv arch/arm/cpu/armv7/am33xx/elm.c drivers/mtd/nand/omap_elm.c
- update Makefiles
- update #include
- add CONFIG_NAND_OMAP_ELM to compile driver/mtd/nand/omap_elm.c
and include in all board configs using AM33xx SoC platform.Signed-off-by: Pekon Gupta
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Signed-off-by: Josh Wu
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Since for some MLC nand, bit errors happened too often. Just disable it
to avoid noiseSigned-off-by: Josh Wu
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Signed-off-by: Josh Wu
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increase the delay to 75us to support the 8k bytes page nand flash
Signed-off-by: Josh Wu
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Defines constants required to support 8K page size NAND flash.
Signed-off-by: Prabhakar Kushwaha
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Current IFC driver supports till 4K page size NAND flash.
Add support of 8K NAND flash
- Program Spare region size in csor_ext
- Add nand_ecclayout for 4 bit & 8 bit ecc
- Defines constants
- Add support of 8K NAND boot.Signed-off-by: Prabhakar Kushwaha
CC: Liu Po -
nand_ecclayout is present in mtd.h at Linux.
Move this structure to mtd.h to comply with Linux.Also, increase the ecc placement locations to 640 to suport device having
writesize/oobsize of 8KB/640B. This means that the maximum oobsize has gone
up to 640 bytes and consequently the maximum ecc placement locations have
also gone up to 640.Changes from Prabhabkar's version (squashed into one patch to preserve
bisectability):
- Added _LARGE to MTD_MAX_*_ENTRIESThis makes the names match current Linux source, and resolves
a conflict between
http://patchwork.ozlabs.org/patch/280488/
and
http://patchwork.ozlabs.org/patch/284513/The former was posted first and is closer to matching Linux, but
unlike Linux it does not add _LARGE to the names. The second adds
_LARGE to one of the names, and depends on it in a subsequent patch
(http://patchwork.ozlabs.org/patch/284512/).- Made max oobfree/eccpos configurable, and used this on tricorder,
alpr, ASH405, T4160QDS, and T4240QDS (these boards failed to build
for me without doing so, due to a size increase).On tricorder SPL, this saves 2576 bytes (and makes the SPL build
again) versus the new default of 640 eccpos and 32 oobfree, and
saves 336 bytes versus the old default of 128 eccpos and 8 oobfree.Signed-off-by: Prabhakar Kushwaha
CC: Vipin Kumar
[scottwood@freescale.com: changes as described above]
Signed-off-by: Scott Wood
Cc: Thomas Weber
Cc: Matthias Fuchs
Cc: Stefan Roese
Cc: York Sun
Cc: Tom Rini
Reviewed-by: Stefan Roese
14 Nov, 2013
2 commits
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as per controller description,
"While programming a NAND flash, status read should never skipped.
Because it may happen that a new command is issued to the NAND Flash,
even when the device has not yet finished processing the previous request.
This may result in unpredictable behaviour."IFC controller never polls for R/B signal after command send. It just return
control to software. This behaviour may not occur with NAND flash access.
because new commands are sent after polling R/B signal. But it may happen
in scenario where GPCM-ASIC and NAND flash device are working simultaneously.Update the controller driver to take care of this requirement
Signed-off-by: Prabhakar Kushwaha
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Add possible to use software BCH ECC for atmel nand driver
Signed-off-by: Bo Shen
12 Nov, 2013
10 commits
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Use scf0403 driver to add scf0403x LCD support for cm-t35 and cm-t3730
boards.Signed-off-by: Nikita Kiryanov
Acked-by: Igor Grinberg -
Add DSS_ONOFF to polarity defines
Cc: Tom Rini
Cc: Anatolij Gustschin
Cc: Igor Grinberg
Signed-off-by: Nikita Kiryanov
Acked-by: Igor Grinberg
Acked-by: Anatolij Gustschin -
Add SPI-based driver for DataImage SCF0403852GGU04 and SCF0403526GGU20
LCD panels.Cc: Tom Rini
Cc: Anatolij Gustschin
Cc: Igor Grinberg
Signed-off-by: Nikita Kiryanov
Acked-by: Anatolij Gustschin
Signed-off-by: Anatolij Gustschin -
The flag combination "SPI_XFER_BEGIN | SPI_XFER_END" is a common use
case of spi_xfer, and it can easily cause an already long line (spi_xfer
takes 5 parameters) to go over the 80 character limit.define SPI_XFER_ONCE to be a shorter version of the above flag combination.
Cc: Tom Rini
Cc: Jagannadha Sutradharudu Teki
Cc: Igor Grinberg
Signed-off-by: Nikita Kiryanov -
Current implementation only supports 8 bit word lengths, even though
omap3 can handle anything between 4 and 32.Update the spi interface to support changing the SPI word length,
and implement it in omap3_spi driver to support the full range of
possible word lengths.
This implementation is backwards compatible by defaulting to the old
behavior of 8 bit word lengths.
Also, it required a change to the omap3_spi non static I/O functions,
but since they are not used anywhere else, no collateral changes are required.Cc: Tom Rini
Cc: Jagannadha Sutradharudu Teki
Cc: Igor Grinberg
Signed-off-by: Nikita Kiryanov -
Remove unnecessary semicolon from #define SPI_WAIT_TIMEOUT
Cc: Tom Rini
Cc: Jagannadha Sutradharudu Teki
Cc: Igor Grinberg
Cc: Gerhard Sittig
Signed-off-by: Nikita Kiryanov -
Depending on the firmware's video options [1] the active SDTV or
HDTV mode can yield a framebuffer with noncontiguous horizontal lines,
giving a messed up display, for both, u-boot and the loaded kernel.Fix this by setting lcd_line_length to the pitch value of the configured
framebuffer.[1] http://elinux.org/RPiconfig#Video_mode_options
Signed-off-by: Andre Heider
Cc: Stephen Warren
Signed-off-by: Anatolij Gustschin
Acked-by: Stephen Warren -
Remove the redundant lcd_line_length initialisation which
sneaked in when an earlier version of the patch of commit
6d330719 has been rebased.Some lcd drivers need to setup lcd_line_length not from the
panel_info parameters but by different means. Make the
lcd_get_size() weak to allow setting lcd_line_length in
a driver specific way.Signed-off-by: Anatolij Gustschin
Cc: Stephen Warren -
Add the missing "right" field to struct bcm2835_mbox_tag_overscan.
Signed-off-by: Andre Heider
Acked-by: Stephen Warren
Acked-by: Albert ARIBAUD -
The MPC824x processors have long reached EOL, and the PN62 board has
not seen any board-specific updates for more than a decade. It is now
causing build issues. Instead of wasting time on things nobody is
interested in any more, we rather drop this board.Signed-off-by: Wolfgang Denk
Cc: Wolfgang Grandegger
cc: Tom Rini
11 Nov, 2013
3 commits
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Commit 8dfafdde88eb3e71d5569846396ae67a91017232 introduced
new gcc warnings on MIPS64:time.c: In function 'tick_to_time':
time.c:59:2: warning: comparison of distinct pointer types lacks a cast [enabled by default]
time.c:59:2: warning: passing argument 1 of '__div64_32' from incompatible pointer type [enabled by default]
In file included from time.c:10:0:
./u-boot-mips/include/div64.h:22:17: note: expected 'uint64_t *' but argument is of type 'long long unsigned int *'
time.c: In function 'usec_to_tick':
time.c:76:2: warning: comparison of distinct pointer types lacks a cast [enabled by default]
time.c:76:2: warning: passing argument 1 of '__div64_32' from incompatible pointer type [enabled by default]
In file included from time.c:10:0:
./u-boot-mips/include/div64.h:22:17: note: expected 'uint64_t *' but argument is of type 'long long unsigned int *'Signed-off-by: Daniel Schwierzeck
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This patch replaces the GPL-2.0 text with a GPL-2.0
SPDX-License-Identifier tag, and adds Imagination Technologies copyright
following my recent changes.Signed-off-by: Paul Burton
10 Nov, 2013
15 commits
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Conflicts:
arch/arm/cpu/arm926ejs/mxs/Makefile
board/compulab/cm_t35/Makefile
board/corscience/tricorder/Makefile
board/ppcag/bg0900/Makefile
drivers/bootcount/Makefile
include/configs/omap4_common.h
include/configs/pdnb3.hMakefile conflicts are due to additions/removals of
object files on the ARM branch vs KBuild introduction
on the main branch. Resolution consists in adjusting
the list of object files in the main branch version.
This also applies to two files which are not listed
as conflicting but had to be modified:board/compulab/common/Makefile
board/udoo/Makefileinclude/configs/omap4_common.h conflicts are due to
the OMAP4 conversion to ti_armv7_common.h on the ARM
side, and CONFIG_SYS_HZ removal on the main side.
Resolution is to convert as this icludes removal of
CONFIG_SYS_HZ.include/configs/pdnb3.h is due to a removal on ARM side.
Trivial resolution is to remove the file.Note: 'git show' will also list two files just because
they are new:include/configs/am335x_igep0033.h
include/configs/omap3_igep00x0.h -
The memsize environment variable must contain the
memory size in bytes on the Malta board. Otherwise
Linux will use wrong memory size which causes a kernel
panic.Define CONFIG_MEMSIZE_IN_BYTES in malta.h to avoid
that.Signed-off-by: Gabor Juhos
Cc: Daniel Schwierzeck
Cc: Paul Burton -
This patch adds me as a maintainer of the malta(el) board(s). I have
access to physical Malta boards and the desire for U-boot to run well on
them.Signed-off-by: Paul Burton
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This patch adds a script which may be used with MIPS Navigator Console
and a MIPS Nagivator Probe in order to flash U-boot to a MIPS Malta
development board.Please see the newly added doc/README.malta for usage instructions.
Signed-off-by: Paul Burton
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Without setting up the PIRQ[A:D] interrupt routes, PCI interrupts will
be left disabled. Linux does not set up this routing but relies upon it
having been set up by the bootloader, reading back the IRQ lines which
the PIRQ[A:D] signals have been routed to.This patch routes PIRQA & PIRQB to IRQ 10, and PIRQC & PIRQD to IRQ 11.
This matches the setup used by YAMON.Signed-off-by: Paul Burton
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Allow the environment to be stored in the monitor flash of a Malta
board. The environment is stored in the final 128KB of the flash, which
both leaves the majority of the flash available for U-boot code and also
matches the location which YAMON uses.Signed-off-by: Paul Burton
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This is actually required in order for a Linux kernel to boot
successfully on a physical Malta board. Without enabling the RTC, a
Malta Linux kernel will get stuck in its estimate_frequencies function
on boot.Signed-off-by: Paul Burton
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Malta boards may be used with cores which support L2 caches, however
U-boot does not yet support L2 cache for MIPS. Thus for the moment we'll
disable L2 caches by setting the L2B bit in Config2. This is specific to
MTI/Imagination MIPS cores which is why this is done for the Malta board
rather than generically.Signed-off-by: Paul Burton
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These will now be detected at runtime, allowing a single U-boot
configuration to function correctly with different bitstreams. Without
this you may need to re-configure, re-build and re-flash U-boot to your
Malta if you flash a new bitstream with a different cache configuration
to your old bitstream.Signed-off-by: Paul Burton
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This model of the pcnet is used in current Malta boards, at least in the
Malta-R rev 3. Enable support for it.The Malta also has the ethernet controller PROM containing its MAC
address, so enable support for that in order to read that MAC address.DHCP is a very useful feature to have available for many networks,
enable support for it also.Signed-off-by: Paul Burton
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Displaying a message on the LCD screen is a simple yet effective way to
show the user that the board has booted successfully.Signed-off-by: Paul Burton
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This patch adds support for running on Malta boards using coreFPGA6
core cards, including support for the msc01 system controller used
with them. The system controller is detected at runtime allowing one
U-boot binary to run on a Malta with either.Due to the PCI I/O base differing between Maltas using gt64120 & msc01
system controllers, the UART setup is modified slightly. A second UART
is added so that there is one pointing at the correct address for each
system controller. The Malta board then defines its own
default_serial_console function to select the correct one at runtime.
The incorrect UART will simply not function.Tested on:
- A coreFPGA6 Malta running interAptiv and proAptiv bitstreams, both
with and without an L2 cache.
- QEMU.Signed-off-by: Paul Burton
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On a real Malta the Super I/O needs to be configured before we are able
to access the UARTs. This patch performs that configuration, setting up
the UARTs in the same way that YAMON would.Signed-off-by: Paul Burton
-
This is in preparation for adapting this board to function correctly on
a physical MIPS Malta board. The board is moved into an "imgtec" vendor
directory at the same time in order to ready us for any other boards
supported by Imagination in the future.Signed-off-by: Paul Burton
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This patch simply #ifdef's out the C-specific parts of pci.h when it is
included by an assembly file. This will allow the macros it contains to
be used from assembly source as will be done in a followup commit adding
support for more modern MIPS Malta boards.Signed-off-by: Paul Burton
