31 Mar, 2020
2 commits
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Add save_boot_params() to save reset status value from bootrom.
Bootrom will clear the status register in reset manager and stores the
reset status value in shared memory. Bootrom stores shared data at last
2KB of onchip RAM.This function save reset status provided by bootrom to rst_mgr_status.
More information about reset status register value can be found in reset
manager register description.When running in debugger without bootrom, r0 to r3 are random values.
So, skip save the value when r0 is not bootrom shared data address.Signed-off-by: Ley Foon Tan
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Add OCRAM size macro for Gen5 and Arria 10.
Signed-off-by: Ley Foon Tan
04 Mar, 2020
1 commit
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Add initial support for the ABB SECU board, which is an ArriaV-based
SoCFPGA system with ethernet and booting from Denali NAND.Signed-off-by: Holger Brunck
Cc: Ley Foon Tan
Cc: Simon Goldschmidt
11 Feb, 2020
1 commit
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sandbox conversion to SDL2
TPM TEE driver
Various minor sandbox video enhancements
New driver model core utility functions
06 Feb, 2020
1 commit
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At present dm/device.h includes the linux-compatible features. This
requires including linux/compat.h which in turn includes a lot of headers.
One of these is malloc.h which we thus end up including in every file in
U-Boot. Apart from the inefficiency of this, it is problematic for sandbox
which needs to use the system malloc() in some files.Move the compatibility features into a separate header file.
Signed-off-by: Simon Glass
05 Feb, 2020
1 commit
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Add DDR2 support to Gen5 DRAM driver. As the DDR2 macro names generated
by Quartus are named differently than the DDR3 ones, use anon unions to
store them in the same structures, without growing their size.Signed-off-by: Marek Vasut
Cc: Ley Foon Tan
Cc: Simon Goldschmidt
03 Feb, 2020
1 commit
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This particular chunk of code was not updated, likely due to the order
in which the patches were posted and applied. Fix this missing part.Fixes: bb25aca13433 ("arm: socfpga: Convert reset manager from struct to defines")
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dalon Westergreen
Cc: Dinh Nguyen
Cc: Ley Foon Tan
Cc: Simon Goldschmidt
Cc: Tien Fong Chee
18 Jan, 2020
2 commits
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At present panic() is in the vsprintf.h header file. That does not seem
like an obvious choice for hang(), even though it relates to panic(). So
let's put hang() in its own header.Signed-off-by: Simon Glass
[trini: Migrate a few more files]
Signed-off-by: Tom Rini -
Move this function out of common.h and into a relevant header file.
Signed-off-by: Simon Glass
07 Jan, 2020
17 commits
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Enable TCU access through the Stratix10 CCU so that the
SMMU can access the SDRAM.Signed-off-by: Thor Thayer
Reviewed-by: Ley Foon Tan -
Add build support for Agilex SoC.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt -
Add SPL support for Agilex SoC.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt -
Add clock handoff offset for Agilex. Remove S10 prefix to avoid confusion.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt -
Add clock wrapper functions call to clock DM functions to get clock
frequency and used in cm_print_clock_quick_summary().Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt -
Add clock manager driver for Agilex. Provides clock initialization
and get_rate functions.agilex-clock.h is from Linux commit ID cd2e1ad12247.
Signed-off-by: Chee Hong Ang
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt -
CLKMGR_INTOSC_HZ should be 400MHz, instead of 460MHz.
Removed also unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ.Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt -
Move Stratix10 and Agilex clock manager common code to new header file.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt -
Add system manager support for Agilex.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt -
Move Stratix10 and Agilex system manager common code to
system_manager_soc64.h. Changed macros to use SYSMGR_SOC64_*.Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt -
Add reset manager support for Agilex.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt -
Move Stratix10 and Agilex reset manager common code to
reset_manager_soc64.h. Changed macros to RSTMGR_SOC64_*.Remove unused RSTMGR_XXX defines.
Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt -
Move firewall related code to new firewall.c, to share
code in Stratix 10 and Agilex.SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC
to allow DMA transfer to OCRAM.Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt -
Add base address for Intel Agilex SoC.
Reuse base_addr_s10.h for Agilex, only one base address is
different from S10.Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt -
Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.Change to get clock manager base address from DT node instead of using
#define.Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt -
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.Change to get system manager base address from DT node instead of
using #define.Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt -
Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.Change to get reset manager base address from DT node instead of using
#define.spl_early_init() initializes the DT setup. So, move spl_early_init() to
beginning of function and before get base address from DT.Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
03 Dec, 2019
2 commits
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These functions belong in cpu_func.h. Another option would be cache.h
but that code uses driver model and we have not moved these cache
functions to use driver model. Since they are CPU-related it seems
reasonable to put them here.Move them over.
Signed-off-by: Simon Glass
Reviewed-by: Tom Rini -
This function belongs in time.h so move it over and add a comment.
Signed-off-by: Simon Glass
Reviewed-by: Tom Rini
25 Nov, 2019
4 commits
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In case the SPL on Gen5 loads U-Boot from NAND, unreset the NAND IP
explicitly in the platform code as the denali-spl driver is not aware
of DM at all.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dalon Westergreen
Cc: Dinh Nguyen
Cc: Ley Foon Tan
Cc: Simon Goldschmidt
Cc: Tien Fong Chee
Reviewed-by: Ley Foon Tan -
Add new FPGA ID for ArriaV ST/D3 or SX/B3 .
Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dalon Westergreen
Cc: Dinh Nguyen
Cc: Ley Foon Tan
Cc: Simon Goldschmidt
Cc: Tien Fong Chee
Reviewed-by: Ley Foon Tan -
On Gen5, when the FPGA is loaded and there was some prior interaction
between the HPS and the FPGA via bridges (e.g. Linux was running and
using some of the IPs in the FPGA) followed by warm reset, it has been
observed that there might be outstanding unfinished transactions. This
leads to an obscure misbehavior of the bridge.When the bridge is enabled again in U-Boot and there are outstanding
transactions, a read from within the bridge address range would return
a result of the previous read instead. Example:
=> bridge enable ; md 0xff200000 1
ff200000: 1234abcd
=> bridge enable ; md 0xff200010 1
ff200010: 5678dcba bridge enable ; md 0xff200000 1
ff200000: 90effe09
Cc: Chin Liang See
Cc: Dalon Westergreen
Cc: Dinh Nguyen
Cc: Ley Foon Tan
Cc: Simon Goldschmidt
Cc: Tien Fong Chee
Reviewed-by: Ley Foon Tan -
On Gen5, the 'bridge disable' command write 0x0 to brgmodrst register,
which releases all bridges from reset, instead of putting all bridges
into reset. Fix this by inverting the mask and actually putting the
bridges into reset.Signed-off-by: Marek Vasut
Cc: Chin Liang See
Cc: Dalon Westergreen
Cc: Dinh Nguyen
Cc: Ley Foon Tan
Cc: Simon Goldschmidt
Cc: Tien Fong Chee
Reviewed-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt
21 Nov, 2019
1 commit
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The file arch/arm/mach-socfpga/include/mach/misc.h used the same include
guard as the global include/misc.h.Fix this by giving the arch file an arch prefix.
Signed-off-by: Simon Goldschmidt
Reviewed-by: Ley Foon Tan
08 Nov, 2019
1 commit
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The default implementation of ERR_PTR/PTR_ERR maps errno values at the
and of the address range (e.g. -EINVAL/-22 gets 0xFFFFFFEA).For socfpga gen5 SPL, this doesn't really work, as the heap is nearly
at the end of the 32 bit address range.This patch adjusts the ERR_PTR_OFFSET to map errno values into the range
of the Boot ROM, which should not be used for valid pointers.Signed-off-by: Simon Goldschmidt
10 Oct, 2019
1 commit
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The company Samtec was merged into Softing, migrate the board over to
the new name and update copyright headers.Signed-off-by: Marek Vasut
Cc: Silvio Fricke
Cc: Simon Goldschmidt
08 Oct, 2019
2 commits
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This is currently a decimal value which is not as convenient or
meaningful. Also U-Boot tends to use hex everywhere.Convert this option to hex and add a comment for the size_check macro.
Signed-off-by: Simon Glass
Reviewed-by: Simon Goldschmidt
Acked-by: Bin Meng
[bmeng: correct the typo in the commit title]
Signed-off-by: Bin Meng -
At present there is only one control for this and it is used for both SPL
and TPL. But SPL might have a lot more space than TPL so the extra cost of
a full printf() might be acceptable.Split the option into two, providing separate SPL and TPL controls. The
TPL setting defaults to the same as SPL.Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
15 Aug, 2019
1 commit
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The socfpga gen5 SPL manually zeroed bss in board_init_f(). Now that the
DDR driver does not use bss any more, bss is not used before board_init_r()
and we can remove this hack.bss is normally zeroed by crt0.S, but after board_init_f(), before
board_init_r(). socfpga just had this double-zeroing because it invalidly
used bss in board_init_f() already (during DDR initialization).Signed-off-by: Simon Goldschmidt
12 Aug, 2019
1 commit
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Move env_set() over to the new header file.
Acked-by: Joe Hershberger
Signed-off-by: Simon Glass
21 Jul, 2019
1 commit
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This moves sysreset support for socfgpa from ad-hoc code in mach-socfpga
to a UCLASS_SYSRESET based dm driver.A side effect is that gen5 and a10 can now select between cold and warm
reset.Signed-off-by: Simon Goldschmidt