11 Aug, 2017
3 commits
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The 'tests' target will run sandbox, sandbox_spl and sandbox_flattree in
test.py and in the case of sandbox_spl ensure that we just run the
specific tests for that build. Update our matrix to perform similar
test.py runs.Signed-off-by: Tom Rini
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Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini
10 Aug, 2017
28 commits
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Allow sending restart conditions upon direction change as this is
required by some chips.Signed-off-by: Marek Vasut
Cc: Stefan Roese
Cc: Alexey Brodkin
Cc: Heiko Schocher
Reviewed-by: Heiko Schocher -
This converts the following to Kconfig:
CONFIG_SYS_I2C_OMAP24XXSigned-off-by: Adam Ford
Reviewed-by: Heiko Schocher -
Set BM poll size once during priv probe and do not
overwrite it during port probe procedure. Pool is common for
all CP ports.Signed-off-by: Stefan Chulski
Tested-by: iSoC Platform CI
Reviewed-by: Nadav Haklai
Reviewed-by: Igal Liberman
Acked-by: Joe Hershberger
Signed-off-by: Stefan Roese -
TX drain in transmit procedure could cause issues due
to race between drain procedure and transmition of descriptor
between AGGR TXQ and physical TXQ.
TXQ will be cleared before moving to Linux by stop procedure.Signed-off-by: Stefan Chulski
Tested-by: iSoC Platform CI
Reviewed-by: Nadav Haklai
Reviewed-by: Igal Liberman
Acked-by: Joe Hershberger
Signed-off-by: Stefan Roese -
MVPP22 driver support 64 Bit arch and require BM pool
high address configuration.Signed-off-by: Stefan Chulski
Tested-by: iSoC Platform CI
Reviewed-by: Nadav Haklai
Reviewed-by: Igal Liberman
Acked-by: Joe Hershberger
Signed-off-by: Stefan Roese -
Remove IRQ configuration from U-Boot PP driver.
U-Boot don't use interrupts and configuration of IRQ in U-Boot
caused crashes in Linux shared interrupt mode.
Also interrupt use is redundant in RX routine since a single RX
queue is used.Signed-off-by: Stefan Chulski
Tested-by: iSoC Platform CI
Reviewed-by: Nadav Haklai
Reviewed-by: Igal Liberman
Acked-by: Joe Hershberger
Signed-off-by: Stefan Roese -
MBUS driver were replaced by AXI in PPv22 and relevant
only for PPv21.Signed-off-by: Stefan Chulski
Tested-by: iSoC Platform CI
Reviewed-by: Nadav Haklai
Reviewed-by: Igal Liberman
Acked-by: Joe Hershberger
Signed-off-by: Stefan Roese -
U-boot use single physical tx queue with size 16 descriptors.
So aggregated tx queue size should be equal to physical tx queue
and cpu descriptor chunk(number of descriptors delivered from
physical tx queue to aggregated tx queue by one chunk) shouldn't be
larger than physical tx queue.Fix:
Set AGGR_TXQ and CPU_DESC_CHUNK to be 16 descriptors, same as
physical TXQ.Signed-off-by: Stefan Chulski
Tested-by: iSoC Platform CI
Reviewed-by: Nadav Haklai
Reviewed-by: Igal Liberman
Acked-by: Joe Hershberger
Signed-off-by: Stefan Roese -
Issue:
BM counters were overrun by probe that called per Network interface and
caused release of wrong number of buffers during remove procedure.Fix:
Use probe_done and num_ports to call init and remove procedure
once per communication controller.Signed-off-by: Stefan Chulski
Tested-by: iSoC Platform CI
Reviewed-by: Igal Liberman
Acked-by: Joe Hershberger
Signed-off-by: Stefan Roese -
This patch enables padding of packets shorter than 64B in TX(set by default).
Disabling of padding causes crashes on MACCIATO board.Signed-off-by: Stefan Chulski
Tested-by: iSoC Platform CI
Reviewed-by: Igal Liberman
Acked-by: Joe Hershberger
Signed-off-by: Stefan Roese -
A8K marvell SoC has two South Bridge communication controllers(CP0 and CP1).
Each communication controller has packet processor ports and MDIO.
On MACHIATOBin board ports from CP1 are connected to mdio on CP0.Issue:
Wrong base address is assigned to MDIO interface during probe.Fix:
Get MDIO address from PHY handler parent base address.This should be refined in the future when MDIO driver is implemented.
Signed-off-by: Stefan Chulski
Tested-by: iSoC Platform CI
Reviewed-by: Igal Liberman
Acked-by: Joe Hershberger
Signed-off-by: Stefan Roese -
This patch add GPIO configuration support in mvpp2x driver.
Driver will handle 10G SFP gpio reset and SFP TX disable. GPIO pins should
be set in device tree.Signed-off-by: Stefan Chulski
Tested-by: iSoC Platform CI
Reviewed-by: Kostya Porotchkin
Reviewed-by: Igal Liberman
Acked-by: Joe Hershberger
Signed-off-by: Stefan Roese -
Increase env sector size from 64kb to 256kb for qspi boot.
Signed-off-by: Santan Kumar
Signed-off-by: Priyanka Jain
Reviewed-by: York Sun -
The implementation of function set_pcie_ns_access() uses a wrong
argument. The structure array ns_dev has a member 'ind' which is
initialized by CSU_CSLX_*. It should use the 'ind' directly to
address the PCIe's CSL register (CSL_base + CSU_CSLX_PCIE*).Signed-off-by: Hou Zhiqiang
[YS: Revise commit message]
Reviewed-by: York Sun -
In fsl_mc_ldpaa_exit(), in case of mc is booted and dpl is applied,
it should return earlier without executing dpbp_exit().Signed-off-by: Santan Kumar
Acked-by: Priyanka Jain
Acked-by: Yogesh Narayan Gaur
Reviewed-by: York Sun -
IFC and QSPI are muxed on board. Add fsl_fdt_fixup_flash() to disable
IFC node in dts if QSPI is enabled, or disable QSPI node in dts if
otherwise.Signed-off-by: Santan Kumar
Signed-off-by: Priyanka Jain
[YS: Revise commit message]
Reviewed-by: York Sun -
Signed-off-by: Rajat Srivastava
Signed-off-by: Rajesh Bhagat
Signed-off-by: yinbo.zhu
[YS: Revise subject, remove commit message]
Reviewed-by: York Sun -
We shouldn't always change the status to okay. There could be
situations that the esdhc is intentionally disabled in the device
tree.Signed-off-by: Li Yang
Reviewed-by: York Sun -
This bug is brought by the commit 3d8553f0a3 (pci: layerscape: add
LS2088A series SoC pcie support), which only updated cfg_res.start
and did not update the .end field. This causes fdt_resource_size()
getting wrong value when calculate the cfg1 space address.Signed-off-by: Hou Zhiqiang
[YS: Revise subject and commit message]
Reviewed-by: York Sun -
This patch enables driver model for USB in defconfigs for LS1021A
platforms.Signed-off-by: Alison Wang
Reviewed-by: Bin Meng
Reviewed-by: York Sun -
Function enable_layerscape_ns_access() is alreayd called soc-wide.
Remove duplicated calling from individual boards.Signed-off-by: Hou Zhiqiang
[YS: Add commit message]
Reviewed-by: York Sun -
It is derived from Platform clock instead of Platform PLL frequency.
Signed-off-by: Hou Zhiqiang
Reviewed-by: York Sun -
Function config_board_mux() reads env variable 'hwconfig' which is
only available after relocation for QSPI boot. Move calling
config_board_mux() to misc_init_r().Signed-off-by: Santan Kumar
[YS: Revise commit message]
Reviewed-by: York Sun -
Smart voltage translator is removed from LS2080ARDB/LS2088ARDB
RevF boards. It is only used on LS2081ARDB. Programming GPIO
is only required for LS2081ARDB.Signed-off-by: Santan Kumar
Signed-off-by: Priyanka Jain
[YS: Revise commit message]
Reviewed-by: York Sun -
Update the default core frequency to 1800MHZ for best performance under
SD boot and eMMC boot.Signed-off-by: Gong Qianyu
Reviewed-by: York Sun -
Commit 4483b7eb added variable vqmmc_dev but only uses it under
CONFIG_DM_REGULATOR. Add the same macro to variable declaration to
get rid of compiling warning.Signed-off-by: York Sun
09 Aug, 2017
6 commits
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The driver is for all boards 24XX and up, so let's eliminate the
extra option called CONFIG_SYS_I2C_OMAP34XX since the driver checks
for CONFIG_OMAP34XX we don't need CONFIG_SYS_I2C_OMAP34XX.Signed-off-by: Adam Ford
Reviewed-by: Heiko Schocher -
Add missing probe function to the device driver to active a device.
Signed-off-by: Wenyou Yang
Reviewed-by: Heiko Schocher -
Reviewed-by: Joe Hershberger
Signed-off-by: Tom Rini
08 Aug, 2017
3 commits
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This defconfig uses the PCIe x4 binary blobs from the congatec BIOS.
Signed-off-by: Stefan Roese
Cc: Simon Glass
Cc: Bin Meng
Reviewed-by: Bin Meng -
- Disable debug UART
- Enable more partition supportSigned-off-by: Stefan Roese
Cc: Simon Glass
Cc: Bin Meng
Reviewed-by: Bin Meng -
- Enable ACPI resume support
- Disable debug UART
- Enable Spansion and Winbond SPI flash support
- Move VGA BIOS binary address to enable bigger U-Boot imagesSigned-off-by: Stefan Roese
Cc: Simon Glass
Cc: Bin Meng
Reviewed-by: Bin Meng
