05 Sep, 2019
1 commit
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Add flexspi_nand driver which works on iMX flexspi controller to support
SPI NAND flash. This driver requires DM_SPI and follows SPI-MEM interfaces
to adapt to the SPI NAND framework.Note: Current implementation limits to the 12-bit column address. This is
popular in main stream SPI NAND and flash devices supported in u-boot.
If device with larger page size (> 4096) needs to support, we have to change
the driver.Signed-off-by: Ye Li
14 Aug, 2019
2 commits
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Add the driver data for each compatible string of different SOC. So we
can remove the SOC config and use driver data instead.Signed-off-by: Ye Li
Reviewed-by: Peng Fan -
On iMX7ULP A0, PCC divider for QSPI has timing issue and it is
only possible to use the divider ratio equal to 1 (PCD=0).
This timing issue causes page program working abnormal if DDR_EN
is set. So current QSPI driver has disabled DDR mode on iMX7ULPSince iMX7ULP B0 has fixed the issue, so re-enable the DDR mode
for iMX7ULP.Signed-off-by: Ye Li
30 Jul, 2019
1 commit
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Set MCR0 RXCLKSRC to 1 to enable DQS loopback from pad to support
higher frequency.Signed-off-by: Ye Li
(cherry picked from commit 256fcd3df1b0a0b9c0fb730fabb7497800cda3a6)
28 May, 2019
3 commits
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The page write sequence in spi-mem is changed with orignal spi-flash. When
the max_write_size is set by driver, the orignal sequence is
1. WREN
2. write max_write_size data to flash
3. wait for WIP clean
4. back to #1 if having data remained in a page.The new sequence is:
1. WREN
2. write (max_write_size - command length) data to flash
3. back to #2 if having data remained in a page
4. wait for WIP cleanSince mx7ulp has 64 bytes TX buffer (max_write_size), while other iMX chips
have 512 bytes (page size is 256). So when adapt qspi with the new sequence,
we have to check the WIP before each write on mx7ulp. Otherwise the WIP may set
due to previous write is not completed by flash device, then cause current
write failed.Signed-off-by: Ye Li
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When slave drivers not set the max_read_size, the spi-mem should directly
use data.nbytes and not limit to any size. But current logic will limit to
the max_write_size.Signed-off-by: Ye Li
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The original codes uses 100ms timeout, but the new is_controller_busy only
try 5 times with each only 1us delay.
When the qspi clock is slower, the controller may need longer time in busy.
On mx7ulp, we meet problem that timeout always happen. So change the codes
to 100ms timeoutSigned-off-by: Ye Li
24 May, 2019
18 commits
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CS GPIO output level is inverse and cause SPI not working. Fix
the issue by setting current CS levelSigned-off-by: Ye Li
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Add the fuse checking in drivers, when the module is disabled in fuse,
the driver will not work.Changed drivers: BEE, GPMI, APBH-DMA, ESDHC, FEC, QSPI, ECSPI, I2C,
USB-EHCI, GIS, LCDIF and EPDC.Signed-off-by: Ye Li
(cherry picked from commit 1704e116f9b39aeb99201919a18bc2b1e19a980e)
(cherry picked from commit 2d3b5df8530cd5ef883750378838dea7c40259af)
(cherry picked from commit 6e8c9ae136bee8ec0121c1db4b935510caad09db) -
support to read the flag status in driver to avoid the spi-nor framework
wait_for_ready hang issue.Signed-off-by: Han Xu
(cherry picked from commit 767faa948d2d140b6d56ee505f81f8f57c045a3d)
(cherry picked from commit 55e83ccb588c3e953f55148161bc524b5dab7a25) -
There are two problems in enabling DDR mode in this new driver:
1. The TDH bits in FLSHCR register should be set to 1. Otherwise, the TX DDR delay logic
won't be enabled. Since u-boot driver does not have DDR commands in LUT. So this won't
cause explicit problem.
2. When doing read/write/readid/erase operations, the MCR register is overwritten, the bits
like DDR_EN are cleared during these operations. When we using DDR mode QSPI boot, the TDH bit
is set to 1 by ROM. if the DDR_EN is cleared, there is no clk2x output for TX data shift.
So these operations will fail.
The explicit problem is users may get "SF: unrecognized JEDEC id bytes: ff, ff, ff" error
after using DDR mode QSPI boot on 6UL/ULL EVK boards.Signed-off-by: Ye Li
(cherry picked from commit 16270556212e6c7422e87f69572c90f1afe6998b)
(cherry picked from commit 1c84e2e3ceeb0c7dce3d5a8b139e7ef6d56725bf) -
The mx7ulp has small TX/RX FIFO (64Bytes) and AHB buffer size (128Bytes)
than other i.MX. Change some parameters for it.Also found when the DDR_EN bit is set, sometime the page programming will fail
during large data programming. The 64 bytes data is not programmed into flash.
But when DDR_EN is clear, there is no such issue. Suspect this is a IC issue.
We have disable the DDR_EN for mx7ulp.Signed-off-by: Ye Li
(cherry picked from commit 5a69ddb7e9886e082da42ddf673415702975ee60) -
Should use CONFIG_IS_ENABLED not IS_ENABLED for CLK driver, so it will
check the CONFIG_SPL_CLK when building SPLSigned-off-by: Ye Li
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In flexspi driver, each sf command will disable the module in release bus
function. So reading from flexspi memory-map address using "md" command
can't work. When iMX8MM kicks M4 image to run flexspi NOR XIP,
this causes problem.Signed-off-by: Ye Li
(cherry picked from commit e92d831e5b1e149b23aeb1774c57d076ac246b1e) -
iMX8MM DTS uses new compatible string "fsl,imx8mm-flexspi" in flexspi
node. Add it into the flexspi driver.Signed-off-by: Ye Li
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The address size is 3 bytes when using BAR mode, but the driver
supposes the 4bytes mode is enabled and uses 4 bytes address. This
cause address issue.Signed-off-by: Ye Li
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If not initialize unused LUT to 0, the value is random which might
cause qspi command failure.On i.MX8QM/QXP, it works ok because ROM inittialize them to 0, but on
i.MX8MM, ROM not initialize them, so let's do it here.Signed-off-by: Peng Fan
(cherry picked from commit c4bd49c7b249073415f052fb28cd5a4ad374a318)
(cherry picked from commit bce752cfe43b3378dbd84b64d46f1d1818e0300f) -
After switched to spi-mem the data format passed by xfer is changed for
erase. The address of erase is moved to data phase in SPI_XFER_END.
Update the driver to fix the erase issueSigned-off-by: Ye Li
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The i.MX8M reuses the QSPI controller from i.MX7D. Add the CONFIG_IMX8M
define to the driver.Signed-off-by: Ye Li
(cherry picked from commit c0d5846b027a51e8d3d12700a63dec5ce8f3cb9a) -
Since iMX8 has implemented the clk uclass driver, so we can parse the
clock from DTB and enable it in driver. Add support to this new interfaceSigned-off-by: Ye Li
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After switch to spi-mem, the din buffer format is changed
1. For erase command, the address is in data phase.
2. For 4 bytes address device, even we do not enable 4 bytes support,
it still pass down 4 bytes address.Signed-off-by: Ye Li
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When the power domain driver is enabled, we need to enable clocks after power
domain on. The clock settings in board level codes must be removed, needs to
set them when the device is probed. Add this weak function in flexspi driver,
that SoC codes can implement the clock settings.Reviewed-by: Peng Fan
Signed-off-by: Ye Li
(cherry picked from commit a4d334e70839021a50dca2ad4ad98ecee16081f9)
(cherry picked from commit 821d6b7b06cba244ac872a7b3af9ee269f464008) -
i.MX8QM ROM didn't calculate the DLL correctly in some cases, to avoid
the wrong DLL setting impact the following functions, reset them to the
default value when probe.Signed-off-by: Han Xu
(cherry picked from commit da3c2a9f09afa45a428809b7bf3f981a1ccb7f2e)
(cherry picked from commit 71368855b63c16998ca5681984e70a913e1f4d84) -
Update the LUT settings, spi_xfer to use the 4bytes address read/write/erase
commands.
Also add a function to enter the 4bytes mode for flash device.Signed-off-by: Ye Li
(cherry picked from commit 704c1c357d5566e6b3a72c57427d90ba08f9ef0f)
(cherry picked from commit 24c5cdaa45fda19b885783054820f309c05bab16) -
Add fsl_fspi driver for flexspi controller. This driver supports:
1. DDR Quad output
2. Prefetch function for improve read performance.
3. Fast read and Quad read for one line read mode.
4. Read flash FSR register.
5. DM.Signed-off-by: Han Xu
Signed-off-by: Ye Li
(cherry picked from commit ae4e80b7b0debd2ad868781aaeb28ca4f2d9a8aa)
(cherry picked from commit dcd5504f6493d9aed415f397f1c13611fc202605)
04 Mar, 2019
9 commits
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Now the same SPI controller driver is reusable in all Allwinner
SoC variants, so rename the existing sun4i_spi.c into spi-sunxi.c
which eventually look like a common sunxi driver.Also update the function, variable, structure names in driver from
sun4i into sunxi.Signed-off-by: Jagan Teki
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- drop unused macros.
- use base instead of base_addr, for better code readability
- move .probe and .ofdata_to_platdata functions in required
places to add platdata support in future.
- use sentinel sun4i_spi_ids.Signed-off-by: Jagan Teki
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The usual SPI transmission protocol in Allwinner A10 and A31
controllers share similar context with minimal changes in register
offsets along with few additional register bits on A31.So, add A31 spi controller support in existing sun4i_spi with A31
specific register offsets and bits.Signed-off-by: Jagan Teki
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Add CLK support to enable AHB and MOD SPI clocks on sun4i_spi driver.
Clock disablement could be done while releasing the bus transfer, but
the existing code doesn't disable the clocks it only taken care of clock
enablement globally in probe.So to make a proper clock handling, the clocks should enable it in claim
and disable it in release.This patch would also do that change, by enable and disable clock in
proper order.Signed-off-by: Jagan Teki
Reviewed-by: Andre Przywara -
Support fifo_depth via drvdata instead of macro definition, this would
eventually reduce another macro definition for new SPI controller fifo
depth support addition.Signed-off-by: Jagan Teki
Reviewed-by: Andre Przywara -
Allwinner support two different SPI controllers one for A10 and
another for A31 with minimal changes in register offsets and
respective register bits, but the logic for accessing the SPI
master via SPI slave remains nearly similar.Add enum offsets for register set and register bits, so-that
it can access both classes of SPI controllers.Assign same control register for global, transfer and fifo control
registers to make the same code compatible with A31 SPI controller.Signed-off-by: Jagan Teki
Tested-by: Stefan Mavrodiev # A20-SOM204 -
Update the existing register writes using setbits_le32 and
clrbits_le32 in required places.Signed-off-by: Jagan Teki
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To drain rx fifo the fifo need to poll for how much data has
been filled up in rx fifo.To achieve this, the current code is using wait_for_bit logic
on control register with exchange burst mode mask, which is not
a proper way of waiting for fifo filled up.So, add code for polling rxfifo to be filled up using fifo
status register.Signed-off-by: Jagan Teki
Reviewed-by: Andre Przywara -
With current order of include files, the file designware_spi.c
can't see that the struct global_data has the member
board_type when CONFIG_BOARD_TYPES is defined. By not seeing this
then all the members are shifted in the struct global_data.
So when the driver is trying to read from device tree blob, it
would pass the wrong address to the function 'fdtdev_get_int'.
This will make to use the default frequency 500000.The fix consists of changing the order of include files in
designware_spi.c to include first common.h file.Signed-off-by: Horatiu Vultur
Reviewed-by: Jagan Teki
01 Mar, 2019
1 commit
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_omap3_spi_set_wordlen() indexed the regs->channel[] array with the
old wordlen (instead of the chipselect number) when reading the current
CHCONF register value. This meant it read from the wrong memory location,
modified that value, and then wrote it back to the correct CHCONF
register. The end result is that most slave configuration settings would
be lost, such as clock divisor, clock/chipselect polarities, etc.Fixes: 77b8d04854f4 ("spi: omap3: Convert to driver model")
Signed-off-by: David Rivshin
14 Feb, 2019
1 commit
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Trivial patch.
Signed-off-by: Michal Simek
07 Feb, 2019
4 commits
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Now that new SPI NOR layer uses stateless 4 byte opcodes by default,
don't enable SPI_FLASH_BAR. For SPI controllers that cannot support
4-byte addressing, (stm32_qspi.c, fsl_qspi.c, mtk_qspi.c, ich.c,
renesas_rpc_spi.c) add an imply clause to enable SPI_FLASH_BAR so as to
not break functionality.Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki #zynq-microzed -
Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD
layer. Fix up sf_dataflash to work in legacy way. And update sandbox to
use new interfaces/definitionsSigned-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki #zynq-microzed -
Add non DM version of SPI_MEM to support easy migration to new SPI NOR
framework. This can be removed once DM_SPI conversion is complete.Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki #zynq-microzed -
It is necessary to call spi_claim_bus() before starting any SPI
transactions and this restriction would also apply when calling spi-mem
operations. Therefore claim and release bus before requesting transfer
via exec_op.Signed-off-by: Vignesh R
Tested-by: Simon Goldschmidt
Tested-by: Stefan Roese
Tested-by: Horatiu Vultur
Reviewed-by: Jagan Teki
Tested-by: Jagan Teki #zynq-microzed
