08 Jan, 2014
2 commits
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The omap3_zoom2 board has not been updated for a correct CONFIG_SYS_HZ
and Tom Rix's email has long been bouncing.Signed-off-by: Tom Rini
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With the changes to make OOBFREE/ECCPOS configurable but default to
larger, we need to set these config options for the space savings they
provide.Cc: Scott Wood
Cc: Heiko Schocher
Signed-off-by: Tom Rini
06 Jan, 2014
2 commits
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Conflicts:
include/micrel.hThe conflict above was trivial, caused by four lines being
added in both branches with different whitepace.
03 Jan, 2014
15 commits
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Enable fuse supply before fuse programming and disable after.
Signed-off-by: Sergey Alyoshin
Reviewed-by: Benoît Thébaudeau -
The enable_fec_anatop_clock method should be available for all MX6
variant as it is not MX6 SoloLite specific. This moves the code out of
the #ifdef/#endif and we make it conditional to CONFIG_FEC_MXC
instead.Signed-off-by: Otavio Salvador
Acked-by: Stefano Babic -
This patch fixes allow for the DeviceTree and initrd relocation fixing
the boot of FSL 3.10.9-1.0.0-alpha kernel.This changes following boards:
- mx6sabreauto
- mx6sabresd
- wandboard
- udoo
- nitrogen6x
- cgtqmx6evalThe reasoning, as explained by Hui Liu, is:
,----
| The FDT blob will be placed at DDR physical addr: 0x11000000. When Linux kernel
| Boot up, it will decompress the compressed kernel image and place the decompressed
| kernel image at the low end of the DDR memory and start running from it. If the
| decompressed kernel image is bigger for example than 16M, it may over written the
| fdt blob which u-boot loaded to the DDR memory @0x11000000 with fdt_addr=0x11000000
|
| To expand the fdt_addr from 0x11000000 to 0x18000000, which can avoid the override
| Since we will not likely have one kernel image larger than 128MB.
`----Signed-off-by: Otavio Salvador
Acked-by: Stefano Babic -
This adds following new targets:
- update_nand_kernel
- update_nand_fdt
- update_nand_filesystemand to avoid confusion, the 'update_nand_full' has been renamed to
'update_nand_firmware_full'.Signed-off-by: Otavio Salvador
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This reads the kernel, ftd and boot into ubifs filesystem. While on
that, the SD firmware filename definition has been moved next to the
other SD related commands.Signed-off-by: Otavio Salvador
Reviewed-by: Fabio Estevam -
Using 512k for fdt partition allow it to be aligned with the other
small partitions and 512k erase block size.Signed-off-by: Otavio Salvador
Acked-by: Stefano Babic -
The macro allows easy setting in per-pin, as for example:
,----
| imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_MODE_SION);
`----The IOMUX_CONFIG_SION allows for reading PAD value from PSR register.
The following quote from the datasheet:
,----
| ...
| 28.4.2.2 GPIO Write Mode
| The programming sequence for driving output signals should be as follows:
| 1. Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need
| to read loopback pad value through PSR
| 2. Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b).
| 3. Write value to data register (GPIO_DR).
| ...
`----This fixes the gpio_get_value to properly work when a GPIO is set for
output and has no conflicts.Thanks for Benoît Thébaudeau , Fabio
Estevam and Eric Bénard
for helping to properly trace this down.Signed-off-by: Otavio Salvador
Acked-by: Stefano Babic -
As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator
in order to save power.Signed-off-by: Anson Huang
Signed-off-by: Jason Liu
Signed-off-by: Fabio Estevam -
When changing LDO voltages we need to wait for the required amount of time
for the voltage to settle.Also, as the timer is still not available when arch_cpu_init() is called, we
need to call it later at board_postclk_init() phase.Signed-off-by: Fabio Estevam
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Introduce set_ldo_voltage() so that all three LDO regulators can be configured.
Signed-off-by: Fabio Estevam
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mx6 datasheet specifies that the minimum VDDSOC at 792 MHz is 1.15 V.
Add a 25 mV margin and set it to 1.175V.This also matches the VDDSOC voltages for 792MHz operation that the kernel configures:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/cpu_op-mx6.c?h=imx_3.0.35_4.1.0Signed-off-by: Fabio Estevam
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Since ROM may modify the LDO ramp up time according to fuse setting,
it is safer to reset the ramp up field to its default value of 00:00: 64 cycles of 24MHz clock;
01: 128 cycles of 24MHz clock;
02: 256 cycles of 24MHz clock;
03: 512 cycles of 24MHz clock;Signed-off-by: Anson Huang
Signed-off-by: Jason Liu
Signed-off-by: Fabio Estevam -
set_vddsoc() is not used anywhere else, so make it static.
Signed-off-by: Fabio Estevam
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Add CONFIG_CMD_FUSE option, so that the fuse API can be used.
Signed-off-by: Fabio Estevam
Reviewed-by: Benoît Thébaudeau -
When using the fuse API in U-boot user must calculate the 'bank' and 'word'
values.Provide a real example on how to calculate such values for the mx6q.
Signed-off-by: Fabio Estevam
Reviewed-by: Benoît Thébaudeau
31 Dec, 2013
2 commits
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This patch add uuid disk to defualt partions necessary to
restore gpt partitions and fixes mmcdev environmental variable.Signed-off-by: Piotr Wilczek
Signed-off-by: Kyungmin Park
Signed-off-by: Minkyu Kang -
This fix is necessary after increased by one the number
of adapters in s3c24x0 driver.Tested on Trats and Trats2.
Signed-off-by: Piotr Wilczek
Signed-off-by: Kyungmin Park
Cc: Minkyu Kang
Cc: Lukasz Majewski
Signed-off-by: Minkyu Kang
30 Dec, 2013
11 commits
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When variable size SPL is used, the BL1 expects the SPL to be
encapsulated differently: instead of putting the checksum at a fixed
offset in the SPL blob, prepend the blob with a header including the
size and the checksum.The enhancements include
- adding a command line option, '--vs' to indicate the need for the
variable size encapsulation
- padding the fixed size encapsulated blob with 0xff instead of random
memory contents
- do not silently truncate the input file, report error instead
- no need to explicitly closing files/freeing memory, this all happens
on exit; removing cleanups it makes code clearer
- profuse commenting
- modify Makefile to allow enabling the new feature per boardSigned-off-by: Vadim Bendebury
Signed-off-by: Rajeshwari S Shinde
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang -
Adding initial config for SMDK5420 to build and boot U-Boot
over Exynos based SMDK5420.Signed-off-by: Rajeshwari S Shinde
Signed-off-by: Akshay Saraswat
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang -
This patch adds dts support for SMDK5420.
exynos5.dtsi created is a common file which has the nodes common
to both 5420 and 5250.Signed-off-by: Akshay Saraswat
Signed-off-by: Rajeshwari S Shinde
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang -
Adding the base patch for Exynos based SMDK5420.
This shall enable compilation and basic boot support for
SMDK5420.Signed-off-by: Rajeshwari S Shinde
Signed-off-by: Akshay Saraswat
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang -
Adds code in pinmux and gpio framework to support Exynos5420.
Signed-off-by: Naveen Krishna Chatradhi
Signed-off-by: Akshay Saraswat
Signed-off-by: Rajeshwari S Shinde
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang -
This patch intends to add DDR3 initialization code for Exynos5420.
Signed-off-by: Akshay Saraswat
Signed-off-by: Rajeshwari S Shinde
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang -
This patch adds code for clock initialization and clock settings
of various IP's and controllers, required for Exynos5420Signed-off-by: Rajeshwari S Shinde
Signed-off-by: Akshay Saraswat
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang -
Add dmc and phy_control register structure for 5420.
Signed-off-by: Rajeshwari S Shinde
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang -
Add structure for power register for Exynos5420
Signed-off-by: Rajeshwari S Shinde
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang -
Adds base addresses of various IPs and controllers required for
Exynos5420.Signed-off-by: Rajeshwari S Shinde
Signed-off-by: Akshay Saraswat
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang -
Create a common board.c file for all functions which are common across
all EXYNOS5 platforms.exynos_init function is provided for platform specific code.
Signed-off-by: Rajeshwari S Shinde
Acked-by: Simon Glass
Signed-off-by: Minkyu Kang
19 Dec, 2013
8 commits
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Commit 164d98466103a46b7c881149e92ec2a28a6375be breaks
board with SATA support, because sata is not compiled.Signed-off-by: Stefano Babic
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Adding Maintainer for AM43xx.
Signed-off-by: Lokesh Vutla
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GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG registerSigned-off-by: Lokesh Vutla
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AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
Adding LPDDR2 init sequence and register details for the same.
Below is the brief description of LPDDR2 init sequence:
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
-> Wait till initialization is complete and the configure MR registers.Signed-off-by: Lokesh Vutla
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Currently same value is programmed for all ioregs. This is not
the case for all SoC's like AM4372. So adding a structure for ioregs
and updating in all board files. And also return from config_cmd_ctrl()
and config_ddr_data() functions if data is not passed.Signed-off-by: Lokesh Vutla
[trini: Fixup dxr2, cm_t335, adapt pcm051 rev3]
Signed-off-by: Tom Rini -
Updating the Multiplier and Dividers value for all DPLLs.
Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value
returned the MPU DPLL is locked.
At different OPPs follwoing are the MPU locked frequencies.
OPP50 300MHz
OPP100 600MHz
OPP120 720MHz
OPPTB 800MHz
OPPNT 1000MHz
According to the latest DM following is the OPP table dependencies:
VDD_CORE VDD_MPU
OPP50 OPP50
OPP50 OPP100
OPP100 OPP50
OPP100 OPP100
OPP100 OPP120
So at different OPPs of MPU it is safest to lock CORE at OPP_NOM.
Following are the DPLL locking frequencies at OPP NOM:
Core locks at 1000MHz
Per locks at 960MHz
LPDDR2 locks at 266MHz
DDR3 locks at 400MHzTouching AM33xx files also to get DPLL values specific to board but no
functionality difference.
Signed-off-by: Lokesh Vutla -
Updating the mux data for UART, adding data for i2c0 and mmc.
And also updating pad_signals structure.Signed-off-by: Lokesh Vutla
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Current Booting devices list is different from that of AM33xx.
Updating the same.Signed-off-by: Lokesh Vutla
