19 Feb, 2018
1 commit
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Only ARM and in some configs MIPS really implement arch_fixup_fdt().
Others just use the same boilerplate which is not good by itself,
but what's worse if we try to build with disabled CONFIG_CMD_BOOTM
and enabled CONFIG_OF_LIBFDT we'll hit an unknown symbol which was
apparently implemented in arch/xxx/lib/bootm.c.Now with weak arch_fixup_fdt() right in image-fdt.c where it is
used we get both items highlighted above fixed.Signed-off-by: Alexey Brodkin
Cc: Daniel Schwierzeck
Cc: Simon Glass
Cc: York Sun
Cc: Stefan Roese
Reviewed-by: Tom Rini
Reviewed-by: Daniel Schwierzeck
19 Jan, 2018
4 commits
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This is useful to make sure no stale data exists in caches after bootloaders.
The worst thing could be some lines of cache were locked in a bootloader
for example during DDR recalibration and never unlocked. This may lead
to really unpredictable issues later down the line.Signed-off-by: Eugeniy Paltsev
Signed-off-by: Alexey Brodkin -
Signed-off-by: Eugeniy Paltsev
Signed-off-by: Alexey Brodkin -
We'd like to keep IOC HW at the same state as t is right after reset when we
start Linux kernel so there will be no re-configuration of IOC on the go.The point is U-Boot doesn't benefit a lot from IOC as it doesn't do a
lot of DMA operations especially on multiple cores simultaneously.At the same time re-configuration of IOC in run-time might become quite
a tricky experience because we need to make sure there're no DMA
trannsactions in flight otherwise unexpected consequencses might affect
us much later and debugging those kinds of issues will be a real
nightmare.That said let's make our life easier a little bit.
Signed-off-by: Eugeniy Paltsev
Signed-off-by: Alexey Brodkin -
Previous SLC management implementation is broken. Seems like it was
never sufficiently tested probably because most of the time IOC was used
instead (i.e. no manual cache operations were done).Now if we disable IOC in U-boot we'll get a lot of errors while using
DMA-enabled peripherals.This time we fix it by substitution of broken per-line SLC operations
region operations as it is done in the Linux kernel (we took it from
v4.14 which is the latest stable as of today).Among other things this implementation might be a bit faster because
instead of iteration over each and every cache line we're taking care
about entire region in one go.Main changes:
* Replaced __slc_line_op (per line operations) by __slc_rgn_op
(region operations).* Reworked __slc_entire_op to get rid of __after_slc_op and
__before_slc_op functions.
Note flush fix (flush only instead of flush-n-inv when OP_FLUSH is
used, see [1] for more details) is already incorporated here.* Added SLC invalidation to invalidate_icache_all().
* Added (start >= end) check to invalidate_dcache_range() and
flush_dcache_range() as some buggy drivers pass region start == end.* Added read-out of MMU BCR so we may know if PAE40 exists in HW and then
act on a particular AUX regs accordingly.[1] http://lists.infradead.org/pipermail/linux-snps-arc/2018-January/003357.html
Signed-off-by: Eugeniy Paltsev
Signed-off-by: Alexey Brodkin
11 Dec, 2017
1 commit
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dcache_exists, icache_exists, slc_exists and ioc_exists global
variables in "arch/arc/lib/cache.c" remain uninitialized if
SoC doesn't have corresponding HW.This happens because we use the next constructions for their
definition and initialization:
-------------------------->>---------------------
int ioc_exists __section(".data");if (/* condition */)
ioc_exists = 1;
-------------------------->>---------------------That's quite a non-trivial issue as one may think of it.
The point is we intentionally put those variables in ".data" section
so they might survive relocation (remember we initilaize them very early
before relocation and continue to use after reloaction). While being
non-initialized and not explicitly put in .data section they would end-up
in ".bss" section which by definition is filled with zeroes.
But since we place those variables in .data section we need to care
about their proper initialization ourselves.Also while at it we change their type to "bool" as more appropriate.
Signed-off-by: Eugeniy Paltsev
Signed-off-by: Alexey Brodkin
25 Nov, 2017
2 commits
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As per ARC HS databook (see chapter 5.3.3.2) it is required to add
3 NOPs after each write to IC_IVIC which we do from now on.Signed-off-by: Alexey Brodkin
Cc: Eugeniy Paltsev -
Currently slave cores will be kick-started even if we want
to dry run bootm which is not what we really want.Signed-off-by: Alexey Brodkin
Cc: Eugeniy Paltsev
16 Aug, 2017
1 commit
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We are now using an env_ prefix for environment functions. Rename these
two functions for consistency. Also add function comments in common.h.Quite a few places use getenv() in a condition context, provoking a
warning from checkpatch. These are fixed up in this patch also.Suggested-by: Wolfgang Denk
Signed-off-by: Simon Glass
30 Jun, 2017
2 commits
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We used to use the same memory layout and size for a couple of
boards and thus we just hardcoding IOC aperture start and size.Now when we're getting more boards with more memory on board we
need to have an ability to set IOC so it matches real DDR layout
and size.Even though it is not really a must but for simplicity we assume
IOC covers all the DDR we have, that gives us a chance to not
bother where DMA buffers are allocated - any part of DDR is OK.Signed-off-by: Alexey Brodkin
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ARCompact cores are not supposed to be used in SMP designs
(this doesn't stop people from creation of heterogeneous chips,
for an example keep reading) so there's no point in
checking ARCNUM and halting somebody if we build for ARC700.Moreover on AXS101 board we have ARC770 in the ASIC together with
other ARC cores and ARC770 happens to be the last node in JTAG chain
with ARCNUM = 4. And existing check halts the one and only core we
want keep running.Signed-off-by: Alexey Brodkin
13 Apr, 2017
1 commit
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This allows us to use the same DRAM init function on all archs. Add a
dummy function for arc, which does not use DRAM init here.Signed-off-by: Simon Glass
[trini: Dummy function on nios2]
Signed-off-by: Tom Rini
11 Apr, 2017
1 commit
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As reported in STAR 9001165532, an SLC control reg read (for checking
busy state) right after SLC invalidate command may incorrectly return
NOT busy causing software to NOT spin-wait while operation is underway.
(and for some reason this only happens if L1 cache is also disabled - as
required by IOC programming model)Suggested workaround is to do an additional Control Reg read, which
ensures the 2nd read gets the right status.Same fix made in Linux kernel:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c70c473396cbdec1168a6eff60e13029c0916854Signed-off-by: Alexey Brodkin
01 Apr, 2017
1 commit
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Even though we expect only master core to execute U-Boot code
let's make sure even if for some reason slave cores attempt to
execute U-Boot in parallel with master they get halted very early.If platform wants it may kick-start slave cores before passing control
to say Linux kernel or any other application that want to see all cores
of SMP SoC up and running.Signed-off-by: Alexey Brodkin
24 Mar, 2017
1 commit
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This commit replaces legacy timer code with usage of arc timer
driver.It removes arch/arc/lib/time.c file and selects CONFIG_CLK,
CONFIG_TIMER and CONFIG_ARC_TIMER options for all ARC boards by default.
Therefore we remove CONFIG_CLK option from less common axs101 and
axs103 defconfigs.Also it removes legacy CONFIG_SYS_TIMER_RATE config symbol from
axs10x.h, tb100.h and nsim.h configs files as it is no longer required.Signed-off-by: Vlad Zakharov
Reviewed-by: Simon Glass
03 Dec, 2016
1 commit
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Commit e2f88dfd2d96 ("libfdt: Introduce new ARCH_FIXUP_FDT option")
allows us to skip memory setup of DTB, but a problem for ARM is that
spin_table_update_dt() and psci_update_dt() are skipped as well if
CONFIG_ARCH_FIXUP_FDT is disabled.This commit allows us to skip only fdt_fixup_memory_banks() instead
of the whole of arch_fixup_fdt(). It will be useful when we want to
use a memory node from a kernel DTB as is, but need some fixups for
Spin-Table/PSCI.Signed-off-by: Masahiro Yamada
Acked-by: Alexey Brodkin
Acked-by: Simon Glass
Fixed build error for x86:
Signed-off-by: Simon Glass
05 Aug, 2016
3 commits
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Starting from arc-2016.03 GNU tools linker properly works with
symbols defined in linker script and so external declarations
are no longer required, dump them.Signed-off-by: Alexey Brodkin
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Initially IVT for ARCv2 was simply copypasted from ARCompact
with some selected fixes so basic stuff works.Now we update it with more ARCv2 specific vectors like
* Software Interrupt
* Division by zero
* Data cache consistency error
* Misaligned accessAlso normal interrupts are now implemented properly and extened to
all possible 240 items.Signed-off-by: Alexey Brodkin
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This might be useful to make sure relocation fixups really
happen. And since this info gets printed only in DEBUG
build it doesn't really hurt normal execution.Signed-off-by: Alexey Brodkin
13 Jun, 2016
2 commits
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According to ARC HS databook it is required to flush and disable
caches prior programming IOC registers. Otherwise ongoing coherent
memory operations may not observe the coherency protocols as
expected.But since in ARC HS v2.1 there's no way to disable SLC (AKA L2 cache)
we're doing our best flushing and invalidating it.Signed-off-by: Alexey Brodkin
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invalidate_dcache_all() could be used in different use-cases
and what is especially important most of those cases won't be
related to DMAed data to or from peripherals, i.e. we'll be doing
invalidation of data used purely by CPU cores.Given that IOC engine only snoops data that goes through DMA
we need to care ourselves about data used only by CPU cores
and so remove dependency on IOC from invalidate_dcache_all()
and always do real invalidation.Signed-off-by: Alexey Brodkin
22 Apr, 2016
1 commit
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flush_dcache_all() is used in the very end of U-Boot self relocation
to write back all copied and then patched code and data to their
new location in the very end of available memory space.Since that has nothing to do with IO (i.e. no external DMA happens
here) IOC won't help here and we need to write back data cache contents
manually.Signed-off-by: Alexey Brodkin
12 Apr, 2016
1 commit
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ISS is obsolete now and nSIM is used for simulation instead.
In its turn nSIM properly handles baud-rate settings so get rid
of now useless check.Signed-off-by: Alexey Brodkin
20 Feb, 2016
2 commits
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With release of ARC HS38 v2.1 new IO coherency engine could be built-in
ARC core. This hardware module ensures coherency between DMA-ed data
from peripherals and L2 cache.With L2 and IOC enabled there's no overhead for L2 cache manual
maintenance which results in significantly improved IO bandwidth.Signed-off-by: Alexey Brodkin
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ARC core could be configured with different L1 and L2 (AKA SLC) cache
line lengths. At least these values are possible and were really used:
32, 64 or 128 bytes.Current implementation requires cache line to be selected upon U-Boot
configuration and then it will only work on matching hardware. Indeed
this is quite efficient because cache line length gets hardcoded during
code compilation. But OTOH it makes binary less portable.With this commit we allow U-Boot to determine real L1 cache line length
early in runtime and use this value later on. This extends portability
of U-Boot binary a lot.Signed-off-by: Alexey Brodkin
14 Jan, 2016
1 commit
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board_init_f_mem() alters the C runtime environment's
stack it is actually already using. This is not a valid
behaviour within a C runtime environment.Split board_init_f_mem into C functions which do not alter
their own stack and always behave properly with respect to
their C runtime environment.Signed-off-by: Albert ARIBAUD
Acked-by: Thomas Chou
01 Jul, 2015
2 commits
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[1] Align cache management functions to those in Linux kernel. I.e.:
a) Use the same functions for all cache ops (D$ Inv/Flush)
b) Split cache ops in 3 sub-functions: "before", "lineloop" and
"after". That way we may re-use "before" and "after" functions for
region and full cache ops.[2] Implement full-functional L2 (SLC) management. Before SLC was
simply disabled early on boot. It's also possible to enable or disable
L2 cache from config utility.[3] Disable/enable corresponding caches early on boot. So if U-Boot is
configured to use caches they will be used at all times (this is useful
in partucular for speed-up of relocation).Signed-off-by: Alexey Brodkin
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With new SMP-enabled CPUs with ARC HS38 cores and corresponding support
in Linux kernel it's required to add basic SMP support in U-Boot.Currently we assume the one and only core starts execution after
power-on. So most of things in U-Boot is handled in UP mode.But when U-Boot is used for loading and starting Linux kernel right
before jumping to kernel's entry point U-Boot:
[1] Sets all slave cores to jump to the same address [kernel's entry
point]
[2] Really starts all slav coresIn ARC's implemetation of SMP in Linux kernel all cores are supposed to
run the same start-up code. But only core with ID 0 (master core)
processes further while others are looping waiting for master core to
complete some initialization.That means it's safe to un-pause slave cores and let them execute kernel
- they will wait for master anyway.Signed-off-by: Alexey Brodkin
Cc: Vineet Gupta
11 Apr, 2015
1 commit
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While testing "arc: make sure _start is in the beginning of .text
section" I haven't done proper clean-up of built binaries and so missed
another tiny bit that lead to the following error:
--->8---
LD u-boot
arc-linux-ld.bfd: cannot find arch/arc/lib/start.o
Makefile:1107: recipe for target 'u-boot' failed
make: *** [u-boot] Error 1
--->8---Fix is trivial: put "start.o" in "extra-y".
Signed-off-by: Alexey Brodkin
10 Apr, 2015
1 commit
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This is important to have entry point in the beginning of .text section
because it allows simple loading and execution of U-Boot.For example pre-bootloader loads U-Boot in memory starting from offset
0x81000000 and then just jumps to the same address.Otherwise pre-bootloader would need to find-out where entry-point is. In
its turn if it deals with binary image of U-Boot there's no way for
pre-bootloader to get required value.Signed-off-by: Alexey Brodkin
03 Apr, 2015
6 commits
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ARCv2 cores may have built-in SLC (System Level Cache, AKA L2-cache).
This change adds functions required for controlling SLC:
* slc_enable/disable
* slc_flush/invalidateFor now we just disable SLC to escape DMA coherency issues until either:
* SLC flush/invalidate is supported in DMA APIin U-Boot
* hardware DMA coherency is implemented (that might be board specific
so probably we'll need to have a separate Kconfig option for
controlling SLC explicitly)Signed-off-by: Alexey Brodkin
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As discussed on mailing list we're drifting away from
CONFIG_SYS_GENERIC_GLOBAL_DATA in favour to use of board_init_f_mem()
for global data.So do this for ARC architecture.
Signed-off-by: Alexey Brodkin
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Intention behind this work was elimination of as much assembly-written
code as it is possible.In case of ARC we already have relocation fix-up implemented in C so why
don't we use C for U-Boot copying, .bss zeroing etc.It turned out x86 uses pretty similar approach so we re-used parts of
code in "board_f.c" initially implemented for x86.Now assembly usage during init is limited to stack- and frame-pointer
setup before and after relocation.Signed-off-by: Alexey Brodkin
Cc: Simon Glass -
This separation makes maintenance of code easier because those low-level
interrupt- or exception handling routines are pretty static and usually
require not much care while start-up code is a subject of modifications
and enhancements.Signed-off-by: Alexey Brodkin
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Even though ARCompact and ARCv2 are not binary compatible most of
assembly instructions are used in both. With this change we'll get rid
of duplicate code.Still IVTs are implemented differently so we're keeping them in separate
files.Signed-off-by: Alexey Brodkin
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always
Make both invalidate_icache_all() and invalidate_dcache_all() available
even if U-Boot is configured with CONFIG_SYS_DCACHE_OFF and/or
CONFIG_SYS_ICACHE_OFF.This is useful because configuration of U-Boot may not match actual
hardware features. Real board may have cache(s) but for some reason we
may want to run U-Boot with cache(s) disabled (for example if some
peripherals work improperly with existing drivers if data cache is
enabled). So board may start with cache(s) enabled (that's the case for
ARC cores with built-in caches) but early in U-Boot we disable cache(s)
and make sure all contents of data cache gets flushed in RAM.Signed-off-by: Alexey Brodkin
09 Feb, 2015
4 commits
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This way we may have very limited set of functions implemented so we
save some space.Also it allows us to build U-Boot for any ARC core with the same one
toolchain because we don't rely on pre-built libgcc.For example:
* we may use little-endian toolchain but build U-Boot for ether
endianess
* we may use non-multilibbed uClibc toolchain but build U-Boot for
whatever ARC CPU flavour that current GCC supportsPrivate libgcc built from generic C implementation contributes only 144
bytes to .text section so we don't see significant degradation of size:
--->8---
$ arc-linux-size u-boot.libgcc-prebuilt
text data bss dec hex filename
222217 24912 214820 461949 70c7d u-boot.libgcc-prebuilt$ arc-linux-size u-boot.libgcc-private
text data bss dec hex filename
222361 24912 214820 462093 70d0d u-boot.libgcc-private
--->8---Also I don't notice visible performance degradation compared to
pre-built libgcc (where at least "*div*" functions are had-written in
assembly) on typical operations of downloading 10Mb uImage over TFTP and
bootm.Signed-off-by: Alexey Brodkin
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This change allows to keep board description clean and minimalistic.
This is especially helpful if one board may house different CPUs with
different features.It is applicable to both FPGA-based boards or those that have CPUs
mounted on interchnagable daughter-boards.Signed-off-by: Alexey Brodkin
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DC_PTAG and IC_PTAG registers only exist in MMUv3.
Signed-off-by: Alexey Brodkin
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It's prohibited to put branch instruction in the very end of zero-delay
loop. On execution this causes "Illegal instruction" exception.Signed-off-by: Alexey Brodkin
Signed-off-by: Igor Guryanov
