Eric Lee / smarc-uboot

15 Feb, 2018

1 commit

10 Feb, 2018

1 commit

  • ee3556bca   drivers/ddr/fsl: Dual-license DDR driver ... Browse Code »
    20

    To make this driver easier to be reused, dual-license DDR driver.

    Signed-off-by: York Sun
    CC: Simon Glass
    CC: Tom Rini
    CC: Heinrich Schuchardt
    CC: Thomas Schaefer
    CC: Masahiro Yamada
    CC: Robert P. J. Day
    CC: Alexander Merkle
    CC: Joakim Tjernlund
    CC: Curt Brune
    CC: Valentin Longchamp
    CC: Wolfgang Denk
    CC: Anatolij Gustschin
    CC: Ira W. Snyder
    CC: Marek Vasut
    CC: Kyle Moffett
    CC: Sebastien Carlier
    CC: Stefan Roese
    CC: Peter Tyser
    CC: Paul Gortmaker
    CC: Peter Tyser
    CC: Jean-Christophe PLAGNIOL-VILLARD

    York Sun
     

11 Sep, 2017

1 commit

  • 63b2316c5   fsl-layerscape: Consolidate registers space defination for CCI-400 bus ... Browse Code »

    CoreLink Cache Coherent Interconnect (CCI) provides full cache
    coherency between two clusters of multi-core CPUs and I/O coherency
    for devices and I/O masters.

    This patch add new config option SYS_FSL_HAS_CCI400 and moves
    existing register space definaton of CCI-400 bus to fsl_immap to be
    shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET
    in Kconfig.

    Signed-off-by: Ashish Kumar
    Signed-off-by: Prabhakar Kushwaha
    [YS: revised commit message, squashed patches for armv8 and armv7]
    Reviewed-by: York Sun

    Ashish Kumar
     

15 Sep, 2016

1 commit

21 May, 2015

1 commit

23 Apr, 2014

1 commit

26 Nov, 2013

1 commit