17 Apr, 2015
1 commit
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Add a convenience function to access the private data that a uclass stores
for each of its devices. Convert over most existing uses for consistency
and to provide an example for others.Signed-off-by: Simon Glass
10 Apr, 2015
1 commit
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The controller's Reed-Solomon ECC hardware is
used except of course for raw reads and writes.
It covers in- and out-of-band data together.The SPL framework is supported.
Signed-off-by: Albert ARIBAUD (3ADEV)
01 Apr, 2015
2 commits
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Add support for on-flash bad block table. This makes U-Boot handle an existing
BBT correctly.Signed-off-by: David Dueck
Reviewed-by: Boris BREZILLON
CC: Boris BREZILLON
CC: Josh Wu
CC: Andreas Bießmann
CC: Scott Wood
Acked-by: Josh Wu
31 Mar, 2015
7 commits
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Testing showed, that commands like STATUS made the buffer dirty
when executed with NFC_SECSZ set to the page size. It looks
like the controller transfers bogus data when this register
is configured. When setting it to 0, the buffer does not get
altered while the status command still seems to work flawless.Signed-off-by: Stefan Agner
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The driver tries to re-use the page buffer by storing the page
number of the current page in the buffer. The page is only read
if the requested page number is not currently in the buffer. When
a block is erased, the page number is marked as invalid if the
erased page equals the one currently in the cache. However, since
a erase block consists of multiple pages, also other page numbers
could be affected.The commands to reproduce this issue (on a written page):
> nand dump 0x800
> nand erase 0x0 0x20000
> nand dump 0x800The second nand dump command returns the data from the buffer,
while in fact the page is erased (0xff).Avoid the hassle to calculate whether the page is affected or not,
but set the page buffer unconditionally to invalid instead.Signed-off-by: Stefan Agner
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This command is only enabled by one board, complicates the NAND code,
and doesn't appear to have been functioning properly for several
years. If there are no bad blocks in the NAND region being written
nand_write_skip_bad() will take the shortcut of calling nand_write()
which bypasses the special yaffs handling. This causes invalid YAFFS
data to be written. See
http://lists.denx.de/pipermail/u-boot/2011-September/102830.html for
an example and a potential workaround.U-Boot still retains the ability to mount and access YAFFS partitions
via CONFIG_YAFFS2.Signed-off-by: Peter Tyser
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The CONFIG_MTD_NAND_VERIFY_WRITE has been removed from Linux for some
time and a more generic method of NAND verification now exists in U-Boot.Signed-off-by: Peter Tyser
Tested-by: Heiko Schocher
Acked-by: Heiko Schocher -
Add nand_verify() and nand_verify_page_oob(). nand_verify() verifies
NAND contents against an arbitrarily sized buffer using ECC while
nand_verify_page_oob() verifies a NAND page's contents and OOB.Signed-off-by: Peter Tyser
Tested-by: Heiko Schocher
Acked-by: Heiko Schocher -
There is only one pio_word in this DMA transaction so data field must be 1.
Signed-off-by: Luca Ellero
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There is only one pio_word in this DMA transaction so data field must be 1.
Signed-off-by: Luca Ellero
06 Mar, 2015
2 commits
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The 'nandecc sw' command selects a software-based error correction
algorithm. By default, this is OMAP_ECC_HAM1_CODE_SW but some
platforms use OMAP_ECC_BCH8_CODE_HW_DETECTION_SW as their
software-based correction algorithm. Allow a user to be specific e.g.
# nandecc sw
where 'hamming' is still the default.Note: we don't just use CONFIG_NAND_OMAP_ECCSCHEME as it might be set
to a hardware-based ECC scheme---a little strange when the user
has requested 'sw' ECC.Signed-off-by: Ash Charles
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Commit fb384c4720ca7496775d6578f184bf628db73456 introduced the use of
WAIT0 pin for determining whether the NAND is ready or not. This only
works if all NAND chips are connected to WAIT0. If some chips are
connected to the other available pin WAIT1, nand_wait() does not really
wait and prints a WARN_ON message.This patch allows the board to provide configuration of which chip is
connected to which WAITx signal. For example, one can define in
include/configs/foo.h:#define CONFIG_NAND_OMAP_GPMC_WSCFG 0,0,1,1
This would mean that chips using to CS0 and 1 are connected to WAIT0 and
chips with CS2 and 3 are connected to WAIT1.Signed-off-by: Michal Sojka
Acked-by: Stefan Roese
Tested-by: Michal VokáčCc: Tom Rini
25 Feb, 2015
2 commits
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Now CONFIG_SPL_BUILD is not defined in Kconfig, so
"!depends on SPL_BUILD" and "if !SPL_BUILD" are redundant.Signed-off-by: Masahiro Yamada
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When Kconfig for U-boot was examined, one of the biggest issues was
how to support multiple images (Normal, SPL, TPL). There were
actually two options, "single .config" and "multiple .config".
After some discussions and thought experiments, I chose the latter,
i.e. to create ".config", "spl/.config", "tpl/.config" for Normal,
SPL, TPL, respectively.It is true that the "multiple .config" strategy provided us the
maximum flexibility and helped to avoid duplicating CONFIGs among
Normal, SPL, TPL, but I have noticed some fatal problems:[1] It is impossible to share CONFIG options across the images.
If you change the configuration of Main image, you often have to
adjust some SPL configurations correspondingly. Currently, we
cannot handle the dependencies between them. It means one of the
biggest advantages of Kconfig is lost.[2] It is too painful to change both ".config" and "spl/.config".
Sunxi guys started to work around this problem by creating a new
configuration target. Commit cbdd9a9737cc (sunxi: kconfig: Add
%_felconfig rule to enable FEL build of sunxi platforms.) added
"make *_felconfig" to enable CONFIG_SPL_FEL on both images.
Changing the configuration of multiple images in one command is a
generic demand. The current implementation cannot propose any
good solution about this.[3] Kconfig files are getting ugly and difficult to understand.
Commit b724bd7d6349 (dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to
Kconfig) has sprinkled "if !SPL_BUILD" over the Kconfig files.[4] The build system got more complicated than it should be.
To adjust Linux-originated Kconfig to U-Boot, the helper script
"scripts/multiconfig.sh" was introduced. Writing a complicated
text processor is a shell script sometimes caused problems.Now I believe the "single .config" will serve us better. With it,
all the problems above would go away. Instead, we will have to add
some CONFIG_SPL_* (and CONFIG_TPL_*) options such as CONFIG_SPL_DM,
but we will not have much. Anyway, this is what we do now in
scripts/Makefile.spl.I admit my mistake with my apology and this commit switches to the
single .config configuration.It is not so difficult to do that:
- Remove unnecessary processings from scripts/multiconfig.sh
This file will remain for a while to support the current defconfig
format. It will be removed after more cleanups are done.- Adjust some makefiles and Kconfigs
- Add some entries to include/config_uncmd_spl.h and the new file
scripts/Makefile.uncmd_spl. Some CONFIG options that are not
supported on SPL must be disabled because one .config is shared
between SPL and U-Boot proper going forward. I know this is not
a beautiful solution and I think we can do better, but let's see
how much we will have to describe them.- update doc/README.kconfig
More cleaning up patches will follow this.
Signed-off-by: Masahiro Yamada
Reviewed-by: Simon Glass
17 Feb, 2015
1 commit
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The patch c316f577b4b72d1a1aeb559e9b3fad20808f1ffd breaks
siemens boards because prefetch mode is not enabled.
I assume it breaks other boards as well that don't use
prefetch.This patch sets read_buf to nand_read_buf if
NAND_OMAP_GPMC_PREFETCH is not defined.Signed-off-by: Samuel Egli
CC: Daniel Mack
CC: Guido Martínez
CC: Tom Rini
CC: Heiko Schocher
13 Feb, 2015
1 commit
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Expand the help messages for each driver. Add missing Kconfig for I2C,
SPI flash and thermal.Signed-off-by: Simon Glass
Reviewed-by: Masahiro Yamada
08 Feb, 2015
1 commit
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As the PMECC hardware has different version. In SAMA5D4 chip, the PMECC ip
can generate 0xff pmecc ECC value for all 0xff sector.According to this, add PMECC version check, if it's SAMA5D4 then we always
let PMECC hardware to correct it.Signed-off-by: Josh Wu
Acked-by: Bo Shen
Acked-by: Andreas Bießmann
05 Feb, 2015
1 commit
30 Jan, 2015
3 commits
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At present we go through various contortions to store the SPI slave's chip
select in its private data. This only exists when the slave is active so
must be set up when it is probed. Until the device is probed we don't
actually know what chip select it will appear on.However, now that we can support per-child platform data, we can use that
instead. This allows us to set up the chip select when the child is bound,
and avoid the messy contortions.Unfortunately this is a fairly large change and it seems to be difficult to
break it down further.Signed-off-by: Simon Glass
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Use a single exit point when we have an error and add debugging there.
Signed-off-by: Simon Glass
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These functions are going away, so use the new uclass support instead.
Signed-off-by: Simon Glass
28 Jan, 2015
1 commit
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if "ubi part" fails, reset also mtd_devs to 0, as
further "ubi part" would use wrong mtd_devs.Signed-off-by: Heiko Schocher
24 Jan, 2015
1 commit
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These boards are still non-generic boards.
It is a good thing that we can drop board-specific hack code
from drivers/mtd/nand/nand_base.cSigned-off-by: Masahiro Yamada
Acked-by: Stefan Roese
Cc: Andrea "llandre" Marson
14 Jan, 2015
1 commit
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Enable GPMC's prefetch feature for NAND access. This speeds up NAND read
access a lot by pre-fetching contents in the background and reading them
through the FIFO address.The current implementation has two limitations:
a) it only works in 8-bit mode
b) it only supports read accessBoth is easily fixable by someone who has hardware to implement it.
Note that U-Boot code uses non word-aligned buffers to read data into, and
request read lengths that are not multiples of 4, so both partial buffers
(head and tail) have to be addressed.Tested on AM335x hardware.
Tested-by: Guido Martínez
Reviewed-by: Guido Martínez
Signed-off-by: Daniel Mack
[trini: Make apply again, use 'cs' fix pointed out by Guido]
Signed-off-by: Tom Rini
10 Jan, 2015
3 commits
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Currently, "nand scrub" runs chip->scan_bbt at the end of
nand_erase_opts() even if NAND_SKIP_BBTSCAN flag is set.It violates the intention of NAND_SKIP_BBTSCAN.
Move NAND_SKIP_BBTSCAN flag check to nand_block_checkbad() so that
chip->scan_bbt() is never run if NAND_SKIP_BBTSCAN is set.Also, unset NAND_BBT_SCANNED flag instead of running chip->scan_bbt()
right after scrub. We can be lazier here because the BBT is scanned
at the next call of nand_block_checkbad().Signed-off-by: Masahiro Yamada
Cc: Scott Wood -
Commit 35c204d8a9d0 (nand: reinstate lazy bad block scanning)
broke NAND_BBT_USE_FLASH feature.Its git-log claimed that it reinstated the change as by commit
fb49454b1b6c ("nand: reinstate lazy bad block scanning"), but it moved
"chip->options |= NAND_BBT_SCANNED" below "chip->scan_bbt(mtd);".It causes recursion if scan_bbt does not find a flash based BBT
and tries to write one, and the attempt to erase the BBT area
causes a bad block check.Reinstate commit ff49ea8977b5 (NAND: Mark the BBT as scanned prior to
calling scan_bbt.).Signed-off-by: Masahiro Yamada
Cc: Rostislav Lisovy
Cc: Heiko Schocher
Cc: Scott Wood -
Since commit ff94bc40af34 (mtd, ubi, ubifs: resync with Linux-3.14),
the "nand scrub" command has not been working.Signed-off-by: Masahiro Yamada
Cc: Scott Wood
Cc: Heiko Schocher
06 Jan, 2015
1 commit
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"err" was an unsigned variable, causing negative error codes to turn
into positive values, which are interpreted as an amount of succesfully
corrected bitflips (and thus not an error).In particular, this resulted in that if the elm reports uncorrectable
errors (-EBADMSG), the MTD layer (and UBI) falsely succeeded.Signed-off-by: Guido Martínez
Reviewed-by: Stefan Roese
18 Dec, 2014
4 commits
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Add the necessary flash entry for the Spansion S25FL164K
flash. Tested on Marvell 88F6218 based design.Signed-off-by: Ben Dooks
Reviewed-by: Jagannadha Sutradharudu Teki -
Added S25FL116K flash and tested on Marvell 88F6281 based system.
Signed-off-by: Adnan Ali
Reviewed-by: Jagannadha Sutradharudu Teki -
Add support for SST25WF040B-40I-SN flash.
Tested on T1024QDS board.Signed-off-by: Shengzhou Liu
Reviewed-by: Jagannadha Sutradharudu Teki -
Removed ramtron driver since the EMK boards are
no longer been active, and these are the only boards
used this flash driver.Commit details for EMK zap:
"ppc/arm: zap EMK boards"
(sha1: d58a9451e7339ed4cf2b2627e534611f427fb791)Signed-off-by: Jagannadha Sutradharudu Teki
Cc: Reinhard Meyer
14 Dec, 2014
4 commits
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Enabled byte program support for sst flashes in sf.
Few controllers will only support BP, so this patch gives
a tx transfer flag to set the BP so-that sf will operate
on byte program transfer.A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI
controller to use byte program op for SST flash.Signed-off-by: Jagannadha Sutradharudu Teki
Tested-by: Bin Meng -
Currently if SST flash advertises SST_WP flag in the params table
the word program command (ADh) with auto address increment will be
used for the flash write op. However some SPI controllers do not
support the word program command (like the Intel ICH 7), the byte
programm command (02h) has to be used.Signed-off-by: Bin Meng
Acked-by: Simon Glass
Tested-by: Simon Glass
Reviewed-by: Jagannadha Sutradharudu Teki -
At present SECT_4K is the same as SST_WP so we cannot tell these apart. Fix
this so that the table in sf_params.c can be used correctly.Reported-by: Jens Rottmann
Signed-off-by: Simon Glass
Reviewed-by: Jagannadha Sutradharudu Teki -
Few of the spi controllers are only supports array slow
read which is quite different behaviour compared to others.So this fix on sf will correctly handle the slow read supported
controllers.Signed-off-by: Jagannadha Sutradharudu Teki
Tested-by: Bin Meng
12 Dec, 2014
2 commits
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'eccstat' array elements might be used uninitialized
Signed-off-by: Jaiprakash Singh
Reviewed-by: York Sun -
This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Alison Wang
Reviewed-by: York Sun
05 Dec, 2014
1 commit
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The functions to detect the state of the ready / busy signal is already
available but only used in the SPL case. Lets use it always, also for the
main U-Boot. As all boards should have this HW connection.Testing on Siemens Draco (am335x) showed a small perfomance gain by using
this ready pin to detect the NAND chip state. Here the values tested on
Draco with Hynix 4GBit NAND:Without NAND ready pin:
U-Boot# time nand read 80400000 0 400000
NAND read: device 0 offset 0x0, size 0x400000
4194304 bytes read: OKtime: 2.947 seconds, 2947 ticks
With NAND ready pin:
U-Boot# time nand read 80400000 0 400000
NAND read: device 0 offset 0x0, size 0x400000
4194304 bytes read: OKtime: 2.795 seconds, 2795 ticks
So an increase of approx. 5%.
Signed-off-by: Stefan Roese
Cc: Tom Rini
Cc: Scott Wood
Cc: Roger Meier
Cc: Samuel Egli
