28 May, 2020
1 commit
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When primary image boot is failed, ROM will select secondary image to
boot if SIT (secondary image table) exists. However, SPL does not know
the secondary boot, still loads the FIT from the position of primary image.Introduce a config to add secondary image sector offset to FIT sector
offset. This config is default set to 0. Secondary image should configure
it to the same value of firstSectorNumber field in SIT.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
13 May, 2020
2 commits
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Add support for imx8mn audio board 2.0 support
reuse common settings from imx8mn evk som
Rework for imx_v2020.04 defconfig, dts and SPLReviewed-by: Ye Li
Signed-off-by: Adrian Alonso -
Add support for imx8mm audio board 2.0 support
reuse common settings from imx8mm evk som
Rework for imx_v2020.04 defconfig, dts and SPLReviewed-by: Ye Li
Signed-off-by: Adrian Alonso
01 May, 2020
2 commits
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Porting board codes, configurations, DTS and DDR initialization codes
for the DDR3L and DDR4 validation boards from imx_v2019.04Ready functions:
- DDR3L board: SD, UART, I2C, USB host and NAND
FPGA on the board controls WDOG_B and ENET PHY reset, so reset
and ethernet can't work- DDR4 board: SD/eMMC, I2C, ENET, Flexspi, UART and USB
Signed-off-by: Ye Li
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Porting board codes, configurations, DTS and DDR initialization codes
for the DDR3L and DDR4 validation boards from imx_v2019.04Supported modules
- DDR3L VAL: Two RANK DDR3L, QSPI B, eMMC/SD, RMII ENET, UART.
- DDR4 VAL: Two RANK DDR4, SD, NAND, RGMII ENET, UARTSigned-off-by: Ye Li
27 Apr, 2020
6 commits
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Add support for iMX8MN LPDDR4 EVK board which uses 2GB LPDDR4 and
PCA9450B PMIC.Signed-off-by: Ye Li
(cherry picked from commit c62f119c6ccde6faefb42314047dc67bb130febd)
(cherry picked from commit d73d363ba70ddf3a411dc57c95d7d2e3d2beb245) -
To align with other iMX8M platforms, use CONFIG_TARGET_IMX8MN_DDR4_EVK for
DDR4 EVK board and will use CONFIG_TARGET_IMX8MN_EVK for LPDDR4 EVK.Signed-off-by: Ye Li
(cherry picked from commit 2fa2f90417df4c68beb78e40c77725ca3caba08e)
(cherry picked from commit 2e06698f0cfd0d06dce80f99b742d5b236e80d02) -
On B1 chips with HAB v4.4, the sticky bits are not locked up in
HAB closed mode. We introduce a workaround in SPL to lock up
these bits and clear Manufacturing Protection Private Key for
secure boot.For field return case, user has to build a SPL with
CONFIG_SECURE_STICKY_BITS_LOCKUP=n and set CONFIG_IMX_UNIQUE_ID to
part's unique id. When the UID check is passed, sticky bits are not
lockup and users can burn field return fuse. Otherwise the boot will
stop.Signed-off-by: Ye Li
(cherry picked from commit c98b47f1ff60e1f99807e24fd76053ad880f803e) -
ROM SError happens on two cases:
1. ERR050342, on iMX8MQ HDCP enabled parts ROM writes to GPV1 register, but
when ROM patch lock is fused, this write will cause SError.2. ERR050350, on iMX8MQ/MM/MN, when the field return fuse is burned, HAB
is field return mode, but the last 4K of ROM is still protected and cause SError.Since ROM mask SError until ATF unmask it, so then ATF always meets the exception.
This patch works around the issue in SPL by enabling SPL Exception vectors table
and the SError exception, take the exception to eret immediately to clear the SError.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit f05dd45251ca82cc54e13a616f00744c26faab53)
(cherry picked from commit 25d059411e702a4002f1aa157839001f796dd9f6) -
Update the board codes to use latest DDR script and support flexspi boot,
USB host/gadget, etc.
Also add DDR4 EVK board support for RAW NAND boot.Signed-off-by: Ye Li
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This patch enable CAAM support for i.MX8M platforms.
Signed-off-by: Aymen Sghaier
(cherry picked from commit 1fc92e6e34b06bdee81240ce06326aca1d9c02d8)
(cherry picked from commit b0f889b77b367b69aa0778b1d03a2ec30fdee243)
(cherry picked from commit f5c28e63f19ef99e0fe4d01b176789aacc507d79)
09 Feb, 2020
1 commit
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This adds initial minimal support for the Toradex Verdin iMX8M Mini Quad
2GB WB IT V1.0A module. They are now strapped to boot from eFuses which
are factory fused to properly boot from their on-module eMMC. U-Boot
supports booting from the on-module eMMC only, SDP support is disabled
for now due to missing i.MX 8M Mini USB support.Functionality wise the following is known to be working:
- eMMC, 8-bit and 4-bit MMC/SD card slots
- Ethernet
- GPIOs
- I2CBoot sequence is:
SPL ---> ATF (TF-A) ---> U-boot properATF, U-boot proper and u-boot.dtb images are packed into a FIT image,
loaded by SPL.Boot:
U-Boot SPL 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100)
Normal Boot
Trying to boot from MMC1
NOTICE: Configuring TZASC380
NOTICE: RDC off
NOTICE: BL31: v2.0(release):rel_imx_4.14.98_2.3.0-0-g09c5cc994-dirty
NOTICE: BL31: Built : 01:11:41, Jan 25 2020
NOTICE: sip svc initU-Boot 2020.01-00187-gd411d164e5 (Jan 26 2020 - 04:47:26 +0100)
CPU: Freescale i.MX8MMQ rev1.0 at 0 MHz
Reset cause: POR
DRAM: 2 GiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In: serial
Out: serial
Err: serial
Model: Toradex Verdin iMX8M Mini Quad 2GB Wi-Fi / BT IT V1.0A, Serial#
06535149
Net: eth0: ethernet@30be0000
Hit any key to stop autoboot: 0
Verdin iMX8MM #Signed-off-by: Igor Opaniuk
Signed-off-by: Max Krummenacher
Signed-off-by: Marcel Ziswiler
Reviewed-by: Oleksandr Suvorov
08 Jan, 2020
2 commits
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Add basic i.MX8MP EVK board support
U-Boot SPL 2020.01-rc4-00388-gb1bf40c0ae-dirty (Dec 30 2019 - 17:55:33 +0800)
power_pca9450b_init
DDRINFO: start DRAM init
DDRINFO:ddrphy calibration done
DDRINFO: ddrmix config done
Normal Boot
Failed to find clock node. Check device tree
WDT: Not found!
Trying to boot from BOOTROM
image offset 0x8000, pagesize 0x200, ivt offset 0x0U-Boot 2020.01-rc4-00388-gb1bf40c0ae-dirty (Dec 30 2019 - 17:55:33 +0800)
CPU: Freescale i.MX8MP rev1.0 at 1000 MHz
Reset cause: POR
Model: NXP i.MX8MPlus EVK board
DRAM: 6 GiB
MMC: FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In: serial
Out: serial
Err: serial
Net: No ethernet found.
Hit any key to stop autoboot: 0
u-boot=> mmc list
FSL_SDHC: 1 (SD)
FSL_SDHC: 2Signed-off-by: Peng Fan
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Add Kconfig entry for i.MX8MP
Signed-off-by: Peng Fan
05 Nov, 2019
2 commits
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Support pinctrl/clk/sdhc, include ddr4 timing data.
Log:
U-Boot SPL 2019.10-rc3-00356-g497c500423-dirty (Sep 16 2019 - 10:54:58 +0800)
Normal Boot
Trying to boot from BOOTROM
image offset 0x8000, pagesize 0x200, ivt offset 0x0U-Boot 2019.10-rc3-00356-g497c500423-dirty (Sep 16 2019 - 10:54:58 +0800)
CPU: Freescale i.MX8MNano rev1.0 at 24 MHz
Reset cause: POR
Model: NXP i.MX8MNano DDR4 EVK board
DRAM: 2 GiB
MMC: FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... *** Warning - bad CRC, using default environmentIn: serial
Out: serial
Err: serial
Net: No ethernet found.
Hit any key to stop autoboot: 0Signed-off-by: Peng Fan
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Add i.MX8MN kconfig entry
Signed-off-by: Peng Fan
08 Oct, 2019
3 commits
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Add board and SoC dts
Add ddr training code
support SD/MMC/GPIO/PINCTRL/UARTSigned-off-by: Peng Fan
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Add IMX8MM kconfig entry
Signed-off-by: Peng Fan
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Add IMX8MQ kconfig entry, preparing support IMX8MM
Signed-off-by: Peng Fan
01 Jan, 2019
2 commits
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Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy
firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to
DRAM.The boot log with Arm trusted firmware console enabled:
"
U-Boot SPL 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800)
PMIC: PFUZE100 ID=0x10
Normal Boot
Trying to boot from MMC2
NOTICE: Configureing TZASC380
NOTICE: BL31: v1.5(release):p9.0.0_1.0.0-beta-20180928-8-ge09c4b62-dirty
NOTICE: BL31: Built : 09:28:54, Nov 8 2018
lpddr4 swffc start
NOTICE: sip svc initU-Boot 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800)
CPU: Freescale i.MX8MQ rev2.0 at 1000 MHz
Reset cause: POR
Model: Freescale i.MX8MQ EVK
DRAM: 3 GiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
In: serial
Out: serial
Err: serial
Net:
Warning: ethernet@30be0000 using MAC address from ROM
eth0: ethernet@30be0000
Hit any key to stop autoboot: 0
"Signed-off-by: Peng Fan
Cc: Fabio Estevam
Cc: Stefano Babic -
Rename mx8m,MX8M to imx8m,IMX8M
Signed-off-by: Peng Fan
Signed-off-by: Jon Nettleton