01 May, 2014
1 commit
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Allow ci_udc.o to be built when using the new(?) USB gadget framework,
as enabled by CONFIG_USB_GADGET.Note that this duplicates the Makefile entry for ci_udc.o, since it's
also included inside #ifdef CONFIG_USB_ETHER. I'm not sure what that
define means; perhaps an old style of Ethernet-specific USB gadget
implementation?I wonder if the line that this patch adds shouldn't be outside all of
the ifdefs, so it stands on its own, similar to how e.g. epautoconf.o
is shared between the two?Signed-off-by: Stephen Warren
30 Apr, 2014
13 commits
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ci_udc.c allocates only a single buffer for each endpoint, which
ci_ep_alloc_request() returns as a hard-coded value rather than
dynamically allocating. Consequently, storage_common.c must limit
itself to using a single buffer at a time. Add a special case
to the definition of FSG_NUM_BUFFERS for this.Another option would be to fix ci_ep_alloc_request() to dynamically
allocate the buffers like some/all(?) other device mode drivers do.
However, I don't think that ci_ep_queue() supports queueing up
multiple buffers either yet, and I'm not familiar enough with the
controller yet to implement that. As such, any attempt to use multiple
buffers simply results in data corruption and other errors.Signed-off-by: Stephen Warren
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Tegra's USB controller appears to be a variant of the ChipIdea
controller; perhaps derived from it, or simply a different version of
the IP core to what U-Boot supports today.In this variant, at least the following difference are present:
- Some registers are moved about.
- Setup transaction completion is reported in a separate 'epsetupstat'
register, rather than in 'epstat' (which still exists, perhaps for
other transaction types).
- USB connection speed is reported in a separate 'hostpc1_devlc'
register, rather than 'portsc'.
- The registers used by ci_udc.c begin at offset 0x130 from the USB
register base, rather than offset 0x140. However, this is handled
by the associated EHCI controller driver, since the register address
is stored in controller.ctrl->hcor.Introduce define CONFIG_CI_UDC_HAS_HOSTPC to indicate which variant of
the controller should be supported. The "HAS_HOSTPC" part of this name
mirrors the similar "has_hostpc" field used by the Linux EHCI controller
core to represent the presence/absence of the hostpc1_devlc register.Signed-off-by: Stephen Warren
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usb_gadget_register_driver() currently unconditionally programs PORTSC
to select a ULPI PHY. This is incorrect on at least the Tegra boards I
am testing with, which use a UTMI PHY for the OTG ports. Make the PHY
selection code conditional upon the specific EHCI controller that is in
use.Ideally, I believe that the PHY initialization code should be part of
ehci_hcd_init() in the relevant EHCI controller driver, or some board-
specific function that ehci_hcd_init() calls.For MX6, I'm not sure this PHY initialization code is correct even before
this patch, since ehci-mx6's ehci_hcd_init() already configures PORTSC to
a board-specific value, and it seems likely that the code in ci_udc.c is
incorrectly undoing this. Perhaps this is not an issue if the PHY
selection register bits aren't implemented on this instance of the MX6
USB controller?ehci-mxs.c doens't appear to touch PORTSC, so this code is likely still
required there.Signed-off-by: Stephen Warren
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At least drivers/usb/gadget/storage_common.c expects that ep->req.actual
contain the number of bytes actually transferred. (At least in practice,
I observed it failing to work correctly unless this was the case).However, ci_udc.c modifies ep->req.length instead. I assume that .length
is supposed to represent the allocated buffer size, whereas .actual is
supposed to represent the actual number of bytes transferred. In the OUT
transaction case, this may happen simply because the host sends a smaller
packet than the max possible size, which is quite legal. In the IN case,
transferring fewer bytes than requested could presumably happen as an
error.Modify handle_ep_complete() to write to .actual rather than modifying
.length.Signed-off-by: Stephen Warren
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ci_ep_queue() currently only fills in the page0/page1 fields in the
queue item. If the buffer is larger than 4KiB (unaligned) or 8KiB
(page-aligned), then this prevents the HW from knowing where to write
the balance of the data.Fix this by initializing all 5 pageN pointers, which allows up to
16KiB (potentially non-page-aligned) buffers.Signed-off-by: Stephen Warren
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This patch remove always false (since we tested ret = 0) ternary operator
with ret value returned.Signed-off-by: Lukasz Majewski
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Commit 4a271cb1b4ff doesn't take into account that fdtdec_setup_gpio()
returns success when the gpio passed to it is FDT_GPIO_NONE (no
gpio node found in the fdtdec_decode_gpio() call). This results in
calling gpio_direction_output() on invalid gpio. For this reason
executing "usb start" command on Arndale causes data abort in the
ehci-exynos driver.Add the fdt_gpio_isvalid() check to fix that problem.
Signed-off-by: Andrey Konovalov
Cc: Julius Werner
Cc: Simon Glass
Cc: Minkyu Kang
Cc: Marek Vasut -
Add missing missing disconnect and unbind calls to the musb gadget driver's
usb_gadget_unregister_driver function. Otherwise, any gadget drivers fail
to uninitialize and run a 2nd time.Signed-off-by: Rob Herring
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Allow a NULL table to be passed to usb_gadget_get_string for cases
when a string table may not be populated.Signed-off-by: Rob Herring
Reviewed-by: Tom Rini
Acked-by: Marek Vasut
Acked-by: Lukasz Majewski -
Since dfu read/write operations needs to be flushed manually,
writing to filesystem on MMC by thor was broken. MMC raw write
actually is working fine because current dfu_flush() function
writes filesystem only. This commit adds dfu_flush() to f_thor
and now filesystem write is working.This change was tested on Trats2 board.
Signed-off-by: Przemyslaw Marczak
Cc: Lukasz Majewski
Cc: Marek Vasut
Cc: Heiko Schocher
Cc: Tom Rini -
In thor's download_tail() function, dfu_get_entity() is called
before each dfu_write() call and the returned entity pointers
are the same. So dfu_get_entity() can be called just once and
this patch changes this.Signed-off-by: Przemyslaw Marczak
Cc: Lukasz Majewski
Cc: Marek Vasut
Cc: Heiko Schocher
Cc: Tom Rini -
Update the EHCI driver to support interrupt transfers on PowerPC.
Signed-off-by: Adrian Cox
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The rmobile SoC has usb host controller.
This supports USB controllers listed in the R8A7790, R8A7791 and R8A7740.Signed-off-by: Nobuhiro Iwamatsu
Reviewed-by: Marek Vasut
29 Apr, 2014
2 commits
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Most of the I2C slaves support accesses in the typical style
that is : read/write series of bytes at particular address offset.
These transactions look like:"
(1) START:Address:Tx:Offset:RESTART:Address[0..4]:Tx/Rx:data[0..n]:STOP"However there are certain devices which support accesses in
terms of the transactions as follows:
(2) "START:Address:Tx:Txdata[0..n1]:Clock_stretching:
RESTART:Address:Rx:data[0..n2]"
Here Txdata is typically a command and some associated data,
similarly Rxdata could be command status plus some data received
as a response to the command sent.Type (1) transactions are currently supportd in the
i2c driver using i2c_read and i2c_write APIs. I2C EEPROMs,
RTC, etc fall in this category.To handle type (2) along with type (1) transactions,
i2c_read() function has been modified.Signed-off-by: Shaveta Leekha
Signed-off-by: Poonam Aggrwal -
This driver needs a data structure in SRAM before SDRAM is available.
This is not alway the case using .data section. Moving this data
structure to global_data guarantees it is writable.Signed-off-by: York Sun
CC: Troy Kisky
26 Apr, 2014
1 commit
23 Apr, 2014
16 commits
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ar8031 has the same config steps with ar8021, so change its
config func to ar8021_config instead of genphy_config.Signed-off-by: Zhao Qiang
Reviewed-by: York Sun -
Add support of loading image, binary for MMC and SPI during SPL boot.
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
SPI driver perform its operation(read/write) on 64KB buffer chunk for data
greater than 64KB. This buffer chunk is allocated from system heap.During SPL boot, 768KB of data is read from SPI flash.
Here, heap size may not be sufficient enough to full-fill 64KB buffer
requirement of SPI driver. So break down u-boot read operation at 8KB of chunk.Also, fix a warning i.e. "unused variable buf" during CONFIG_FSL_CORENET
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
nand_spl_load_image() can also be used for non TPL framework.
Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.Signed-off-by: Tang Yuantian
Reviewed-by: York Sun -
This is a theoretical possible out of bounds error in DDR driver. Adding
check before using array index. Also change some runtime conditions to
pre-compiling conditions.Signed-off-by: York Sun
Reviewed-by: York Sun -
MDIO clock needs to be initialized in u-boot code for SoCs
having FMAN-v3(v3H or v3L) controller due to below reasons-On SoCs that have FMAN-v3H like B4860, default value of
MDIO_CLK_DIV bits in mdio_stat(mdio_cfg) register generates
mdio clock too high (much higher than 2.5MHz), violating the
IEEE specs.
-On SOCs that have FMAN-v3L like T1040, default value of
MDIO_CLK_DIV bits is zero, so MDIO clock is disabled.So, for proper functioninig of MDIO, MDIO_CLK_DIV bits needs to
be properly initialized.
Also this type of initialization is generally done in
PBI(pre-bootloader) phase using rcw.But for chips like T1040
which support deep-sleep, such type of initialization cannot be
done in PBI phase due to the limitation that during deep-sleep
resume, FMAN (MDIO) registers are not accessible in PBI phase.
So, mdio clock initailization must be done as part of u-boot.This initialization code is implemented in memac_phy.c which
gets compiled only for SoCs having FMANv3, so no extra compilation
flag is required.Signed-off-by: Priyanka Jain
Reviewed-by: York Sun -
Increase TXFIFOTHRES field value in TXFILLTUNING register of usb for T4 Rev 2.0.
This decreases data burst rate with which data packets are posted from the TX
latency FIFO to compensate for latencies in DDR pipeline during DMA.
This avoids Tx buffer underruns and leads to successful usb writesSigned-off-by: Ramneek Mehresh
Signed-off-by: Nikhil Badola
Reviewed-by: York Sun -
Fix following compile warnings
fsl_esdhc_spl.c: In function 'mmc_boot':
fsl_esdhc_spl.c:35:10: warning: unused variable 'byte_num' [-Wunused-variable]
fsl_esdhc_spl.c:35:7: warning: unused variable 'i' [-Wunused-variable]
fsl_esdhc_spl.c:34:8: warning: unused variable 'val' [-Wunused-variable]
fsl_esdhc_spl.c:33:6: warning: unused variable 'blklen' [-Wunused-variable]
fsl_esdhc_spl.c:105:7: warning: 'tmp_buf' may be used uninitialized in this
function [-Wuninitialized]Signed-off-by: Prabhakar Kushwaha
Reviewed-by: York Sun -
Put a delay of 5 millisecond after reset so that ULPI phy
gets enough time to come out of reset. Erratum A007075 applies
to following SOCs and their variants, if any
P1010 rev 1.0
B4860 rev 1.0, 2.0
P4080 rev 2.0, 3.0Signed-off-by: Nikhil Badola
Reviewed-by: York Sun -
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.Signed-off-by: York Sun
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In the current Datasheet for VSC8514 there is a mistake, saying that
the PHY id is 0x70570. The real value in the identifier registers is
0x70670. Linux PHY driver uses 0x70670 also.Signed-off-by: Codrin Ciubotariu
Cc: York Sun
Reviewed-by: York Sun -
For fsl-lsch3 NOR flash boot, IFC CS0 needs to be binded with address
within 32-bit at fist. After u-boot relocates to DDR, CS0 can be binded
to higher address to support large space.Signed-off-by: York Sun
CC: Prabhakar Kushwaha -
Modify code to adapt to both u-qe and qe.
U_QE is a kind of cutted QE.
the differences between U_QE and QE
1. UCC: U_QE supports 2 UCCs while QE supports up to 8 UCCs.
2. IMMR: have different immr base addr.
3. iopin: U_QE doesn't need to config iopin.Signed-off-by: Zhao Qiang
Reviewed-by: York Sun -
CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address.
Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address,
and CONFIG_SYS_QE_FW_ADDR for QE microcode address.Signed-off-by: Zhao Qiang
Reviewed-by: York Sun -
Set correct phy_type value for second USB controller.
This is required for supporting SOCs having 2 USB controllers
working simultaneously, one with UTMI phy and other with ULPI phySigned-off-by: Nikhil Badola
Reviewed-by: York Sun
20 Apr, 2014
1 commit
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This is dead hardware and no one is interested in making the
necessary changes for upcoming features like generic board or
driver model.Signed-off-by: Daniel Schwierzeck
Cc: Wolfgang Denk
19 Apr, 2014
1 commit
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Signed-off-by: David Mueller
Acked-by: Joe Hershberger
18 Apr, 2014
5 commits
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The ordering of accesses to the rx & tx descriptors is important, yet
the send & recv functions accessed them via regular structure accesses.
This leaves the compiler with the opportunity to reorder those accesses
or to hoist them outside of loops. Prevent that from happening by using
readl & writel to access the descriptors. As a nice bonus, this removes
the need for the driver to care about endianness.Signed-off-by: Paul Burton
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The RX buffers are invalidated when a packet is received, however they
were not suitably cache-line aligned. Allocate them seperately to the
pcnet_priv structure and align to ARCH_DMA_MINALIGN in order to ensure
suitable alignment for the cache invalidation, preventing anything else
being placed in the same lines & lost.Signed-off-by: Paul Burton
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The prior accesses to the descriptor rings & init block via cached
memory had a few issues:- The memory needs cache flushes or invalidation at the appropriate
times, but was not necessarily aligned on cache line boundaries.
This could lead to data being incorrectly lost or written back to
RAM at the wrong time.- There are points where ordering of writes to the memory is
important, but because it's cached memory the pcnet controller
would see cache lines written back ordered by address. This could
occasionally lead to hardware seeing descriptors in an incorrect
state.- Flushing the cache constantly is inefficient.
So, to avoid all of those issues simply access the descriptors & init
block via uncached memory. The MIPS-specific UNCACHED_SDRAM macro is
used to do this (retrieving an address in kseg1) as I could see no
existing generic solution. Since the MIPS Malta board is the only user
of the pcnet driver, hopefully this doesn't matter.Signed-off-by: Paul Burton
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Enough time has passed since this board was moved to Orphan. Remove.
- Remove board/lubbock/*
- Remove include/configs/lubbock.h
- Cleanup defined(CONFIG_LUBBOCK)
- Move the entry from boards.cfg to doc/README.scrapyardSigned-off-by: Masahiro Yamada
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Enough time has passed since these boards were moved to Orphan. Remove.
- Remove board/RPXlite/*
- Remove board/RPXClassic/*
- Remove include/configs/RPXlite.h
- Remove include/configs/RPXClassic.h
- Clean-up defined(CONFIG_RPXCLASSIC)
- Move the entry from boards.cfg to doc/README.scrapyardSigned-off-by: Masahiro Yamada
