18 Jan, 2020
1 commit
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At present panic() is in the vsprintf.h header file. That does not seem
like an obvious choice for hang(), even though it relates to panic(). So
let's put hang() in its own header.Signed-off-by: Simon Glass
[trini: Migrate a few more files]
Signed-off-by: Tom Rini
07 Jan, 2020
2 commits
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Add Cache Coherency Unit (CCU) driver.
CCU is to ensures consistency of shared data between multi masters
in the system.Driver initializes CCU's directories and coherency agent
interfaces in CCU IP.Signed-off-by: Ley Foon Tan
Reviewed-by: Simon Goldschmidt -
Add an option for building cache drivers in SPL.
Signed-off-by: Ley Foon Tan
Reviewed-by: Tom Rini
Reviewed-by: Simon Goldschmidt
03 Sep, 2019
3 commits
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Add a v5l2 cache controller driver that is usually found on
Andes RISC-V ae350 platform. It will parse the cache settings
from the dtb.In this version tag and data ram control timing can be adjusted
by the requirement from the dtb.Signed-off-by: Rick Chen
Cc: KC Lin
Reviewed-by: Bin Meng -
Add cache enable and disable ops for test coverage.
Signed-off-by: Rick Chen
Cc: KC Lin
Reviewed-by: Bin Meng -
Add cache enable/disable ops to the DM cache uclass driver
Signed-off-by: Rick Chen
Cc: KC Lin
Reviewed-by: Bin Meng
05 May, 2019
2 commits
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Add a PL310 cache controller driver that is usually found on
ARMv7(32-bit) devices. The driver configures the cache settings that can
be found in the device tree files.This initial revision only configures basic settings(data & instruction
prefetch, shared-override, data & tag latency). I believe these are the
settings that affect performance the most. Comprehensive settings can be
done by the OS.Reviewed-by: Simon Glass
Signed-off-by: Dinh Nguyen -
The cache UCLASS will be used for configure settings that can be found
in a CPU's L2 cache controller.Add a uclass and a test for cache.
Reviewed-by: Simon Glass
Signed-off-by: Dinh Nguyen
