25 Feb, 2016
2 commits
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PAMU driver basic support for usage in Secure Boot.
In secure boot PAMU is not in bypass mode. Hence to use
any peripheral (SEC Job ring in our case), PAMU has to be
configured.The patch reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3.
The Header file pamu.h and few functions in driver have been derived
from Freescale Libos.Signed-off-by: Ruchika Gupta
Signed-off-by: Aneesh Bansal
Reviewed-by: York Sun -
The output ring needs to be invalidated before enqueuing the job to SEC.
While allocation of space to output ring, it should be taken care that the
size is cacheline size aligned inorder to prevent invalidating valid data.The patch also correct the method of aligning end of structs while flushing caches
Since start = align(start_of_struct), it is incorrect to assign
end = align(start + struct_size). It should instead be,
end = align(start_of_struct + struct_size).Signed-off-by: Saksham Jain
Signed-off-by: Ruchika Gupta
Reviewed-by: York Sun
21 Feb, 2016
6 commits
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Introudce i.MX7 pinctrl driver support.
For now only i.MX7D supported.
There are two iomux controllers in i.MX7D, iomuxc and iomuxc_lpsr.
To iomuxc_lpsr, ZERO_OFFSET_VALID is set, means offset of mux_reg
and conf_reg can begin at 0.Signed-off-by: Peng Fan
Reviewed-by: Simon Glass -
Introduce pinctrl for i.MX6
1. pinctrl-imx.c is for common usage. It's used by i.MX6/7.
2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry.
3. To the pinctrl_ops implementation, only set_state is implemented.
To i.MX6/7, the pinctrl dts entry is as following:
&iomuxc {
pinctrl-names = "default";pinctrl_csi1: csi1grp {
fsl,pins = <
MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
>;
};[.....]
};
there is no property named function or groups. So pinctrl_generic_set_state
can not be used here.
5. This driver is a simple implementation for i.mx iomux controller,
only parse the fsl,pins property and write value to registers.
6. With DEBUG enabled, we can see log when "i2c bus 0":
"
set_state_simple op missing
imx_pinctrl_set_state: i2c1grp
mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f
write mux: offset 0x14c val 0x10
select_input: offset 0x5d8 val 0x1
write config: offset 0x3bc val 0x7f
mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f
write mux: offset 0x148 val 0x10
select_input: offset 0x5d4 val 0x1
write config: offset 0x3b8 val 0x7f
"
this means imx6 pinctrl driver works as expected.Signed-off-by: Peng Fan
Reviewed-by: Simon Glass -
Refactored data structure for CAAM's job ring and Secure Memory
to support i.MX7.The new memory map use macros to resolve SM's offset by version.
This will solve the versioning issue caused by the new version of
secure memory of i.MX7Signed-off-by: Ulises Cardenas
Reviewed-by: Stefano Babic -
The SMSC SIO1007 superio chipset integrates two ns16550 compatible
serial ports for legacy applications, 16 GPIO pins and some other
functionalities like power management.This adds a simple driver to enable serial port and handle GPIO.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
19 Feb, 2016
6 commits
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Due to introducing the new PLLB clock handle functions,
use these functions to clean up the PLLB enable/disable code.Signed-off-by: Wenyou Yang
Reviewed-by: Andreas Bießmann
Tested-by: Heiko Schocher -
Due to introducing the new UTMI PLL clock handle functions,
use these function to reduce the duplicated code.Signed-off-by: Wenyou Yang
Tested-by: Heiko Schocher
Reviewed-by: Andreas Bießmann -
Due to introducing the new peripheral clock handle functions,
use these functions to reduce the duplicated code.Signed-off-by: Wenyou Yang
Tested-by: Heiko Schocher
[fixup for missing clk.h in at91_emac.c]
Signed-off-by: Andreas Bießmann -
With commit a058052c [net: phy: do not read configuration register on
reset], phy_reset() will clear the BMCR register. Resulting in bit 12
being cleared (A/N enable). This leads to autonegotiation link problems,
at least on the Marvell Armada ClearFog board. I suspect that other
boards using this driver will be affected as well.At the of m88e1111s_config(), phy_reset() is called. This is not needed
for the PHY to load the changed configuration, as phy_reset() is called
a few lines before already. So lets call genphy_restart_aneg() here
instead to start the AN correctly.Tested on clearfog.
Signed-off-by: Stefan Roese
Cc: Stefan Agner
Cc: Hao Zhang
Cc: Michal Simek
Cc: Andy Fleming
Cc: Joe Hershberger
Acked-by: Joe Hershberger -
Instead of coding the soft PHY reset function multiple times in marvell.c,
lets call the common phy_reset() function from phy.c.Signed-off-by: Stefan Roese
Cc: Stefan Agner
Cc: Hao Zhang
Cc: Michal Simek
Cc: Andy Fleming
Cc: Joe Hershberger
Acked-by: Joe Hershberger
17 Feb, 2016
17 commits
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Use the driver-model PWM driver in preference to the old code.
Signed-off-by: Simon Glass
Acked-by: Anatolij Gustschin
Signed-off-by: Tom Warren -
Move this option to Kconfig and clean up the header files. Adjust the only
user (the LCD driver) to work with the new driver.Signed-off-by: Simon Glass
Signed-off-by: Tom Warren -
Join the two functions which decode the device tree and put them in the
ofdata_to_platdata() method.Signed-off-by: Simon Glass
Acked-by: Anatolij Gustschin
Signed-off-by: Tom Warren -
There is no need to have these in a separate file as they are not
referenced from anywhere else.Signed-off-by: Simon Glass
Acked-by: Anatolij Gustschin
Signed-off-by: Tom Warren -
We can move the static variables into the driver-private data.
Signed-off-by: Simon Glass
Acked-by: Anatolij Gustschin
Signed-off-by: Tom Warren -
Move this driver over to use driver model. This involves rearranging the
code somewhat. The effect is that everything is run from the probe() method.Boards which use this are fixed up, but only seaboard is tested.
Signed-off-by: Simon Glass
Acked-by: Anatolij Gustschin
Signed-off-by: Tom Warren -
We have a structure for the display panel and another for the controller.
There is some overlap between them. Merge them to simplify the driver.Signed-off-by: Simon Glass
Acked-by: Anatolij Gustschin
Signed-off-by: Tom Warren -
We can check this in Kconfig now.
Signed-off-by: Simon Glass
Acked-by: Anatolij Gustschin
Signed-off-by: Tom Warren -
At present we have code in arch/arm and code in drivers/video. Move it all
into drivers/video since it is a display driver and our current approach is
to put all driver code in drivers/.Make a few functions static now that they are not used outside the file.
Signed-off-by: Simon Glass
Acked-by: Anatolij Gustschin
Signed-off-by: Tom Warren -
This option refers only to the tegra20 video driver, so name it as such
to avoid confusion with tegra124.Also move this option to Kconfig.
Signed-off-by: Simon Glass
Acked-by: Anatolij Gustschin
Signed-off-by: Tom Warren -
Adjust the driver to use driver model. The SOR becomes a bridge device. We
use the normal simple_panel driver to handle the display itself. We also
need to enable some options such as regulators, PWMs and DM_VIDEO itself.Signed-off-by: Simon Glass
Acked-by: Anatolij Gustschin
Signed-off-by: Tom Warren -
There isn't a lot of benefit of have two separate files. With driver model
the code needs to be in the same driver, so it's better to have it in the
same file.Signed-off-by: Simon Glass
Acked-by: Anatolij Gustschin
Signed-off-by: Tom Warren -
This PWM supports four channels. The driver always uses the 32KHz clock,
and adjusts the duty cycle accordingly.Signed-off-by: Simon Glass
Signed-off-by: Tom Warren -
The tegra GPIO controller has two ways of reading the value of a GPIO. It
can supply the 'input' value (which is the value read from the pin) and the
'output' value (which is the value being driven from the pin. With a GPIO
set to output mode, the 'input' value is always low which is not very
useful.This has the unfortunate result that setting a GPIO high still leaves it
showing as low in the 'gpio status' command.Adjust the driver to check which direction the GPIO is set to, then read
the value from the appropriate register: 'input' for input GPIOs, 'output'
for output GPIOs.Signed-off-by: Simon Glass
Reviewed-by: Joe Hershberger
Signed-off-by: Tom Warren -
Fix the SoC names in two comments.
Signed-off-by: Simon Glass
Signed-off-by: Tom Warren -
This helps keep the display consistent. puts() is used when printing the
prompt, so is a useful way to make sure the current display contents is
visible.Signed-off-by: Simon Glass
Acked-by: Anatolij Gustschin
Signed-off-by: Tom Warren -
We need to add the base tables before adding the function tables. Fix the
init order so the keyboard scans keys correctly.Signed-off-by: Simon Glass
Signed-off-by: Tom Warren
14 Feb, 2016
3 commits
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Now, all this driver does can be covered by the generic EHCI driver
(drivers/usb/host/ehci-generic.c). UniPhier SoCs have switched to
use it. Delete this driver rather than bothering to convert it to
Driver Model.Signed-off-by: Masahiro Yamada
Acked-by: Marek Vasut -
This is the initial commit for the UniPhier clock drivers.
Currently, only the Media I/O clock is supported.Signed-off-by: Masahiro Yamada
13 Feb, 2016
6 commits
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Added initial nand driver support for arasan nand flash
controller.This supports nand erase,nand read, nand write
This uses the hardware ECC for read and write operations
ZynqMP uses this driver.Signed-off-by: Siva Durga Prasad Paladugu
[scottwood: Fix checkpatch warnings]
Signed-off-by: Scott Wood -
Add nand driver support for zynqmp. The Nand
controller used in ZynqMP is Arasan Nand Flash
controller.Signed-off-by: Siva Durga Prasad Paladugu
[scottwood: Fix checkpatch warning]
Signed-off-by: Scott Wood -
The allocation size is reduced from what was introduced from the
Linux kernel, as U-boot uses the statically allocated nand_info
instead of needing to dynamically allocate an mtd_info instance.Signed-off-by: Kevin Smith
Cc: Stefan Roese
Cc: Luka Perkov
Cc: Scott Wood -
Correct some pointer math in initialization. An offset was added
to a struct-typed pointer instead of one casted to a byte-size,
resulting in a much larger offset than intended.Signed-off-by: Kevin Smith
Cc: Stefan Roese
Cc: Luka Perkov
Cc: Scott Wood -
Correct a null pointer dereference in board_nand_init(). Zeroed
memory was allocated, then immediately dereferenced. The
dereference is completely removed, since this pointer is later
initialized in alloc_nand_resources.Signed-off-by: Kevin Smith
Cc: Stefan Roese
Cc: Luka Perkov
Cc: Scott Wood -
Fix error handling for mxs_nand_init.
The original error handling is wrong for err2 and err1.
Should first free desc[x], then free desc.This patch also correctly handle err3, should use
MXS_DMA_CHANNEL_AHB_APBH_GPMI0 as the check point.Cc: Stefano Babic
CC: Fabio Estevam
Cc: Scott Wood
Cc: Marek Vasut
Signed-off-by: Peng Fan
Reviewed-by: Marek Vasut
